WO2010059868A2 - Procédé et appareil de modification de profil de tranchée et de trou d'interconnexion - Google Patents
Procédé et appareil de modification de profil de tranchée et de trou d'interconnexion Download PDFInfo
- Publication number
- WO2010059868A2 WO2010059868A2 PCT/US2009/065208 US2009065208W WO2010059868A2 WO 2010059868 A2 WO2010059868 A2 WO 2010059868A2 US 2009065208 W US2009065208 W US 2009065208W WO 2010059868 A2 WO2010059868 A2 WO 2010059868A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- etchant
- trench structure
- sacrifice layer
- top opening
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/066—Patterning of the switching material by filling of openings, e.g. damascene method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
- H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
Definitions
- Embodiments of the present invention generally relate to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via.
- trench or via structures formed on a semiconductor substrate during fabrication become increasingly narrow and high in aspect ratio.
- Narrow opening and high aspect ratio usually present difficulties and challenges for subsequent material filling process.
- voids are more likely to form in the filling material because the narrow openings would be pinched off during filling process.
- the liner, barrier or seed layer is usually deposited on the trench or via structure using a physical vapor deposition (PVD) process.
- PVD physical vapor deposition
- overhangs usually form near an entrance of the trench or via. The overhangs worsen the pinch off in the subsequent material filling causing more voids formed in the filling.
- Figures 1A-1 B schematically illustrate problems in trench and via filling.
- Figure 1A schematically illustrates a partial sectional side view of a substrate 10.
- a trench structure 2 is formed in a first material 1.
- a barrier layer 3 is then deposited over the trench structure 2.
- the barrier layer 3 is thicker near an entrance 8 of the trench structure 2 and forms overhangs 4 near the entrance 8. The overhangs 4 further narrow the entrance 8.
- Figure 1 B schematically illustrates a material filling result of the substrate 10 of Figure 1A.
- the entrance 8 is closed up by a filling material 5 prior to filling in the rest of the trench structure 2 forming a void 6 in the trench structure 2.
- the void 6 is usually undesirable especially when the filling material 5 is a conductive material (copper or aluminum) for interconnect, Germanium-Selenium-Tellurium (GST) fill for phase change memory cell, gate metal filling for metal gates.
- GST Germanium-Selenium-Tellurium
- Conventional fabrication process generally uses a sputtering process to modify the entrance 8 prior to depositing the filling material 5.
- positive ions 6, such as positive argon ions, generated in a plasma chamber are accelerated towards the substrate 10.
- the positive ions 6 gain momentum during acceleration and strike top surfaces of the substrate 10.
- the ions 6 physically dislodged the overhangs 4 to open up the entrance 8, as show in modified profile 7.
- the ions 6 also strike other areas outside the overhangs 4 damaging the substrate 10.
- the dislodged particles generated during sputtering require additional cleaning process and may still become potential source of contamination for subsequent processing.
- Embodiments of the present invention generally relate to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via.
- One embodiment provides a method for processing a substrate comprising forming a trench structure in the substrate, wherein sidewalls of the trench structure comprises a first material, forming a sacrifice layer to pinch off a top opening of the trench structure by exposing the substrate to an etchant, wherein the sacrifice layer comprises a by-product of a reaction between the etchant and the first material, allowing the etchant to further react with the first material by continuously exposing the substrate to the etchant, and removing the sacrifice layer from the substrate.
- Another embodiment provides a method for processing a substrate comprising forming a trench structure on the substrate, wherein sidewalls of the trench structure comprises a first material, widening a top opening of the trench structure, wherein widening the upper opening comprises forming a sacrifice layer to pinch off the top opening of the trench structure by exposing the substrate to an etchant, wherein the sacrifice layer comprises a by-product of an reaction between the etchant and the first material, allowing the etchant to further react with the first material by continuously exposing the substrate to the etchant, and removing the sacrifice layer from the substrate, depositing a second material to fill the trench structure.
- Yet another embodiment provides a method for processing a substrate comprising positioning the substrate in a processing chamber, wherein the substrate has a trench structure, and sidewalls of the trench structure comprise a first material, flowing a first processing gas to the processing chamber to form a sacrifice layer to pinch off a top opening of the trench structure, continuing the flow of the first processing gas after the top opening has been pinched off, and annealing the substrate to remove the sacrifice layer from the trench structure.
- Figures 1 A-1 B schematically illustrate problems in trench and via filling.
- Figure 1C schematically illustrates a conventional method for modifying trench and via profile.
- Figures 2A-2B schematically illustrate a method for modifying a trench profile prior to material filling in accordance with one embodiment of the present invention.
- Figure 3 is a schematic flow chart showing a process for modifying a trench profile in accordance with one embodiment of the present invention.
- Figure 4 is a schematic side view of a chamber for modifying a trench profile in accordance with one embodiment of the present invention.
- Figures 5A-5C schematically illustrate a method for modifying a trench profile in accordance with another embodiment of the present invention.
- Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via.
- One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a trench structure by exposing the trench structure to an etchant.
- the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.
- the sacrifice layer restrains the access of the etchant from sidewalls of the trench structure allowing more material removed near the top opening of the trench structure.
- the profile of the trench structure is modified to have a widened opening after removing the sacrifice layer from the substrate.
- a dry etching method is used to form the sacrifice layer.
- the sacrifice layer can be removed by annealing in the same dry etching chamber, thus, increasing efficiency and reducing cross contamination.
- Methods and apparatus of the present invention can be used to modify profile of bare trench and via structures, on trench and via structures having a liner, a barrier and/or a seed layer deposited thereon.
- Figures 2A-2B schematically illustrate a method for modifying a trench profile prior to material filling in accordance with one embodiment of the present invention.
- Figure 3 is a schematic flow chart showing a process 30 for modifying a trench profile shown in Figures 2A-2B.
- Block 32 of the process 30 comprises forming a trench structure 22 in a base layer 21 of a substrate 20 as shown in Figure 2A.
- the base layer 21 hence, sidewalls of the trench structure 22 comprise a first material.
- forming the trench structure 22 may comprise depositing a liner, barrier or seed layer 23 having the first material may be deposited over the substrate 20.
- the trench structure 22 has overhangs 24a formed near a top opening 24.
- Block 34 of the process 30 comprises forming a sacrifice layer 25 to pinch off the top opening 24 of the trench structure 22 by exposing the substrate 20 to an etchant.
- the etchant is configured to etch away the first material by reacting with the first material and to generating a by-product from reaction with the first material.
- the sacrifice layer 25 comprises the by-product generated from reaction between the etchant and the first material.
- forming the sacrifice layer 25 comprises increasing a rate of reaction between the first material and the etchant. The increased reaction rate between the first material and the etchant causes the by-product to form quickly near the top opening 24 before the by-product can be evenly formed within the trench structure 22.
- increasing the reaction rate between the first material and the etchant may be achieved by increasing a flow rate of one or more processing gas of the etchant.
- forming the sacrifice layer 25 comprises determining the reaction rate between the first material and the etchant according to a target trench profile.
- a higher reaction rate corresponds to a higher ratio of removal amount between a top portion of the trench structure 22 and a lower portion of the trench structure 22.
- a lower reaction rate corresponds to a lower ratio of removal amount between the top portion and the lower portion. Accordingly, increasing the reaction rate increases an opening angle of the sidewalls and reducing the reaction rate reduces the opening angel of the sidewalls.
- Block 36 of the process 30 comprising allowing the etchant to further reacting with the first material by continuously exposing the substrate 20 to the etchant, as shown in Figure 2A.
- active species 26 in the etchant may still be able to diffuse through the sacrifice layer 25 from a top surface of the sacrifice layer 25 and react with the first material underneath.
- diffusion distance varies significantly along sidewalls of the trench structure 22. Therefore, this leads to fast etching around the top opening 24 significant reduced etching down the sidewalls of the trench structure 22.
- flow rate of the etchant may remain the same after the sacrifice layer 25 has pinched off the top opening 24. In another embodiment, flow rate of the etchant may be adjusted after the pinch off. [0034] In one embodiment, a desired top opening widening can be achieved by varying etching time.
- Block 38 of the process 30 comprises removing the sacrifice layer 25 and exposing a modified profile 27 of the trench structure 22.
- removing the sacrifice layer 25 may comprise annealing the substrate 20 to vaporize the sacrifice layer 25. In one embodiment, removing the sacrifice layer 25 can be performed in the same chamber where forming the sacrifice layer 25 and continued etching are performed.
- removing the sacrifice layer 25 comprising dissolving the sacrifice layer 25 in a solvent.
- the solvent may be water.
- Figure 2A shows an example of a trench structure having overhangs formed near a top opening
- embodiments of the present invention may be applied to modify trench structure without overhangs, such as trench structures with relatively straight walls.
- any etching methods that produce a removable byproduct can be used with embodiments of the present invention.
- Particularly etchant may be selected according to materials to be etched. Composition of etchant may also be determined by process requirement.
- a dry etching method is used in accordance with embodiment of the present invention.
- Embodiments of the present invention may use an etchant may be a fluorine, nitrogen, and hydrogen containing source.
- the etchant comprises one of a mixture of nitrogen trifluoride (NF 3 ) and ammonia (NH 3 ), a mixture of nitrogen trifluoride (NF 3 ) and hydrogen (H 2 ), a mixture of nitrogen trifluoride (NF 3 ), hydrogen (H 2 ), and nitrogen (N 2 ), a mixture of nitrogen trifluoride (NH 3 ) and hydrogen fluoride (HF), or other similar fluorine, nitrogen, and hydrogen containing source.
- the etchant comprises a fluorine containing source, such as CIF3, CH3F, CHF3, and similar compounds.
- One embodiment of the present invention comprises generating a plasma of a drying etching etchant comprising a mixture of nitrogen trifluoride (NF3) and ammonia (NH3), and exposing the plasma of the nitrogen trifluoride and ammonia to modify trench and/or via structures having sidewalls comprising silicon oxide, silicon, or silicon nitride.
- the plasma may be generated remotely and flown to an etching chamber.
- the plasma may be generated in-situ in an etching chamber.
- Figure 4 is a schematic side view of a processing chamber 100 for modifying a trench profile in accordance with one embodiment of the present invention.
- the processing chamber 100 comprises a lid assembly 200 disposed at an upper end of a chamber body 112, and a support assembly 300 at least partially disposed within the chamber body 112.
- the processing chamber also includes a remote plasma generator 140 having a remote electrode with a U-shaped cross section.
- the processing chamber 100 and the associated hardware are preferably formed from one or more process-compatible materials, for example, aluminum, anodized aluminum, nickel plated aluminum, nickel plated aluminum 6061 -T6, stainless steel, as well as combinations and alloys thereof.
- the support assembly 300 is partially disposed within the chamber body 112.
- the support assembly 300 is raised and lowered by a shaft 314 which is enclosed by bellows 333.
- the chamber body 112 includes a slit valve opening 160 formed in a sidewall thereof to provide access to the interior of the chamber 100.
- the slit valve opening 160 is selectively opened and closed to allow access to the interior of the chamber body 112 by a wafer handling robot (not shown). Wafer handling robots are well known to those with skill in the art, and any suitable robot may be used.
- a wafer can be transported in and out of the process chamber 100 through the slit valve opening 160 to an adjacent transfer chamber and/or load-lock chamber (not shown), or another chamber within a cluster tool.
- Illustrative cluster tools include but are not limited to the PRODUCERTM, CENTURATM, ENDURATM, and ENDURASLTM platforms available from Applied Materials, Inc. of Santa Clara, CA.
- the chamber body 112 also includes a channel 113 formed therein for flowing a heat transfer fluid therethrough.
- the heat transfer fluid can be a heating fluid or a coolant and is used to control the temperature of the chamber body 112 during processing and substrate transfer.
- the temperature of the chamber body 112 is important to prevent unwanted condensation of the gas or byproducts on the chamber walls.
- Exemplary heat transfer fluids include water, ethylene glycol, or a mixture thereof.
- An exemplary heat transfer fluid may also include nitrogen gas.
- the chamber body 112 further includes a liner 133 that surrounds the support assembly 300, and is removable for servicing and cleaning.
- the liner 133 is preferably made of a metal such as aluminum, or a ceramic material. However, any process compatible material may be used.
- the liner 133 may be bead blasted to increase the adhesion of any material deposited thereon, thereby preventing flaking of material which results in contamination of the chamber 100.
- the liner 133 typically includes one or more apertures 135 and a pumping channel 129 formed therein that is in fluid communication with a vacuum system. The apertures 135 provide a flow path for gases into the pumping channel 129, and the pumping channel provides a flow path through the liner 133 so the gases can exit the chamber 100.
- the vacuum system may comprise a vacuum pump 125 and a throttle valve 127 to regulate flow of gases within the chamber 100.
- the vacuum pump 125 is coupled to a vacuum port 131 disposed on the chamber body 112, and is in fluid communication with the pumping channel 129 formed within the liner 133.
- the vacuum pump 125 and the chamber body 112 are selectively isolated by the throttle valve 127 to regulate flow of the gases within the chamber 100.
- gas and “gases” are used interchangeably, unless otherwise noted, and refer to one or more precursors, reactants, catalysts, carrier, purge, cleaning, combinations thereof, as well as any other fluid introduced into the chamber body 112.
- the lid assembly 200 comprises a number of components stacked together.
- the lid assembly 200 comprises a lid rim 210, gas delivery assembly 220, and a top plate 250.
- the lid rim 210 is designed to hold the weight of the components making up the lid assembly 200 and is coupled to an upper surface of the chamber body 112 to provide access to the internal chamber components.
- the gas delivery assembly 220 is coupled to an upper surface of the lid rim 210 and is arranged to make minimum thermal contact therewith.
- the components of the lid assembly 200 are preferably constructed of a material having a high thermal conductivity and low thermal resistance, such as an aluminum alloy with a highly finished surface, for example.
- the thermal resistance of the components is less than about 5x10 "4 m 2 K/W.
- the gas delivery assembly 220 may comprise a gas distribution plate
- a gas supply panel (not shown) is typically used to provide the one or more gases to the chamber 100.
- the particular gas or gases that are used depend upon the process to be performed within the chamber 100.
- the typical gases include one or more precursors, reductants, catalysts, carriers, purge, cleaning, or any mixture or combination thereof.
- the one or more gases are introduced to the chamber 100 into the lid assembly 200 and then into the chamber body 112 through the gas delivery assembly 220.
- An electronically operated valve and/or flow control mechanism (not shown) may be used to control the flow of gas from the gas supply into the chamber 100.
- the gas is delivered from the gas supply panel to the chamber 100 where the gas line tees into two separate gas lines which feed gases to the chamber body 112 as described above.
- the lid assembly 200 may further include an electrode 240 to generate a plasma of reactive species within the lid assembly 200.
- the electrode 240 is supported on the top plate 250 and is electrically isolated therefrom.
- An isolator filler ring (not shown) is disposed about a lower portion of the electrode 240 separating the electrode 240 from the top plate 250.
- annular isolator (not shown) is disposed about an upper portion of the isolator filler ring and rests on an upper surface of the top plate 250, as shown in Figure 3.
- An annular insulator (not shown) is then disposed about an upper portion of the electrode 240 so that the electrode 240 is electrically isolated from the other components of the lid assembly 200.
- Each of these rings, the isolator filler and annular isolators can be made from aluminum oxide or any other insulative, process compatible material.
- the electrode 240 is coupled to a power source 340 while the gas delivery assembly 220 is connected to ground. Accordingly, a plasma of the one or more process gases is struck in the volume formed between the electrode 240 and the gas delivery assembly 220.
- the plasma may also be contained within the volumes formed by blocker plates. In the absence of a blocker plate assembly, the plasma is struck and contained between the electrode 240 and the gas delivery assembly 220. In either embodiment, the plasma is well confined or contained within the lid assembly 200.
- Any power source capable of activating the gases into reactive species and maintaining the plasma of reactive species may be used.
- radio frequency (RF), direct current (DC), alternating current (AC), or microwave (MW) based power discharge techniques may be used.
- the activation may also be generated by a thermally based technique, a gas breakdown technique, a high intensity light source (e.g., UV energy), or exposure to an x-ray source.
- a remote activation source may be used, such as a remote plasma generator, to generate a plasma of reactive species which are then delivered into the chamber 100.
- Exemplary remote plasma generators are available from vendors such as MKS Instruments, Inc. and Advanced Energy Industries, Inc.
- an RF power supply is coupled to the electrode 240.
- the gas delivery assembly 220 may be heated depending on the process gases and operations to be performed within the chamber 100.
- a heating element 270 such as a resistive heater for example, is coupled to the gas delivery assembly 220.
- the heating element 270 is a tubular member and is pressed into an upper surface of the gas delivery assembly 220.
- the upper surface of the gas delivery assembly 220 includes a groove or recessed channel having a width slightly smaller than the outer diameter of the heating element 270, such that the heating element 270 is held within the groove using an interference fit.
- the heating element 270 regulates the temperature of the gas delivery assembly 220 since the components of the delivery assembly 220, including the gas delivery assembly 220 and the blocker assembly 230 are each conductively coupled to one another. Additional details of the processing chamber may be found in United States Patent Application Number 11/063,645, filed February 22, 2005 which is incorporated by reference herein.
- the processing chamber 100 is particularly useful for performing a plasma assisted dry etching process that requires heating and cooling of the substrate surface without breaking vacuum.
- the processing chamber 100 may be used to selectively remove one or more oxides on the substrate.
- the processing chamber 100 is advantageous for any dry etch process that benefits from a plasma treatment in addition to both substrate heating and cooling all within a single processing environment, including an anneal process.
- the dry etch process begins by placing a substrate 110, such as a semiconductor substrate for example, into the processing chamber 100.
- the substrate is typically placed into the chamber body 112 through the slit valve opening 160 and disposed on the upper surface of the support member 310.
- the substrate 110 may be chucked to the upper surface of the support member 310.
- the substrate 110 is chucked to the upper surface of the support member 310 by pulling a vacuum.
- the support member 310 is then lifted to a processing position within the chamber body 112, if not already in a processing position.
- the chamber body 112 is preferably maintained at a temperature of between 5O 0 C and 8O 0 C, more preferably at about 65 0 C. This temperature of the chamber body 112 is maintained by passing a heat transfer medium through the channel 113.
- the substrate 110 is cooled below 65°C, such as between 15°C and
- the substrate is maintained below room temperature. In another embodiment, the substrate is maintained at a temperature of between 22 0 C and 4O 0 C. Typically, the support member 310 is maintained below about 22 0 C to reach the desired substrate temperatures specified above.
- the coolant is passed through the fluid channel formed within the support assembly 300. A continuous flow of coolant is preferred to better control the temperature of the support member 310.
- the coolant is preferably 50 percent by volume ethylene glycol and 50 percent by volume water. Of course, any ratio of water and ethylene glycol can be used so long as the desired temperature of the substrate is maintained.
- An etching gas mixture is introduced to the chamber 100 for selectively removing various oxides on a surface of the substrate 110.
- ammonia and nitrogen trifluoride gases are then introduced into the chamber 100 to form the etching gas mixture.
- the amount of each gas introduced into the chamber is variable and may be adjusted to accommodate, for example, the thickness of the oxide layer to be removed, the geometry of the substrate being cleaned, the volume capacity of the plasma, the volume capacity of the chamber body 112, as well as the capabilities of the vacuum system coupled to the chamber body 112.
- the ratio of the etching gas mixture may be predetermined to selectively remove various oxides on the substrate surface.
- the ratio of ingredient in the etching gas mixture may be adjusted to uniformly remove various oxides, such as thermal oxides, deposited oxides, and/or native oxides.
- molar ratio of ammonia to nitrogen triflouride in the etching gas mixture may be set to uniformly remove various oxides.
- the gases are added to provide a gas mixture having at least a 1 :1 molar ratio of ammonia to nitrogen trifluoride.
- the molar ratio of the gas mixture is at least about 3 to 1 (ammonia to nitrogen trifluoride).
- the gases are introduced in the chamber 100 at a molar ratio of from 5:1 (ammonia to nitrogen trifluoride) to 30:1. More preferably, the molar ratio of the gas mixture is of from about 5 to 1 (ammonia to nitrogen trifluoride) to about 10 to 1. The molar ratio of the gas mixture may also fall between about 10:1 (ammonia to nitrogen trifluoride) and about 20:1.
- a purge gas or carrier gas may also be added to the etching gas mixture.
- Any suitable purge/carrier gas may be used, such as argon, helium, hydrogen, nitrogen, or mixtures thereof, for example.
- the overall etching gas mixture is from about 0.05% to about 20% by volume of ammonia and nitrogen trifluoride. The remainder being the carrier gas.
- the purge or carrier gas is first introduced into the chamber body 112 before the reactive gases to stabilize the pressure within the chamber body 112.
- the operating pressure within the chamber body 112 can be variable. Typically, the pressure is maintained between about 500 mTorr and about 30 Torr. Preferably, the pressure is maintained between about 1 Torr and about 10 Torr. More preferably, the operating pressure within the chamber body 112 is maintained between about 3 Torr and about 6 Torr.
- An RF power of from about 5 and about 600 Watts is applied to the electrode 240 to ignite a plasma of the gas mixture within the volumes 261 , 262, and 263 contained in the gas delivery assembly 220.
- the RF power is less than 100 Watts. More preferable is that the frequency at which the power is applied is very low, such as less than 100 kHz. Preferably, the frequency ranges from about 50 kHz to about 90 kHz.
- the plasma energy dissociates the ammonia and nitrogen trifluoride gases into reactive species that combine to form a highly reactive ammonia fluoride (NH4F) compound and/or ammonium hydrogen fluoride (NH4F HF) in the gas phase. These molecules then flow through the gas delivery assembly 220 via the holes 225A of the gas distribution plate 225 to react with the substrate surface to be processed.
- the carrier gas is first introduced into the chamber 100, a plasma of the carrier gas is generated, and then the reactive gases, ammonia and nitrogen trifluoride, are added to the plasma.
- the etchant gas NH4F and/or NH4F HF, reacts with the silicon oxide surface to form ammonium hexafluorosilicate (NH4)2SiF6, NH3, and H2O products.
- the NH3, and H2O are vapors at processing conditions and removed from the chamber 100 by the vacuum pump 125.
- the volatile gases flow through the apertures 135 formed in the liner 133 into the pumping channel 129 before the gases exit the chamber 100 through the vacuum port 131 into the vacuum pump 125.
- a thin film of (NH4)2SiF6 is left behind on the substrate surface.
- the support member 310 may be elevated to an anneal position in close proximity to the heated gas distribution plate 225.
- the heat radiated from the gas distribution plate 225 may dissociate or sublimate the thin film of (NH4)2SiF6 into volatile SiF4, NH3, and HF products. These volatile products are then removed from the chamber 100 by the vacuum pump 125 as described above.
- a temperature of 75°C or more is used to effectively sublimate and remove the thin film from the substrate 110.
- a temperature of 100 0 C or more is used, such as between about 115°C and about 200 0 C.
- the thermal energy to dissociate the thin film of (NH4)2SiF6 into its volatile components is convected or radiated by the gas distribution plate 225.
- the heating element 270 is directly coupled to the distribution plate 225, and is activated to heat the distribution plate 225 and the components in thermal contact therewith to a temperature between about 75°C and 250 0 C.
- the distribution plate 225 is heated to a temperature of between 100 0 C and 15O 0 C, such as about 12O 0 C.
- the distance between the upper surface of the substrate 110 having the thin film thereon and the distribution plate 225 is not critical and is a matter of routine experimentation. A person of ordinary skill in the art can easily determine the spacing required to efficiently and effectively vaporize the thin film without damaging the underlying substrate. It is believed, however, that a spacing of between about 0.254 mm (10 mils) and 5.08 mm (200 mils) is effective.
- the processing chamber 100 is purged and evacuated.
- the processed substrate is then removed from the chamber body 112 by lowering the support assembly 300 to the transfer position, de-chucking the substrate, and transferring the substrate through the slit valve opening 160.
- a gas mixture of 2 seem of NF3, 10 seem of NH3 and 2,500 seem of argon was introduced into a vacuum chamber.
- a plasma of the gas mixture was ignited using 100 Watts of power.
- 1 ,500 seem of argon is supplied to a lower portion of the chamber for bottom purge.
- 50 seem of argon is supplied to near the edge region of the substrate support for edge purge.
- the chamber pressure was maintained at about 6 Torr, and the substrate temperature was about 22°C.
- the substrate was etched for 120 seconds.
- the spacing between the substrate and a heated chamber lid was 750 mil and the lid temperature was 120 0 C.
- the substrate was annealed for about 60 seconds. About 50 angstroms of material was removed from the substrate surface. No anneal effect was observed. The etch rate was about 0.46 angstroms per second (28 A/min). The observed etch uniformity was about 5 % for the 50 A etch.
- Figures 5A-5B schematically illustrate modifying a trench profile in accordance with another embodiment of the present invention.
- a trench structure 52 is formed in a substrate 50.
- the trench structure 52 is formed through a first layer 53 comprising a first material, and into a second layer 51 comprising a second material.
- Sidewalls 52a of the trench structure 52 comprise the first material in an upper portion and the second material in a lower portion.
- a sacrifice layer 54 is formed over the substrate 50 to pinch off a top opening 52b of the trench structure 52 by exposing the substrate 50 to an etchant.
- the etchant is configured to etch both the first material and the second material by reacting with the first and second materials and to generating byproducts from reactions with the first material and second material.
- the sacrifice layer 54 comprises the by-products generated from reactions between the etchant and the first material and between the etchant and the second material.
- the etchant etches the first material much faster than the etchant etches the second material. As shown in Figure 5A, the etchant reacts to the first material fast and the sacrifice layer 54 pinches off the top opening 52b comprising the first material, while the etchant reacts relative slow with the second material and the sacrifice layer 54 is very thin down the bottom portion of the trench structure 52.
- the first material comprises silicon oxide
- the second material comprises a low-k material
- the etchant comprises a mixture of ammonia and nitrogen trifluoride which etches silicon oxide much faster than it etches low-k material.
- the etchant may be continuously flown the substrate 50 to further react with the first material and the second material by diffusing through the sacrifice layer 54. According, more material can be etched. However, the etching rate slows down along the sidewalls 52. In one embodiment, etching time and/or etchant flow rate may be varied for an ideal trench widening.
- the sacrifice layer 54 is removed exposing a modified trench profile 57 as shown in Figure 5B.
- the original trench profile is shown in dashed line of Figure 5B. Comparing the original trench profile and the modified trench profile 57, it shows that more material has been removed from the upper portion of the trench structure 52, rendering a widened top opening.
- formation of the sacrifice layer 54, continued etching, and removal of the sacrifice layer 54 may be performed in the same processing chamber, such as the processing chamber 100 of Figure 4.
- Figure 5C schematically illustrates the substrate 50 a subsequent formation of a liner film 55 and a filling material 56.
- the widened trench profile allows the filling material 56 to form in the trench structure 52 without formation of voids.
- Embodiments of the present invention can be used in any situation that calls for trench and/or via profile modification.
- embodiments of the present invention can be used to modify trench and via profile prior to depositing a conductive material, such as copper or aluminum, to form chip interconnection.
- Embodiments of the present invention can also be used to modify trench and via profile prior to Germanium-Selenium-Tellurium (GST) filling in manufacturing phase change memory cells.
- GST Germanium-Selenium-Tellurium
- Embodiments of the present invention can also be used to modify trench and/or via profile prior to gate metal filling in fabricating transistors.
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200980147109.5A CN102224573B (zh) | 2008-11-24 | 2009-11-19 | 用于沟槽与介层洞轮廓修饰的方法与设备 |
JP2011537631A JP5319782B2 (ja) | 2008-11-24 | 2009-11-19 | トレンチ及びビアの断面形状を変形させる方法及び装置 |
KR1020117014410A KR101148252B1 (ko) | 2008-11-24 | 2009-11-19 | 트렌치 및 비아 프로파일 변형 장치 및 방법 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11753108P | 2008-11-24 | 2008-11-24 | |
US61/117,531 | 2008-11-24 | ||
US12/620,799 US7994002B2 (en) | 2008-11-24 | 2009-11-18 | Method and apparatus for trench and via profile modification |
US12/620,799 | 2009-11-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010059868A2 true WO2010059868A2 (fr) | 2010-05-27 |
WO2010059868A3 WO2010059868A3 (fr) | 2010-08-19 |
Family
ID=42196677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2009/065208 WO2010059868A2 (fr) | 2008-11-24 | 2009-11-19 | Procédé et appareil de modification de profil de tranchée et de trou d'interconnexion |
Country Status (6)
Country | Link |
---|---|
US (2) | US7994002B2 (fr) |
JP (2) | JP5319782B2 (fr) |
KR (1) | KR101148252B1 (fr) |
CN (2) | CN102224573B (fr) |
TW (1) | TWI413179B (fr) |
WO (1) | WO2010059868A2 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109706066A (zh) * | 2018-12-29 | 2019-05-03 | 赛纳生物科技(北京)有限公司 | 基因测序芯片微坑表面修饰方法 |
US11264248B2 (en) | 2018-12-06 | 2022-03-01 | Tokyo Electron Limited | Etching method and substrate processing apparatus |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009152108A2 (fr) * | 2008-06-10 | 2009-12-17 | Advanced Technology Materials, Inc. | Utilisation d'une couche d'isolation de ge et as sur un alliage sbxtey ou gextey pour empêcher l'intéraction de te provenant de sbxtey et gextey entraînant une augmentation de la teneur en te et de la cristallinité du film |
US7994002B2 (en) * | 2008-11-24 | 2011-08-09 | Applied Materials, Inc. | Method and apparatus for trench and via profile modification |
JP5703590B2 (ja) * | 2010-05-10 | 2015-04-22 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
GB2487716B (en) * | 2011-01-24 | 2015-06-03 | Memsstar Ltd | Vapour Etch of Silicon Dioxide with Improved Selectivity |
US8334198B2 (en) * | 2011-04-12 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a plurality of gate structures |
CN102800577B (zh) * | 2011-05-26 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | 金属栅极及mos晶体管的形成方法 |
US8815734B2 (en) | 2011-11-07 | 2014-08-26 | International Business Machines Corporation | Use of gas cluster ion beam to reduce metal void formation in interconnect structures |
CN102709188A (zh) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | 一种改善侧墙氮化硅不同区域的厚度均匀性的方法 |
CN102709173A (zh) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | 一种改善侧墙氮化硅不同区域的厚度均匀性的方法 |
JP2015012243A (ja) * | 2013-07-01 | 2015-01-19 | 東京エレクトロン株式会社 | 被処理体の処理方法 |
CN104425710B (zh) * | 2013-08-20 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | 相变存储器及其形成方法 |
US8980758B1 (en) * | 2013-09-17 | 2015-03-17 | Applied Materials, Inc. | Methods for etching an etching stop layer utilizing a cyclical etching process |
JP6405958B2 (ja) * | 2013-12-26 | 2018-10-17 | 東京エレクトロン株式会社 | エッチング方法、記憶媒体及びエッチング装置 |
WO2015199640A1 (fr) * | 2014-06-23 | 2015-12-30 | Applied Materials, Inc. | Procédé pour le dépôt d'une couche dans un trou d'interconnexion ou une tranchée, et produits obtenus par ce procédé |
CN105742231B (zh) * | 2014-12-11 | 2020-04-24 | 中国科学院微电子研究所 | 形成纳米线阵列的方法 |
CN106033714A (zh) * | 2015-03-10 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US9502303B2 (en) * | 2015-04-09 | 2016-11-22 | United Microelectronics Corp. | Method for manufacturing semiconductor device with a barrier layer having overhung portions |
CN108780735B (zh) * | 2016-03-13 | 2023-04-21 | 应用材料公司 | 用于间隔件应用的氮化硅膜的选择性沉积 |
US10229832B2 (en) * | 2016-09-22 | 2019-03-12 | Varian Semiconductor Equipment Associates, Inc. | Techniques for forming patterned features using directional ions |
CN107611007A (zh) * | 2017-08-24 | 2018-01-19 | 长江存储科技有限责任公司 | 一种深沟槽的预清洗方法及3d nand制备工艺 |
US10269559B2 (en) * | 2017-09-13 | 2019-04-23 | Lam Research Corporation | Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer |
US10170300B1 (en) * | 2017-11-30 | 2019-01-01 | Tokyo Electron Limited | Protective film forming method |
US11195759B2 (en) * | 2018-11-30 | 2021-12-07 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and method for making |
CN109545963B (zh) * | 2018-12-12 | 2022-09-30 | 北京时代全芯存储技术股份有限公司 | 制造相变化记忆体的方法 |
US11830725B2 (en) | 2020-01-23 | 2023-11-28 | Applied Materials, Inc. | Method of cleaning a structure and method of depositing a capping layer in a structure |
KR20220041358A (ko) | 2020-09-25 | 2022-04-01 | 에스케이하이닉스 주식회사 | 반도체장치 및 그 제조 방법 |
CN113506771B (zh) * | 2021-07-23 | 2022-12-09 | 长江存储科技有限责任公司 | 半导体结构的制作方法以及半导体结构 |
US20230136499A1 (en) * | 2021-10-31 | 2023-05-04 | Applied Materials, Inc. | Selective Passivation Of Damaged Nitride |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6335261B1 (en) * | 2000-05-31 | 2002-01-01 | International Business Machines Corporation | Directional CVD process with optimized etchback |
US20020137337A1 (en) * | 2001-03-23 | 2002-09-26 | Jiong-Ping Lu | Use of a sacrificial layer to facilitate metallization for small features |
US20060223323A1 (en) * | 2001-10-09 | 2006-10-05 | Liang-Yuh Chen | Method of forming an interconnect structure |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4784720A (en) * | 1985-05-03 | 1988-11-15 | Texas Instruments Incorporated | Trench etch process for a single-wafer RIE dry etch reactor |
US4807016A (en) * | 1985-07-15 | 1989-02-21 | Texas Instruments Incorporated | Dry etch of phosphosilicate glass with selectivity to undoped oxide |
DE3613181C2 (de) * | 1986-04-18 | 1995-09-07 | Siemens Ag | Verfahren zum Erzeugen von Gräben mit einstellbarer Steilheit der Grabenwände in aus Silizium bestehenden Halbleitersubstraten |
DE3884653T2 (de) * | 1987-04-03 | 1994-02-03 | Fujitsu Ltd | Verfahren und Vorrichtung zur Gasphasenabscheidung von Diamant. |
US5030319A (en) * | 1988-12-27 | 1991-07-09 | Kabushiki Kaisha Toshiba | Method of oxide etching with condensed plasma reaction product |
US5118384A (en) * | 1990-04-03 | 1992-06-02 | International Business Machines Corporation | Reactive ion etching buffer mask |
US5578130A (en) * | 1990-12-12 | 1996-11-26 | Semiconductor Energy Laboratory Co., Ltd. | Apparatus and method for depositing a film |
US5282925A (en) * | 1992-11-09 | 1994-02-01 | International Business Machines Corporation | Device and method for accurate etching and removal of thin film |
US5505816A (en) | 1993-12-16 | 1996-04-09 | International Business Machines Corporation | Etching of silicon dioxide selectively to silicon nitride and polysilicon |
US5846375A (en) * | 1996-09-26 | 1998-12-08 | Micron Technology, Inc. | Area specific temperature control for electrode plates and chucks used in semiconductor processing equipment |
TW304293B (en) * | 1996-11-18 | 1997-05-01 | United Microelectronics Corp | Manufacturing method for shallow trench isolation |
US6054377A (en) * | 1997-05-19 | 2000-04-25 | Motorola, Inc. | Method for forming an inlaid via in a semiconductor device |
US6706334B1 (en) * | 1997-06-04 | 2004-03-16 | Tokyo Electron Limited | Processing method and apparatus for removing oxide film |
US6232233B1 (en) * | 1997-09-30 | 2001-05-15 | Siemens Aktiengesellschaft | Methods for performing planarization and recess etches and apparatus therefor |
US6635185B2 (en) * | 1997-12-31 | 2003-10-21 | Alliedsignal Inc. | Method of etching and cleaning using fluorinated carbonyl compounds |
US6127237A (en) * | 1998-03-04 | 2000-10-03 | Kabushiki Kaisha Toshiba | Etching end point detecting method based on junction current measurement and etching apparatus |
JP3178412B2 (ja) * | 1998-04-27 | 2001-06-18 | 日本電気株式会社 | トレンチ・アイソレーション構造の形成方法 |
JP4124543B2 (ja) | 1998-11-11 | 2008-07-23 | 東京エレクトロン株式会社 | 表面処理方法及びその装置 |
JP4057198B2 (ja) | 1999-08-13 | 2008-03-05 | 東京エレクトロン株式会社 | 処理装置及び処理方法 |
US6318384B1 (en) * | 1999-09-24 | 2001-11-20 | Applied Materials, Inc. | Self cleaning method of forming deep trenches in silicon substrates |
EP1099776A1 (fr) | 1999-11-09 | 2001-05-16 | Applied Materials, Inc. | Etape de nettoyage par plasma dans un procédé de salicidation |
US6271147B1 (en) * | 2000-08-18 | 2001-08-07 | Vanguard International Semiconductor Corporation | Methods of forming trench isolation regions using spin-on material |
US6372657B1 (en) * | 2000-08-31 | 2002-04-16 | Micron Technology, Inc. | Method for selective etching of oxides |
US6448537B1 (en) * | 2000-12-11 | 2002-09-10 | Eric Anton Nering | Single-wafer process chamber thermal convection processes |
US6670278B2 (en) * | 2001-03-30 | 2003-12-30 | Lam Research Corporation | Method of plasma etching of silicon carbide |
US6506291B2 (en) * | 2001-06-14 | 2003-01-14 | Applied Materials, Inc. | Substrate support with multilevel heat transfer mechanism |
US7138649B2 (en) * | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
JP3954833B2 (ja) | 2001-10-19 | 2007-08-08 | 株式会社アルバック | バッチ式真空処理装置 |
AU2002353145A1 (en) * | 2001-12-13 | 2003-06-30 | Applied Materials, Inc. | Self-aligned contact etch with high sensitivity to nitride shoulder |
US7256370B2 (en) * | 2002-03-15 | 2007-08-14 | Steed Technology, Inc. | Vacuum thermal annealer |
US6500728B1 (en) * | 2002-05-24 | 2002-12-31 | Taiwan Semiconductor Manufacturing Company | Shallow trench isolation (STI) module to improve contact etch process window |
KR100728173B1 (ko) * | 2003-03-07 | 2007-06-13 | 앰버웨이브 시스템즈 코포레이션 | 쉘로우 트렌치 분리법 |
US20040256353A1 (en) * | 2003-04-24 | 2004-12-23 | Tokyo Electron Limited | Method and system for deep trench silicon etch |
US20050079729A1 (en) * | 2003-10-08 | 2005-04-14 | Woo-Sung Jang | High density plasma oxide film deposition apparatus having a guide ring and a semiconductor device manufacturing method using the same |
US7780793B2 (en) * | 2004-02-26 | 2010-08-24 | Applied Materials, Inc. | Passivation layer formation by plasma clean process to reduce native oxide growth |
US20050230350A1 (en) * | 2004-02-26 | 2005-10-20 | Applied Materials, Inc. | In-situ dry clean chamber for front end of line fabrication |
US20070123051A1 (en) * | 2004-02-26 | 2007-05-31 | Reza Arghavani | Oxide etch with nh4-nf3 chemistry |
US7049200B2 (en) * | 2004-05-25 | 2006-05-23 | Applied Materials Inc. | Method for forming a low thermal budget spacer |
KR100593740B1 (ko) | 2004-09-16 | 2006-06-28 | 삼성전자주식회사 | 반도체 자연산화막 제거방법 |
US20060130971A1 (en) * | 2004-12-21 | 2006-06-22 | Applied Materials, Inc. | Apparatus for generating plasma by RF power |
JP4475136B2 (ja) | 2005-02-18 | 2010-06-09 | 東京エレクトロン株式会社 | 処理システム、前処理装置及び記憶媒体 |
US20070087573A1 (en) * | 2005-10-19 | 2007-04-19 | Yi-Yiing Chiang | Pre-treatment method for physical vapor deposition of metal layer and method of forming metal silicide layer |
JP2009094307A (ja) * | 2007-10-10 | 2009-04-30 | Tokyo Electron Ltd | エッチング方法及び記録媒体 |
US7994002B2 (en) * | 2008-11-24 | 2011-08-09 | Applied Materials, Inc. | Method and apparatus for trench and via profile modification |
-
2009
- 2009-11-18 US US12/620,799 patent/US7994002B2/en active Active
- 2009-11-19 JP JP2011537631A patent/JP5319782B2/ja not_active Expired - Fee Related
- 2009-11-19 KR KR1020117014410A patent/KR101148252B1/ko active IP Right Grant
- 2009-11-19 CN CN200980147109.5A patent/CN102224573B/zh not_active Expired - Fee Related
- 2009-11-19 CN CN201410050265.2A patent/CN103824746B/zh not_active Expired - Fee Related
- 2009-11-19 WO PCT/US2009/065208 patent/WO2010059868A2/fr active Application Filing
- 2009-11-19 TW TW098139358A patent/TWI413179B/zh not_active IP Right Cessation
-
2011
- 2011-08-08 US US13/205,379 patent/US8268684B2/en not_active Expired - Fee Related
-
2013
- 2013-07-10 JP JP2013144230A patent/JP5518239B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6335261B1 (en) * | 2000-05-31 | 2002-01-01 | International Business Machines Corporation | Directional CVD process with optimized etchback |
US20020137337A1 (en) * | 2001-03-23 | 2002-09-26 | Jiong-Ping Lu | Use of a sacrificial layer to facilitate metallization for small features |
US20060223323A1 (en) * | 2001-10-09 | 2006-10-05 | Liang-Yuh Chen | Method of forming an interconnect structure |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11264248B2 (en) | 2018-12-06 | 2022-03-01 | Tokyo Electron Limited | Etching method and substrate processing apparatus |
CN109706066A (zh) * | 2018-12-29 | 2019-05-03 | 赛纳生物科技(北京)有限公司 | 基因测序芯片微坑表面修饰方法 |
CN109706066B (zh) * | 2018-12-29 | 2022-08-26 | 赛纳生物科技(北京)有限公司 | 基因测序芯片微坑表面修饰方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5518239B2 (ja) | 2014-06-11 |
US20100129958A1 (en) | 2010-05-27 |
JP2012510164A (ja) | 2012-04-26 |
KR20110097884A (ko) | 2011-08-31 |
US8268684B2 (en) | 2012-09-18 |
CN103824746B (zh) | 2017-03-01 |
TW201027619A (en) | 2010-07-16 |
JP2013258408A (ja) | 2013-12-26 |
JP5319782B2 (ja) | 2013-10-16 |
CN102224573B (zh) | 2014-03-19 |
CN103824746A (zh) | 2014-05-28 |
TWI413179B (zh) | 2013-10-21 |
WO2010059868A3 (fr) | 2010-08-19 |
US7994002B2 (en) | 2011-08-09 |
US20110294258A1 (en) | 2011-12-01 |
CN102224573A (zh) | 2011-10-19 |
KR101148252B1 (ko) | 2012-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7994002B2 (en) | Method and apparatus for trench and via profile modification | |
KR100931765B1 (ko) | Nh3-nf3 화학물질을 이용하는 산화물 식각 | |
US10199215B2 (en) | Apparatus and method for selective deposition | |
US7780793B2 (en) | Passivation layer formation by plasma clean process to reduce native oxide growth | |
US20060130971A1 (en) | Apparatus for generating plasma by RF power | |
US8951913B2 (en) | Method for removing native oxide and associated residue from a substrate | |
US9093390B2 (en) | Conformal oxide dry etch | |
JP5250668B2 (ja) | 基板から未変性酸化物を除去する方法 | |
US20140363979A1 (en) | Directional sio2 etch using low-temperature etchant deposition and plasma post-treatment | |
US20090191703A1 (en) | Process with saturation at low etch amount for high contact bottom cleaning efficiency for chemical dry clean process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980147109.5 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09828246 Country of ref document: EP Kind code of ref document: A2 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011537631 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 20117014410 Country of ref document: KR Kind code of ref document: A |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09828246 Country of ref document: EP Kind code of ref document: A2 |