WO2015199640A1 - Procédé pour le dépôt d'une couche dans un trou d'interconnexion ou une tranchée, et produits obtenus par ce procédé - Google Patents

Procédé pour le dépôt d'une couche dans un trou d'interconnexion ou une tranchée, et produits obtenus par ce procédé Download PDF

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Publication number
WO2015199640A1
WO2015199640A1 PCT/US2014/043610 US2014043610W WO2015199640A1 WO 2015199640 A1 WO2015199640 A1 WO 2015199640A1 US 2014043610 W US2014043610 W US 2014043610W WO 2015199640 A1 WO2015199640 A1 WO 2015199640A1
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WO
WIPO (PCT)
Prior art keywords
layer
deposition
trench
substrate
depositing
Prior art date
Application number
PCT/US2014/043610
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English (en)
Inventor
Dharam GOSAIN
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to PCT/US2014/043610 priority Critical patent/WO2015199640A1/fr
Priority to JP2016575144A priority patent/JP6386106B2/ja
Priority to CN201480080149.3A priority patent/CN106460148B/zh
Priority to KR1020177032386A priority patent/KR20170127051A/ko
Priority to KR1020177002044A priority patent/KR20170018074A/ko
Priority to TW104119663A priority patent/TWI649804B/zh
Publication of WO2015199640A1 publication Critical patent/WO2015199640A1/fr

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering

Definitions

  • Embodiments relate to deposition of a layer filling a via or a trench, devices manufactured with material filled in a via or a trench and apparatus for depositing layer with material filled in a via or a trench. Particularly, embodiments relate to methods of depositing a material in a via or a trench provided in a first layer deposited over a substrate, methods of manufacturing a transistor on a substrate, layer stacks for an electronic device, and electronic devices.
  • a substrate e.g. on a glass substrate
  • the substrates are coated in different chambers of a coating apparatus.
  • the substrates are coated in a vacuum, using a vapor deposition technique.
  • vapor deposition technique Several methods are known for depositing a material on a substrate.
  • substrates may be coated by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or a plasma enhanced chemical vapor deposition (PECVD) process etc.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the process is performed in a process apparatus or process chamber where the substrate to be coated is located.
  • LTPS-TFT thin-film transistors
  • the increased number of TFTs results in a higher aspect ratio of the via, which is to be filled with the conductive material.
  • Filling the via with a sputtering process is beneficial in light of the manufacturing costs and the potential to scale-up the process. Also other applications, in which the via or a trench needs to be filled, i.e. other than manufacturing of a LTPS-TFT, can benefit from an improved process.
  • the deposition material can be present in the solid phase in a target.
  • atoms of the target material i.e. the material to be deposited
  • the atoms of the target material are deposited on the substrate to be coated.
  • the sputter material i.e. the material to be deposited on the substrate
  • the target may be made from the material to be deposited or may have a backing element on which the material to be deposited is fixed.
  • the target, including the material to be deposited is supported or fixed in a predefined position in a deposition chamber.
  • sputtering can be conducted as magnetron sputtering, wherein a magnet assembly is utilized to confine the plasma for improved sputtering conditions.
  • the plasma distribution, the plasma characteristics and other deposition parameters need to be controlled in order to obtain a desired layer deposition on the substrate. For example, a uniform layer with desired layer properties is desired. Accordingly, considering the increasing demands for the manufacturing of opto-electronic devices and other devices on a large scale, processes for manufacturing of devices such as displays need to be further improved.
  • a method of depositing a material in a via or a trench a method of manufacturing a transistor on a substrate, a layer stack, and an electronic device are provided.
  • a method of depositing a material in a via or a trench provided in a first layer deposited over a substrate is provided.
  • the method includes providing the first layer having the via or trench; depositing a first portion of a second layer on the first layer having the via or trench, wherein the deposition of the first portion of the second layer is conducted with a magnetron sputter cathode having a first magnet arrangement, wherein the first magnet arrangement is provided at a first angular coordinate resulting in a first deposition direction; and depositing a second portion of the second layer on the first layer having the via or trench, wherein the deposition of the second portion of the second layer is conducted with the magnetron sputter cathode, wherein the first magnet arrangement is provided at a second angular coordinate resulting in a second deposition direction, wherein the second angular coordinate is different from the first angular coordinate.
  • the first magnet arrangement can be rotatable around a first rotation axis.
  • a method of manufacturing a transistor on a substrate includes depositing a material in a via or a trench provided in a first layer deposited over a substrate.
  • the depositing a material in a via or trench includes providing the first layer having the via or trench; depositing a first portion of a second layer on the first layer having the via or trench, wherein the deposition of the first portion of the second layer is conducted with a magnetron sputter cathode having a first magnet arrangement, which is rotatable around a first rotation axis, wherein the first magnet arrangement is provided at a first angular coordinate resulting in a first deposition direction; and depositing a second portion of the second layer on the first layer having the via or trench, wherein the deposition of the second portion of the second layer is conducted with the magnetron sputter cathode, wherein the first magnet arrangement is provided at a second angular coordinate resulting in a second deposition direction, wherein the second
  • a layer stack for an electronic device includes a first layer and a second layer of a material deposited over a substrate.
  • the first layer and the second layer are deposited with a method of depositing a material in a via or a trench provided in a first layer deposited over a substrate.
  • the method includes providing the first layer having the via or trench; depositing a first portion of a second layer on the first layer having the via or trench, wherein the deposition of the first portion of the second layer is conducted with a magnetron sputter cathode having a first magnet arrangement, which is rotatable around a first rotation axis, wherein the first magnet arrangement is provided at a first angular coordinate resulting in a first deposition direction; and depositing a second portion of the second layer on the first layer having the via or trench, wherein the deposition of the second portion of the second layer is conducted with the magnetron sputter cathode, wherein the first magnet arrangement is provided at a second angular coordinate resulting in a second deposition direction, wherein the second angular coordinate is different from the first angular coordinate.
  • an electronic device includes a layer stack.
  • the layer stack includes a first layer and a second layer of a material deposited over a substrate.
  • the first layer and the second layer are deposited with a method of depositing a material in a via or a trench provided in a first layer deposited over a substrate.
  • the method includes providing the first layer having the via or trench; depositing a first portion of a second layer on the first layer having the via or trench, wherein the deposition of the first portion of the second layer is conducted with a magnetron sputter cathode having a first magnet arrangement, which is rotatable around a first rotation axis, wherein the first magnet arrangement is provided at a first angular coordinate resulting in a first deposition direction; and depositing a second portion of the second layer on the first layer having the via or trench, wherein the deposition of the second portion of the second layer is conducted with the magnetron sputter cathode, wherein the first magnet arrangement is provided at a second angular coordinate resulting in a second deposition direction, wherein the second angular coordinate is different from the first angular coordinate.
  • FIGS. 1 A to II show schematic views of a portion of the substrate, wherein layer stack according to embodiments is deposited on the substrate;
  • FIG. 2 shows a flowchart illustrating a method of depositing a layer of material over substrate according to embodiments described herein and corresponding to FIGS. 1A to IE;
  • FIG. 3 A shows a schematic view of an apparatus for depositing a layer of the material in a first processing condition according to embodiments described herein;
  • FIG. 3B shows a schematic view of an apparatus for depositing a layer of the material in a second processing condition according to embodiments described herein;
  • FIGS. 4A and 4B illustrate the first and the second processing condition according to embodiments described herein;
  • FIGS. 5 A and 5B show a schematic result of the layer deposited, wherein FIG. 5 A shows the first portion of the layer and FIG. 5B shows the first and the second portion of the layer according to embodiments described herein; and
  • FIG. 6 shows a flowchart illustrating a method of depositing a layer of material over substrate according to embodiments described herein.
  • a layer stack is provided to fill a via or trench, wherein a step coverage is improved by providing different angular coordinates of a magnet assembly, e.g. in a line source.
  • the line source can be provided by a rotary cathode or a rotatable cathode.
  • FIG. 1A shows a layer stack 150 after a first deposition process 202 (see FIG. 2).
  • An active channel layer 152 is deposited over the substrate 151.
  • the active channel layer 152 includes the active channel 152a, a source region 152s, and a drain region 152d.
  • the active channel layer 152 can be a polysilicon layer.
  • the polysilicon layer can be manufactured by deposition of silicon, for example from a sputtering cathode, and crystallization of the deposited silicon layer.
  • the crystallization process can be conducted by laser processing, by a catalytic process, or by another process.
  • excimer laser annealing can be used.
  • MILC enhanced metal-induced lateral crystallization
  • PRTA pulsed rapid thermal annealing
  • CGS continuous grain silicon
  • CW continuous wave
  • SLS sequential lateral solidification
  • the techniques for manufacturing TFT on the glass substrate include the amorphous silicon (a-Si) process and the low temp polysilicon (LTPS) process.
  • the major differences between the a-Si process and the LTPS process are the electrical characteristics of the devices and the complexity of the processes.
  • the LTPS TFT possesses higher mobility but the process for fabricating the LTPS TFT is more complicated. Although the a-Si TFT possesses lower mobility, the process for fabricating the a-Si TFT is simple. According to embodiments described herein, the LTPS TFT process can be improved.
  • the LTPS TFT process is one example for which embodiments described herein can be beneficially utilized. [0026] In FIG.
  • a gate insulator layer 153 is provided over the active channel layer 152 (see box 204 in FIG. 2).
  • some of the layers described herein, such as the active channel layer 152, the layer of the material forming the gate, and other layers are structured during the LTPS TFT process.
  • the structuring for example due to etching, can be conducted according to any of the methods known to a person skilled in the art and are not described within the present disclosure. It will be apparent for a person skilled in the art whether or not a structuring process is utilized between subsequent deposition processes described herein.
  • FIG. 1C shows a first portion 162 of the layer.
  • the first portion 162 is deposited (see box 206 in FIG. 2) with a first deposition direction of the material to be deposited on the substrate and with columnar growth.
  • the first deposition direction results in a first columnar growth direction.
  • FIG. ID shows a second portion 164 of the layer.
  • the second portion 164 is deposited (see box 208 in FIG. 2) with a second deposition direction of the material to be deposited on the substrate and with columnar growth.
  • the second deposition direction results in a second columnar growth direction.
  • a deposition direction can be referred to as a main deposition direction or an average deposition direction.
  • the deposition distribution typically has a main or average direction of the materials, even though the deposition distribution may have some directional spread.
  • a layer of material is deposited over the substrate, i.e. a layer with physical characteristics of a single layer, wherein the layer of material includes a first columnar growth direction and a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
  • the process parameters for the columnar growth can be as follows.
  • the exemplary process parameters refer to deposition of molybdenum and the position of other materials may have other process parameters for columnar growth of such other materials.
  • Columnar growth as referred to herein is understood as a morphology with columnar grains, wherein the grains have a significantly larger length in one direction, i.e. along the columns, which is referred to as the columnar growth direction.
  • a columnar growth can be provided for a film thickness of 20 nm to 500 nm, or above, particularly 100 nm to 400 nm.
  • further process parameters can be selected from the group of: a deposition pressure of 0.1 to 1 Pa, particularly 0.2 to 0.5 Pa, a deposition power, which may depend on the system geometry of 3 kW to 60 kW per cathode, mores specifically, 20 kW to 40 kW per cathode.
  • an ion implantation process is conducted.
  • the ion implantation is also illustrated by arrows 90 in FIG. IE.
  • the ion implantation process provides doping for the source region 152s and the drain region 152d.
  • the gate electrode of the transistor is used as a mask during the ion implantation process. Accordingly, a self- aligned doping process is conducted.
  • the likelihood of ions to channel through the mask, i.e. the gate electrode is significantly reduced. The reduction of the channeling of ions through the gate electrode reduces undesired doping of the active channel region.
  • a gate electrode layer (or another layer for other applications utilizing ion implantation, the thickness of the layer can be 200 nm or above, particularly 300 nm or above.
  • the thickness of the first portion of a layer for masking and/or the thickness of the second portion of layer for masking can be 40 nm or above, particularly 100 nm or above.
  • the gate electrode layer can be a metallic layer, particularly wherein the layer can be a MoW layer, a Mo layer, a Ti layer, a Al layer, a Cu layer, a layer comprising two or more of MoW, Mo, Ti, Al, Cu, or a layer comprising an alloy of one or more of MoW, Mo, Ti, Al, Cu.
  • Figure IF shows the layer stack 150, wherein the dielectric layer 172 is provided (see box 212 in FIG. 2).
  • the dielectric layer can be an inter-layer dielectric.
  • the dielectric layer 172 can be a silicon oxide layer, a silicon nitride layer, a silicon oxinitride layer, or other suitable dielectric layers.
  • a via 173 is etched in the dielectric layer 172.
  • the via 173 is filled with a conductive material 174, as shown in figure 1G (see also box 214 in FIG. 2). .
  • the layer stacks and/or the corresponding devices have a high density transistor integration.
  • the devices can have a pixel density of 300 pixels per inch (PPI) or above.
  • PPI pixels per inch
  • the contact hole size is reduced and the taper angle of the contact hole, i.e. a via, is increased.
  • the step coverage is improved to 60% or above by providing a first portion of the layer filling the via with a first deposition direction, wherein the depositing of the first portion of the layer filling the via is conducted with a magnetron sputter cathode having a first magnet arrangement, which is rotatable around a first rotation axis, wherein the first magnet arrangement is provided at a first angular coordinate resulting in a first deposition direction.
  • the step coverage can be improved by providing two or more angular coordinates of a magnetron.
  • the magnetron can be provided in at rotatable sputter cathode, which forms a line source extending along the rotation axis of the cathode. It is an unexpected result that the step coverage can be improved with a plurality of line sources and by depositing material with different angular coordinates of the magnetron.
  • the via can be filled with material selected from the group consisting of Mo, W, Mo, Ti, Al, Cu, combinations thereof, and alloys including Mo, W, Mo, Ti, Al, Cu.
  • conductive material 174 can be deposited from a material of the above mentioned group having a high conductivity, for example aluminum, and the material like molybdenum or titanium can be used as an adhesive layer.
  • Box 216 in figure 2 illustrates the position of a passivation layer 176, for example an organic passivation layer such as a lacquer, and the common- voltage electrode 178. This is also illustrated in figure 1H.
  • the passivation layer is provided with a via, which can be filled (see box 218 in FIG. 2) to provide the pixel electrode 182, after a further dielectric layer 180 provided between the common- voltage electrode 178 and the pixel electrode 182.
  • the pixel electrode which also fills the wire in the passivation layer 176, can be sputtered.
  • the pixel electrode can be deposited from a transparent conductive oxide (TCO) to form a TCO layer.
  • TCO transparent conductive oxide
  • the TCO layer can include at least one of an indium tin oxide (ITO) layer, a doped ITO layer, impurity-doped ZnO, In203, Sn02 and CdO, ITO (In203:Sn), AZO (ZnO:Al), IZO (ZnO: In), GZO (ZnO:Ga), or multi-component oxides including or consisting of combinations of ZnO, In203 and Sn02, or combinations thereof.
  • ITO indium tin oxide
  • a doped ITO layer impurity-doped ZnO, In203, Sn02 and CdO
  • ITO In203:Sn
  • AZO ZnO:Al
  • IZO ZnO: In
  • GZO ZnO:Ga
  • multi-component oxides including or consisting of combinations of ZnO, In203 and Sn02, or combinations thereof.
  • FIG. 1A to II refers to the filling of a via. Yet, according to other embodiments, filling with an improved step coverage according to embodiments described herein can also be provided for filling of the trench.
  • FIG. 3A shows a schematic cross-sectional view of a deposition apparatus 100 according to embodiments as described herein.
  • a deposition apparatus 100 e.g. one vacuum chamber 102 for deposition of layers therein is shown.
  • further chambers 102 can be provided adjacent to the chamber 102.
  • the vacuum chamber 102 can be separated from adjacent chambers by a valve having a valve housing 104 and a valve unit 105.
  • the valve unit 105 can be closed. Accordingly, the atmosphere in the vacuum chambers 102 and 103 can be individually controlled by generating a technical vacuum, for example, with vacuum pumps connected to the chamber 102 and 103, and/or by inserting processing gases in the deposition region in the chamber 102. As described above, for many large area processing applications, the large area substrates are supported by a carrier. However, embodiments described herein are not limited thereto and other transportation elements for transporting a substrate through a processing apparatus or processing system may be used.
  • a transport system is provided in order to transport the carrier 114, having the substrate 14 thereon, into and out of the chamber 102.
  • substrate as used herein shall embrace substrates such as a glass substrate, a wafer, slices of transparent crystal such as sapphire or the like, or a glass plate.
  • deposition sources e.g. cathodes 122
  • the deposition sources can, for example, be rotatable cathodes having targets of the material to be deposited on the substrate.
  • the cathodes can be rotatable cathodes with a magnet assembly 121 therein. Magnetron sputtering can be conducted for deposition of the layers.
  • each pair of neighboring cathodes can be connected to a power supply 123a-c.
  • each pair of neighboring cathodes can be connected to an AC power supply or each cathode can be connected to a DC power supply.
  • a DC power supply is shown in FIG. 3 A, wherein anodes 116 are further connected to the power supply.
  • the cathodes 122 are connected to an AC power supply such that the cathodes can be biased in an alternating manner.
  • AC power supplies such as MF power supplies can, for example, be provided for depositing layers of A1203.
  • the cathodes can be operated without additional anodes, which can e.g. be removed, as a complete circuit including cathode and anode is provided by a pair of cathodes 122.
  • a first outer deposition assembly 301 may be connected to a first group of gas tanks 141 for providing a first composition of reactive gases
  • the second outer deposition assembly 302 may be connected to a second group of gas tanks 142 for providing a second composition of reactive gases
  • the inner deposition assembly 303 may be connected to a third group 143 of gas tanks for providing a third composition of reactive gases to the inner deposition assembly.
  • all deposition assemblies may also be connected to the same group of gas tanks for providing the processing gas.
  • the controller 500 is configured for controlling one or more of the power supplies commonly or individually.
  • the controller 500 is configured for controlling a first power supply for supplying a first power to the first outer deposition assembly and the second outer deposition assembly.
  • the controller can also be configured for controlling a second power supply 123b for supplying a second power to the inner deposition assembly.
  • the first power supply for supplying a first power to the first outer deposition assembly and the second outer deposition assembly can include two separate power supplies 123 a, 123 c for supplying the first power to the first outer deposition assembly and the second outer deposition assembly.
  • deposition sources e.g. cathodes 122
  • the deposition sources can, for example, be rotatable cathodes having targets of the material to be deposited on the substrate.
  • the cathodes can be rotatable cathodes with a magnet assembly 121 therein.
  • magnetron sputtering can be conducted for the deposition of material on a substrate.
  • the deposition process can be conducted with rotary cathodes and a rotatable magnet assembly, i.e. a rotatable magnet yoke therein.
  • magnet sputtering refers to sputtering performed using a magnetron, i.e. a magnet assembly, that is, a unit capable of generating a magnetic field.
  • a magnet assembly consists of one or more permanent magnets.
  • permanent magnets are typically arranged within a rotatable target or coupled to a planar target in a manner such that the free electrons are trapped within the generated magnetic field generated below the rotatable target surface.
  • Such a magnet assembly may also be arranged coupled to a planar cathode.
  • magnetron sputtering can be realized by a double magnetron cathode, i.e.
  • cathodes 122 such as, but not limited to, a TwinMagTM cathode assembly.
  • target assemblies including double cathodes can be applied.
  • the cathodes in a deposition chamber may be interchangeable. Accordingly, the targets are changed after the material to be sputtered has been consumed.
  • sputtering can be conducted as DC sputtering, MF (middle frequency) sputtering, as RF sputtering, or as pulse sputtering. As described herein, some deposition processes might beneficially apply MF, DC or pulsed sputtering. However, other sputtering methods can also be applied.
  • FIGS. 3A and 3B a plurality of cathodes 122 with a magnet assembly 121 or magnetron provided in the cathodes are shown.
  • the sputtering according to the described embodiments can be conducted with three or more cathodes.
  • an array of cathodes or cathode pairs can be provided.
  • three or more cathodes or cathode pairs e.g. three, four, five, six or even more cathodes or cathode pairs can be provided.
  • the array can be provided in one vacuum chamber. Further, an array can typically be defined such that adjacent cathodes or cathode pairs influence each other, e.g. by having interacting plasma confinement.
  • the magnet assemblies are rotated such that a deposition direction is provided, which is indicated by arrows 300 A.
  • a first deposition direction is provided, which results in a first deposition direction.
  • the magnet assemblies are rotated such that a deposition direction is provided, which is indicated by arrows 300B.
  • a second deposition direction is provided, which results in an improved step coverage.
  • Embodiments described herein which relate to manufacturing of the transistor on a substrate, particularly a LPS-TFT, wherein the gate electrode is used as a mask for self- aligned doping can for example utilize a DC sputtering process for depositing molybdenum (Mo), molybdenum-tungsten (MoW), titanium (Ti), aluminum (Al), copper (Cu) and alloys containing one or more of the above elements.
  • Mo molybdenum
  • MoW molybdenum-tungsten
  • Ti titanium
  • Al aluminum
  • Cu copper
  • sputtering can be conducted as DC (direct current) sputtering, MF (middle frequency) sputtering, RF sputtering, or as pulse sputtering.
  • DC direct current
  • MF middle frequency
  • RF RF
  • pulse sputtering some deposition processes might beneficially apply MF, DC or pulsed sputtering.
  • middle frequency is a frequency in the range of 0.5 kHz to 350 kHz, for example, 10 kHz to 50 kHz.
  • the sputtering according to the described embodiments can be conducted with three or more cathodes.
  • an array of cathodes having 6 or more cathodes, e.g. 10 or more cathodes can be provided.
  • the array can be provided in one vacuum chamber.
  • an array can typically be defined such that adjacent cathodes or cathode pairs influence each other, e.g. by having interacting plasma confinement.
  • the sputtering can be conducted by a rotary cathode array, such as, but not limited to, a system such as PiVot of Applied Materials Inc..
  • the embodiments described herein can be utilized for Display PVD, i.e. sputter deposition on large area substrates for the display market.
  • a flat panel display or mobile phone displays can be manufactured on large area substrates.
  • large area substrates or respective carriers, wherein the carriers have a plurality of substrates may have a size of at least 0.67 m 2 .
  • the size can be about 0.67m 2 (0.73x0.92m - Gen 4.5) to about 8 m 2 , more typically about 2 m 2 to about 9 m 2 or even up to 12 m 2 .
  • a large area substrate or a respective carrier can have a size of 1.4 m 2 or above.
  • the substrates or carriers, for which the structures, apparatuses, such as cathode assemblies, and methods according to embodiments described herein are provided are large area substrates as described herein.
  • a large area substrate or carrier can be GEN 4.5, which corresponds to about 0.67 m 2 substrates (0.73x0.92m), GEN 5, which corresponds to about 1.4 m 2 substrates (1.1 m x 1.3 m), GEN 7.5, which corresponds to about 4.29 m 2 substrates (1.95 m x 2.2 m), GEN 8.5, which corresponds to about 5.7m 2 substrates (2.2 m x 2.5 m), or even GEN 10, which corresponds to about 8.7 m 2 substrates (2.85 m x 3.05 m). Even larger generations such as GEN 11 and GEN 12 and corresponding substrate areas can similarly be implemented.
  • the target material can be selected from the group consisting of: aluminum, silicon, tantalum, molybdenum, niobium, titanium, indium, gallium, zinc, tin, silver and copper. Particularly, the target material can be selected from the group consisting of indium, gallium and zinc.
  • the reactive sputter processes provide typically deposited oxides of these target materials. However, nitrides or oxi-nitrides might be deposited as well.
  • the methods provide a sputter deposition for a positioning of the substrate for a static deposition process.
  • large area substrate processing such as processing of vertically oriented large area substrates
  • it can be distinguished between static deposition and dynamic deposition.
  • the substrates and/or the carriers described herein and the apparatuses for utilizing the gas distribution systems described herein can be configured for vertical substrate processing.
  • the term vertical substrate processing is understood to distinguish over horizontal substrate processing. That is, vertical substrate processing relates to an essentially vertical orientation of the carrier and the substrate during substrate processing, wherein a deviation of a few degrees, e.g.
  • a vertical substrate orientation with a small inclination can, for example, result in a more stable substrate handling or a reduced risk of particles contaminating a deposited layer.
  • a horizontal substrate orientation may be possible.
  • the cathode array would, for example, also be essentially horizontal.
  • a vertical substrate orientation e.g. within -15° to +15° from the vertical orientation, reduces the floor space for large area substrate processing and, thus, the cost of ownership (CoO).
  • a static deposition process can be understood as a deposition process with a static position, a deposition process with an essentially static position, or a deposition process with a partially static position of the substrate.
  • a static deposition process, as described herein, can be clearly distinguished from a dynamic deposition process without the necessity that the substrate position for the static deposition process is fully without any movement during deposition.
  • a deviation from an fully static substrate position e.g.
  • oscillating, wobbling or any other movement of substrates as described above can additionally or alternatively be provided by a movement of the cathodes or the cathode array, e.g. wobbling, oscillating or the like.
  • the substrate and the cathodes (or the cathode array) can move relative to each other, e.g. in the substrate transport direction, in a lateral direction essentially perpendicular to the substrate transport direction or both.
  • the manufacture of a layer having a first portion with a first deposition direction and a second portion with a second, different deposition direction can also be conducted in a dynamic deposition system, wherein the substrate is moved by two or more sources.
  • the transportation speed of the substrate may be taken into consideration when determining the deposition directions for the manufacturing processes.
  • the step coverage for the layer deposited in a via or trench can be improved by switching between the first deposition direction and a second, different deposition direction, wherein the magnetron is rotated to have different angular coordinates providing that different deposition directions.
  • the switching between the angular coordinates of the magnet assembly can be conducted back and forth without switching off the sputtering process, e.g. a so-called "wobbling" of the magnet assembly.
  • FIG. 4A shows the cathode 122 having a magnet assembly 121 provided in the cathode, for example within a backing tube supporting the target material.
  • the magnet assembly 121 can be rotated to deviate from the vertical deposition direction, i.e. to have a first angular coordinate.
  • the vertical direction i.e. the direction perpendicular to the surface of the substrate 451, is shown by line 471.
  • the angle 470 can be 10° or above, for example 20° to 60°, such as about 25° to 40°, for example about 30°.
  • FIG. 4A illustrates confined plasma tubes 407 and the deposition direction (see arrow 300 A) resulting from the angular position of the magnet assembly 121 relative to line 471 or the substrate 451, respectively.
  • a first portion 474a of the layer is grown on the substrate 451 , wherein one side of the via or trench is preferentially coated with the material.
  • the substrate 451 shown in FIGS. 4A to 5B can be a substrate as described above but may also be a substrate having one or more layers provided thereon.
  • FIGS. 5 A and 5B schematically show layer 472 having the via (or trench) provided therein and an underlying layer 452, both of which are provided on the substrate 451.
  • the magnet assembly 121 After deposition of the first portion 474a of the layer, the magnet assembly 121 is rotated to the second position shown exemplarily in FIG. 4B, i.e. to a second angular coordinate. A second deposition direction indicated by arrow 300B is provided by the second position of the magnet assembly 121. As a result, as shown in FIG. 5B, a second portion 474 of the layer is grown on the first portion 474a of the layer. The second portion is deposited, wherein another side of the via or trench is preferentially coated with the material. According to embodiments described herein, a layer thickness d and the layout width w within the via or the trench can be provided. The step coverage is provided by the ratio of the thinnest width w divided by the layer thickness d. According to typical embodiments, methods of depositing a layer in a via or trench as described herein can provide a step coverage of 60% or above.
  • switching between the first position of the magnet assembly and the second position of the magnet assembly or vice versa is provided one or more times.
  • the switching between the first position of the magnet assembly and the second position of the magnet assembly can be a continuous movement or a quasi- continuous movement, e.g. back and forth.
  • the magnetron sputter cathode can be a rotatable magnetron sputter cathode having a rotating target, wherein the rotatable magnetron sputter target forms a line source.
  • an array of cathodes such that a magnetron sputter cathode is one deposition source of at least three deposition sources in an array of deposition sources can be provided.
  • the trench or via can have a width of 3 nm or below at the bottom of the via or trench. Yet further additionally or alternatively, the trench or via can have a taper angle of 70° or above. By providing one or both of the aspects, a pixel density of 300 ppi or above can be realized.
  • the thickness of a pixel electrode can be for example 30 nm to 100 nm, e.g. about 50 nm, for ITO or other TCOs, and the thickness of a pixel electrode can be for example 150 nm to 500 nm, e.g. 250 nm to 350 nm, for metals.
  • the layer can be a metallic layer, particularly the layer can be a MoW layer, a Mo layer, a Ti layer, a Al layer, a Cu layer, a layer comprising two or more of MoW, Mo, Ti, Al, Cu, or a layer comprising an alloy of one or more of MoW, Mo, Ti, Al, Cu.
  • the layer can be a metallic layer, particularly the layer can be a MoW layer, a Mo layer, a Ti layer, a Al layer, a Cu layer, a layer comprising two or more of MoW, Mo, Ti, Al, Cu, or a layer comprising an alloy of one or more of MoW, Mo, Ti, Al, Cu.
  • the layer can include one or more elements selected from a group consisting of: indium tin oxide (ITO) layer, a doped ITO layer, impurity-doped ZnO, In203, Sn02 and CdO, ITO (In203:Sn), AZO (ZnO:Al), IZO (ZnO: In), GZO (ZnO:Ga), or multi-component oxides including or consisting of combinations of ZnO, In203 and Sn02, or combinations thereof.
  • ITO indium tin oxide
  • a doped ITO layer impurity-doped ZnO, In203, Sn02 and CdO
  • ITO In203:Sn
  • AZO ZnO:Al
  • IZO ZnO: In
  • GZO ZnO:Ga
  • multi-component oxides including or consisting of combinations of ZnO, In203 and Sn02, or combinations thereof.
  • FIG. 7 shows a method of depositing a second layer of a material over a first layer having a via or trench, wherein the first portion of the layer is deposited (see box 601 in FIG.
  • a method of depositing a layer of a material over a substrate includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
  • first deposition direction can for example be essentially constant during the depositing the first portion of the layer and/or the second deposition direction can for example be essentially constant during the depositing the second portion of the layer.
  • the first deposition directions for angular growth may be provided, wherein the first deposition direction is defined by a first angular coordinate of a magnet arrangement of a magnetron sputter cathode and/or wherein the second deposition direction is defined by a second angular coordinate of the magnet arrangement of the magnetron sputter cathode.

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  • Organic Chemistry (AREA)
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  • Mechanical Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé pour le dépôt d'un matériau dans un trou d'interconnexion ou une tranchée ménagé dans une première couche disposée par-dessus un substrat. Le procédé comprend la fourniture de la première couche ayant le trou d'interconnexion ou la tranchée ; le dépôt d'une première portion d'une deuxième couche sur la première couche ayant le trou d'interconnexion ou la tranchée, le dépôt de la première portion de la deuxième couche étant réalisé avec une cathode de pulvérisation cathodique à magnétron ayant un premier agencement d'aimants, qui peut tourner autour d'un premier axe de rotation, le premier agencement d'aimants étant disposé sur une première coordonnée angulaire, conduisant à une première direction de dépôt ; et le dépôt d'une deuxième portion de la deuxième couche sur la première couche ayant le trou d'interconnexion ou la tranchée, le dépôt de la deuxième portion de la deuxième couche étant réalisé avec la cathode de pulvérisation cathodique à magnétron, le premier agencement d'aimants étant disposé sur une deuxième coordonnée angulaire, conduisant à une deuxième direction de dépôt, la deuxième coordonnée angulaire étant différente de la première coordonnée angulaire.
PCT/US2014/043610 2014-06-23 2014-06-23 Procédé pour le dépôt d'une couche dans un trou d'interconnexion ou une tranchée, et produits obtenus par ce procédé WO2015199640A1 (fr)

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PCT/US2014/043610 WO2015199640A1 (fr) 2014-06-23 2014-06-23 Procédé pour le dépôt d'une couche dans un trou d'interconnexion ou une tranchée, et produits obtenus par ce procédé
JP2016575144A JP6386106B2 (ja) 2014-06-23 2014-06-23 ビア又はトレンチの中に層を堆積する方法、及び当該方法によって得られる製品
CN201480080149.3A CN106460148B (zh) 2014-06-23 2014-06-23 在通孔或沟槽中沉积层的方法以及由此获得的产品
KR1020177032386A KR20170127051A (ko) 2014-06-23 2014-06-23 비아 또는 트렌치에 층을 증착하는 방법 및 그에 의해 획득된 제품들
KR1020177002044A KR20170018074A (ko) 2014-06-23 2014-06-23 비아 또는 트렌치에 층을 증착하는 방법 및 그에 의해 획득된 제품들
TW104119663A TWI649804B (zh) 2014-06-23 2015-06-18 在通孔或溝槽中沈積層的方法、製造電晶體的方法、用於電子裝置的層堆疊、及電子裝置

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WO2022223096A1 (fr) * 2021-04-19 2022-10-27 Applied Materials, Inc. Source de dépôt par pulvérisation, cathode de pulvérisation magnétron et procédé de dépôt d'un matériau sur un substrat

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EP2306489A1 (fr) * 2009-10-02 2011-04-06 Applied Materials, Inc. Procédé de revêtement d'un substrat et dispositif de revêtement
JP2011091242A (ja) * 2009-10-23 2011-05-06 Elpida Memory Inc 半導体装置の製造方法

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US6143140A (en) * 1999-08-16 2000-11-07 Applied Materials, Inc. Method and apparatus to improve the side wall and bottom coverage in IMP process by using magnetic field
US20050205411A1 (en) * 2004-03-19 2005-09-22 Tai-Yuan Chen [physical vapor deposition process and apparatus therefor]
US20080289957A1 (en) * 2004-09-14 2008-11-27 Shinmaywa Industries, Ltd. Vacuum Film Forming Apparatus

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WO2022223096A1 (fr) * 2021-04-19 2022-10-27 Applied Materials, Inc. Source de dépôt par pulvérisation, cathode de pulvérisation magnétron et procédé de dépôt d'un matériau sur un substrat

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CN106460148B (zh) 2018-12-04
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JP2017520683A (ja) 2017-07-27
TW201614726A (en) 2016-04-16
KR20170018074A (ko) 2017-02-15
TWI649804B (zh) 2019-02-01
KR20170127051A (ko) 2017-11-20

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