TW201614726A - Method of depositing a layer in a via or trench, method of manufacturing a transistor, layer stack for an electronic device, and an electronic device - Google Patents

Method of depositing a layer in a via or trench, method of manufacturing a transistor, layer stack for an electronic device, and an electronic device

Info

Publication number
TW201614726A
TW201614726A TW104119663A TW104119663A TW201614726A TW 201614726 A TW201614726 A TW 201614726A TW 104119663 A TW104119663 A TW 104119663A TW 104119663 A TW104119663 A TW 104119663A TW 201614726 A TW201614726 A TW 201614726A
Authority
TW
Taiwan
Prior art keywords
layer
trench
electronic device
depositing
transistor
Prior art date
Application number
TW104119663A
Other languages
Chinese (zh)
Other versions
TWI649804B (en
Inventor
Dharam Gosain
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW201614726A publication Critical patent/TW201614726A/en
Application granted granted Critical
Publication of TWI649804B publication Critical patent/TWI649804B/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

A method of depositing a material in a via or a trench provided in a first layer deposited over a substrate is described. The method includes providing the first layer having the via or trench; depositing a first portion of a second layer on the first layer having the via or trench, wherein the deposition of the first portion of the second layer is conducted with a magnetron sputter cathode having a first magnet arrangement, which is rotatable around a first rotation axis, wherein the first magnet arrangement is provided at a first angular coordinate resulting in a first deposition direction; and depositing a second portion of the second layer on the first layer having the via or trench, wherein the deposition of the second portion of the second layer is conducted with the magnetron sputter cathode, wherein the first magnet arrangement is provided at a second angular coordinate resulting in a second deposition direction, wherein the second angular coordinate is different from the first angular coordinate.
TW104119663A 2014-06-23 2015-06-18 Method of depositing a layer in a via or trench, method of manufacturing a transistor, layer stack for an electronic device, and an electronic device TWI649804B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
??PCT/US2014/043610 2014-06-23
PCT/US2014/043610 WO2015199640A1 (en) 2014-06-23 2014-06-23 Method of depositing a layer in a via or trench and products obtained thereby

Publications (2)

Publication Number Publication Date
TW201614726A true TW201614726A (en) 2016-04-16
TWI649804B TWI649804B (en) 2019-02-01

Family

ID=51211334

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104119663A TWI649804B (en) 2014-06-23 2015-06-18 Method of depositing a layer in a via or trench, method of manufacturing a transistor, layer stack for an electronic device, and an electronic device

Country Status (5)

Country Link
JP (1) JP6386106B2 (en)
KR (2) KR20170018074A (en)
CN (1) CN106460148B (en)
TW (1) TWI649804B (en)
WO (1) WO2015199640A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230172566A (en) * 2021-04-19 2023-12-22 어플라이드 머티어리얼스, 인코포레이티드 Sputter deposition source, magnetron sputter cathode, and method for depositing material on a substrate

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0211758A (en) * 1988-06-28 1990-01-16 Nec Corp Sputtering device
US6143140A (en) * 1999-08-16 2000-11-07 Applied Materials, Inc. Method and apparatus to improve the side wall and bottom coverage in IMP process by using magnetic field
US6242348B1 (en) * 1999-10-04 2001-06-05 National Semiconductor Corp. Method for the formation of a boron-doped silicon gate layer underlying a cobalt silicide layer
TWI242052B (en) * 2004-03-19 2005-10-21 Promos Technologies Inc Physical vapor deposition process and apparatus thereof
JP2006083408A (en) * 2004-09-14 2006-03-30 Shin Meiwa Ind Co Ltd Vacuum film-forming apparatus
US7994002B2 (en) * 2008-11-24 2011-08-09 Applied Materials, Inc. Method and apparatus for trench and via profile modification
EP2306489A1 (en) * 2009-10-02 2011-04-06 Applied Materials, Inc. Method for coating a substrate and coater
JP2011091242A (en) * 2009-10-23 2011-05-06 Elpida Memory Inc Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
KR20170127051A (en) 2017-11-20
TWI649804B (en) 2019-02-01
CN106460148A (en) 2017-02-22
KR20170018074A (en) 2017-02-15
JP6386106B2 (en) 2018-09-05
CN106460148B (en) 2018-12-04
JP2017520683A (en) 2017-07-27
WO2015199640A1 (en) 2015-12-30

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees