WO2010059336A1 - Condensateur intégré à plaques de réseau - Google Patents
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- WO2010059336A1 WO2010059336A1 PCT/US2009/061958 US2009061958W WO2010059336A1 WO 2010059336 A1 WO2010059336 A1 WO 2010059336A1 US 2009061958 W US2009061958 W US 2009061958W WO 2010059336 A1 WO2010059336 A1 WO 2010059336A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- ICs integrated capacitors
- Methods of fabricating ICs typically include a front-end sequence of processing, in which various electrical devices such as transistors are formed in a semiconductor substrate, and a back-end sequence of processing, generally including forming alternating layers of dielectric material and patterned conductive material (typically metal) with conductive vias or other techniques being used to interconnect the metal layers to form a three-dimensional wiring structure that connects electrical devices to other electrical devices and to terminals of the IC.
- a front-end sequence of processing in which various electrical devices such as transistors are formed in a semiconductor substrate
- a back-end sequence of processing generally including forming alternating layers of dielectric material and patterned conductive material (typically metal) with conductive vias or other techniques being used to interconnect the metal layers to form a three-dimensional wiring structure that connects electrical devices to other electrical devices and to terminals of the IC.
- Capacitors are used in IC systems for a variety of purposes. In many instances, it is desirable to incorporate (integrate) a capacitor in the IC chip. A simple approach is to form two conductive plates with an intervening dielectric; however, this consumes a relatively large area for the capacitance obtained.
- One technique for increasing the capacitance of a given area is to use multiple conductive plates, each conductive plate separated from the proximate plate(s) by dielectric. Further techniques use conducting strips, also called conductive lines, conductive fingers, or conductive traces that are alternately connected to the first and second capacitor terminals (nodes). Sidewall coupling between the conductive strips provides capacitance. Layers of conducting strips, either offset or arranged in vertical congruency, can be added to further increase the capacitance of an integrated capacitor structure.
- One capacitor has a number of conductive strips in successive layers connected to the first node alternating with an equal number of conductive strips connected to the second node of the integrated capacitor.
- the conductive strips are offset a half cell on successive layers, so that a conductive strip connected to the first node has conductive strips connected to the second node above and on both sides of it.
- Providing an equal number of conductive strips in a layer for each node balances the coupling of each node to the substrate, which is desirable in some applications, but undesirable in others, such as switching applications where it is desirable to have less coupling at one node.
- a thick layer of silicon dioxide is used between the substrate and the first layer of conductive strips. This may be difficult to integrate in a standard CMOS fabrication sequence, and might require additional steps to be added to the standard process flow.
- the overlapping parallel conductive strips are connected at their ends using buss strips that consume additional surface area.
- Another approach to providing an integrated capacitor is to have conductive strips in a layer connected to alternate nodes of the capacitor with overlapping conductive strips connected to the same node. This forms essentially a curtain of conductive strips and interconnecting vias connected to the first node of the capacitor with adjacent curtains of conductive strips and interconnecting vias connected to the second node. Overlapping conductive strips connected to the same node avoids the lost surface area associated with buss strips; however, inter-layer capacitance is reduced because the upper strip is connected to the same node as the lower strip. This effect is somewhat obviated because, as critical dimensions shrink, inter-strip capacitance becomes more dominant than inter-layer capacitance. In other words, the dielectric layer separation between successive metal layers becomes increasingly greater than the dielectric separation between conductive strips with decreasing critical dimension.
- integrated capacitors overcoming the disadvantages of prior art are desired. It is further generally desired that integrated capacitors have high capacitance per unit area, low loss (resistance), and low self-inductance, which improves high-frequency applications by increasing self-resonant frequency and the quality of capacitor circuits. In some applications, it is further desirable to shield integrated capacitors from electrical noise.
- a capacitor in an integrated circuit has a distribution grid formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament connected to and extending away from the distribution grid along a first direction.
- a second vertical conductive filament is connected to the distribution grid and extends in the opposite direction.
- a first and second grid plates are formed in the metal layers above and below the first patterned metal layer. The grid plates surround the first and second vertical conductive filaments.
- the distribution grid, first vertical conductive filament and second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a portion of a second node of the capacitor.
- FIG. 1 A is an isometric view of a portion of an integrated capacitor with horizontal cabled filaments according to an embodiment.
- FIG. 1 B is a side view of the integrated capacitor of FIG. 1 A incorporated in the backend layers of an integrated circuit.
- FIG. 2A is an isometric view of a portion of an integrated capacitor with vertical cabled filaments according to an embodiment of the present invention.
- FIG. 2B is a cross section of the integrated capacitor of FIG. 2A as seen along section line B-B.
- FIG. 2C is a cross section of the integrated capacitor of FIG. 2A as seen along section line C-C.
- FIG. 3 is an isometric view of the integrated capacitor of FIG. 2A with some of the layers removed to illustrate further details of the integrated capacitor.
- FIG. 4 is an isometric view of the integrated capacitor of FIG. 2A with plate encasings according to another embodiment.
- FIG. 5 is a plan view of an FPGA incorporating an integrated capacitor according to an embodiment.
- Complex ICs such as programmable logic devices, often have several patterned metal layers separated by layers of dielectric material formed over a semiconductor substrate that are used for wiring connections and other functions.
- Some embodiments of the invention are adaptable to existing CMOS process sequences by using masks that form the desired patterns in the appropriate metal layers and vias through the inter-metal dielectric ("IMD") layers or inter-layer dielectric (“ILD").
- the vias are formed using any of several known techniques, such as contact plug, damascene, or dual damascene techniques.
- the conductive strips are formed using any of several known techniques, such as thin-film metal etch, thin-film metal lift-off, damascene, and dual damascene techniques.
- one of the conductive layers is a polysilicon or suicide layer.
- a conductive well in the semiconductor substrate forms a portion of a capacitor plate or a shield.
- Embodiments of the invention are referred to as “cabled” because conductors, such as horizontal filaments or vertical columns, electrically connected to one node of the capacitor are surrounded by conductors electrically connected the other node of the capacitor, similar to how a conductive sheath surrounds a center conductor of a co-axial cable to shield the inner conductor from electrical noise.
- Some embodiments use horizontal filaments connected to a first node, which in a particular embodiment is a top node of a switching capacitor in an IC, surrounded by filaments electrically connected to a second node (e.g., bottom node) formed in multiple layers and interconnected with conductive vias ("vias").
- conductive columns connected to the first node surrounded by conductive grids connected to the second node.
- the conductive grids are formed in successive metal layers and are interconnected with vias that provide additional lateral capacitance to corresponding vias in the conductive columns. High specific capacitance with good noise shielding is achieved.
- FIG. 1 A is an isometric view of a portion 100 of an integrated capacitor according to an embodiment.
- the view shows the conductive portions of the integrated capacitor with dielectric material removed for purposes of illustration.
- dielectric material(s) such as silicon dioxide or fluid-based dielectric materials fill the spaces between the conductive portions.
- the integrated capacitor has conductive vertical panels ("conductive curtains") 102, 104 alternating with interleaved vertical planes 105, 106 in which conductive elements connected to a first node of the capacitor alternate with conductive elements connected to the second node of the capacitor in successive layers of the backend stack.
- the conductive curtain 102 has a number of conductive filaments 108, 11 , 112, 114, 116 formed in successive patterned metal layers running horizontally (i.e., along the X direction) with conductive vias 118, 120 connecting filaments in successive patterned metal layers in the X direction to form a conductive plate in the plane defined by the X and Z directions .
- the conductive curtains are connected to one of the electrical nodes of the integrated capacitor, and in a particular embodiment the conductive curtains are connected to the bottom node of a switching integrated capacitor.
- the conductive filaments are metal traces, such as those formed using damascene or dual damascene techniques.
- the conductive vias are also formed using a dual damascene technique.
- the interleaved vertical planes 105, 106 have horizontal conductive filaments 122, 126, 130 connected to the first node of the integrated capacitor interleaved with horizontal conductive filaments 124, 128 connected to the second node of the integrated capacitor.
- the horizontal conductive filament 124 of the second node is surrounded by conductive filaments 122, 110, 126, 132 (and to a further extent diagonal filaments, e.g. 108, 112) of the first node. This provides high specific capacitance between the first node filaments and the second node, and also electrically shields the first node conductive filament 124, which in a specific embodiment is the top node of an integrated switching capacitor, from electronic noise and cross-coupling from other IC components and traces.
- Shielding of the top node conductive elements (e.g., conductive filaments 124, 128) by bottom node conductive elements (e.g., conductive filaments and vias in conductive curtains 102, 104 and conductive filaments 122, 126, 130) is desirable for insuring low-distortion sampled data transfers in an IC, for example.
- an optional ground shield is used to shield the bottom node from electronic noise and cross-coupling.
- each major surface (i.e., top, bottom, and both sides) of a conductor connected to one node of the capacitor e.g., top node conductive filament 124) is adjacent to a conductor connected to the other node of the capacitor (e.g., bottom node conductive filaments 122, 108, 110, 126, 132).
- the conductive filaments in the upper-most metal layer are all connected to one node (e.g. the bottom node) of the capacitor.
- Other metal layers also have conductive elements connected to a single node, such as the M3 and M1 layers shown in FIG. 1 B.
- the conductive filaments in these single-node layers can be cross- connected by conductive cross members to form a conductive grid plate (compare, FIG. 2A, ref. num. 208).
- the conductive filaments electrically connected to the top node can be interconnected using buss bars and vias (not shown) at one end of the filaments, for example.
- a transverse conductive curtain (i.e., in the plane defined by the Y and Z directions) of the bottom node is added so that ends of the conductive filaments connected to the top node are covered.
- cross members i.e., in the Y direction
- a gap would be provided to allow the cross connection.
- a gap in filament 132 would allow a cross member to extend from filament 124 to filament 125.
- a conductive curtain in the plane defined by the Z and Y axes connected to the bottom node is optionally included to shield the end surfaces of the filaments 124, 125 connected to the top node.
- connection to the top node can be lead through the top-most or bottom-most bottom node layer, or out one end or the other of the interconnected top node conductive filaments (see, e.g., FIG. 2A, ref. num. 218).
- a bottom node layer shields a trace from the top node of the integrated capacitor to the connection to a switch in a switched capacitor implementation. The capacitance between the trace and the bottom node shielding adds to the capacitance of the integrated capacitor.
- top node and bottom node do not necessarily relate to the physical orientation of the nodes relative to the IC or other structure, but are used as terms of convenience.
- the top node of a capacitor indicates the node that is connected to a high-impedance or high-gain port of an amplifier or other device.
- SoC system-on-chip
- ADC analog-to-digital converter
- C top the top node
- C s ⁇ g the capacitance
- Using the bottom node to essentially surround the top node isolates the top node from coupling with other nodes in the circuit by essentially forming a portion of Faraday shell around the top node, and in some embodiments, distancing the top node from other conductive elements in the IC. It is understood by those of skill in the art that electrical connection to the top node is made through the bottom node shield, and therefore the bottom node shield does not completely surround the top node.
- Capacitors are generally useful in a wide variety of integrated circuits and in a wide variety of applications. For instance, one or more capacitors may be useful for a switched capacitor network, such as in an analog-to-digital converter, or as a decoupling or filtering capacitor for AC signaling (e.g., in an MGT).
- the capacitor structure described herein may be useful in any application requiring capacitance. Note that a capacitor is generally thought of as a two terminal device, and the "top" and “bottom” nodes as described herein generally correspond to these two terminals of the capacitor.
- the structures described below may be thought of as connecting (e.g., electrically) to one or the other node, or forming portions of a node. A node is not separate from the capacitive structures connected to it, but those structures may form portions of a node.
- Design rules typically have a maximum trace (filament) width, and layers, such as the top, middle, and bottom 140 layers of the integrated capacitor 100 are formed of conductive strips, rather than a contiguous conductive plate.
- the bottom conductive layer is formed in a polysilicon or suicide layer, rather than being patterned in a metal layer, and is formed as a contiguous conductive plate.
- other layers may be formed as contiguous conductive plates, depending on the limitations of the manufacturing process. For instance, wider metal strips or even metal plates may be used in some embodiments. As another example, in a multiple poly process, multiple poly contiguous conductive plates may be used. Also, in some instances "trench" contacts and vias may be used, which may increase the capacitive and shielding effects of the curtains.
- the capacitance between the nodes of the capacitor is established by the capacitive coupling between the conductive elements connected to the bottom node and the conductive elements connected to the top node, as is well known in the art.
- the horizontal and vertical spacing between conductive filaments is shown as being about equal, in many IC fabrication technologies, the vertical separation between patterned metal layers is greater than the minimum required separation between conductive filaments within a patterned metal layer.
- the capacitance between conductive filaments within a layer such as between top node conductive filament 124 and bottom node conductive filament 132 will be referred to as lateral capacitance, and the capacitance between top node conductive filament 124 and bottom node conductive filament 126 or 122 will be referred to as vertical capacitance.
- the lateral capacitance per unit length of adjacent filaments can be greater than the vertical capacitance if the inter-filament spacing is sufficiently close.
- the spacing and width of the various elements may be varied in some embodiments. For instance, non-minimum width and/or spacing may be used, which may improve manufacturability or reliability. In general, the dimensions may be chosen to meet the needs of the particular application.
- FIG. 1 B is a side view of the integrated capacitor of FIG. 1 A incorporated in the backend layers of an integrated circuit.
- the backend layers include five metal layers M1 , M2, M3, M4, M5 and intervening dielectric layers IMD2, IMD3, IMD4, IMD5.
- Conductive vias such as conductive via 120, connect conductive structures, such as conductive filaments 110, 112.
- conductive vias and metal layers are formed using dual damascene and chemical-mechanical polishing ("CMP") techniques.
- CMP chemical-mechanical polishing
- a polysilicon layer, suicide layer, or doped semiconductor i.e., a conductive well formed in a semiconductor wafer is used for one or more lower conductive layers.
- FIG. 2A is an isometric view of a portion of an integrated capacitor 200 with vertical cabled filaments according to an embodiment of the present invention.
- operabled refers to vertical filaments 202, 204 electrically connected to a first node of the capacitor extending through apertures in a grid plate 208 electrically connected to a second node of the capacitor such that the vertical filaments are surrounded by second node conductors, similar to how a sheath of a coaxial cable surrounds the center conductor.
- a first conductive matrix is formed of vertical conductive filaments 202, 204, 206 and cross members (see FIG. 3, ref. nums. 212, 214) in an intermediate layer (see FIG. 3, ref. num. 216).
- a center tap 218 extends through a gap 219 in a perimeter shield conductor 221 formed in the third metal layer and allows electrical connection to a distribution grid of the first conductive matrix, which is otherwise essentially surrounded by the perimeter shield conductor 221.
- the first conductive matrix is connected to the top node of the integrated capacitor and the second conductive matrix is connected to the bottom node of the integrated capacitor and provides shielding for the top node.
- the center tap 218 provides electrical connection of the distribution grid and to vertical conductive filaments extending in opposite directions from the distribution grid to a node of the integrated capacitor.
- a side of the perimeter shield is omitted, such as when capacitors are stepped to form an array of capacitors.
- a single bottom node shield may be shared by two adjacent capacitors, or is optionally omitted. Note that although it is referred to herein as a "center tap," the connection to the first conductive matrix may be made at any point, for instance along the edges, and may be made in any suitable layer, such as M2 or M4.
- the second conductive matrix is formed of grid plates 208, 209, 210, 211 above and below a distribution layer (e.g., the layer in which center tap 218 is formed in).
- the lowest plate layer 209 is formed in a polysilicon or suicide layer as a contiguous sheet.
- Vertical conductive filaments extend up and down from the distribution layer (see, e.g., FIG. 3) and conductive vias 220, 222.
- the grid plates are essentially conductive grids that have apertures through which the vertical conductive filaments of the complementary node plate (e.g., the vertical conductive filaments of the top node plate) extend.
- a vertical conductive filament extends upwards from the distribution layer, and a corresponding vertical conductive filament extends downwards from the distribution layer.
- This arrangement provides lower and more evenly distributed resistive and inductive components of the capacitor impedance from the distribution layer and center tap, compared to a similar design using long filaments (fingers) connected at their endpoints.
- FIG. 2B is a cross section of the integrated capacitor of FIG. 2A as seen along section line B-B. Only the sectioned portions of the first and second conductive matrices are shown, and intervening dielectric material is omitted for clarity of illustration.
- the grid plates 208 and 210 surround conductive filament 223 and other conductive filaments extending in both directions from a cross member 228 formed in the intermediate metal layer M3.
- Conductive vias such as conductive via 220, electrically connects grid plates 208, 210 formed in successive metal layers M4, M5. Similar conductive vias connect other conductive structures formed in adjacent metal layers M1 , M2, M3, M4, M5.
- the layers are shifted so that the lowest layer (illustrated M1 ) is a poly layer formed as a contiguous sheet rather than as filaments.
- integrated capacitors are formed in backend stacks having greater or fewer metal layers.
- an integrated capacitor similar to integrated capacitor 200 of FIG. 2A is formed in a backend stack having four metal layers by forming the bottom-most grid plate and ends of the vertical conductive filaments of the top node matrix in a layer of polysilicon or suicide ("poly" layer).
- the vertical filaments terminate in the M1 layer and the poly layer forms a node shield plate.
- a node plate can be formed in the poly layer as a contiguous sheet, rather than a series of conductive strips (filaments) or conductive grid.
- the bottom-most grid plate is formed in a conductive well of a semiconductor substrate, and contacts are used to electrically connect the conductive well to the metal matrix of the bottom node, thus allowing an integrated capacitor according to an embodiment to be formed in a backend stack having three metal layers, using the poly layer.
- additional metal layers allow extending the vertical conductive filaments of the top node and forming associated grid plates around them.
- FIG. 2C is a cross section of the integrated capacitor of FIG. 2A as seen along section line C-C. Only the sectioned portions of the first and second conductive matrices are shown, intervening dielectric material is omitted for clarity of illustration.
- Top node cross member 214 is surrounded by conductive elements of the bottom node that form a three-dimensional conductive matrix in a distribution layer of the integrated capacitor. A portion of the upper grid plate 225 (removed for purposes of illustration in FIG. 3) and lower grid plate 224 are shown in cross section.
- FIG. 3 is an isometric view of the integrated capacitor of FIG. 2A with some of the layers removed to illustrate further details of the integrated capacitor.
- a grid plate 224 connected to the bottom node is below a distribution grid 226, which is connected to the top node.
- the distribution grid has cross members 212, 214 connecting vertical filaments extending in opposite directions from the distribution layer (e.g., M3).
- the top node distribution layer is formed in the middle layer, but is alternatively formed in other layers.
- the vertical filaments extend further in one direction (i.e., thorough more metal layers) than in the opposite direction.
- FIG. 4 is an isometric view of an integrated capacitor 400 similar to the embodiment of FIG. 2A with plate encasings 402 according to another embodiment.
- the plate encasings cover the top ends of the vertical conductive filaments of the top node and provide additional shielding to the top node, as well as increasing the specific capacitance per unit area of the integrated capacitor, as the ends of conductive filaments capacitively couple with the plate encasings.
- the lowest conductive grid plate 404 is formed in a polysilicon or suicide layer ("poly" layer), and metal layers M1 , M2, M3, M4 are used to form conductive matrices of the integrated capacitor in conjunction with the poly, and with metal layer M5.
- the integrated capacitor 400 including the plate encasings 402 are achieved in a five-metal layer backend stack.
- FIG. 5 is a plan view of an FPGA 500 semiconductor device incorporating an integrated capacitor according to an embodiment.
- the FPGA 500 includes CMOS portions in several of the functional blocks, such as in RAM and logic, and is fabricated using a CMOS fabrication process.
- One or more integrated capacitors 555 are incorporated in any of several functional blocks of the FPGA, such as a clock circuit 505, a multi-gigabit transceivers 501 , or other functional block; within many functional blocks; or within a physical section or segment of the FPGA 500.
- Integrated capacitors 555 are particularly desirable in applications where one or both terminals of the capacitor are switched, and embodiments including top node shielding are further desirable in applications wherein the top node is connected to or switched to a high-impedance or high-gain node of a circuit in the FPGA 500.
- the FPGA architecture includes a large number of different programmable tiles including multi-gigabit transceivers (MGTs 501 ), configurable logic blocks (CLBs 502), random access memory blocks (BRAMs 503), input/output blocks (lOBs 504), configuration and clocking logic (CONFIG/CLOCKS 505), digital signal processing blocks (DSPs 506), specialized input/output blocks (I/O 507) (e.g., configuration ports and clock ports), and other programmable logic 508 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth.
- Some FPGAs also include dedicated processor blocks (PROC 510).
- each programmable tile includes a programmable interconnect element (INT 511 ) having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA.
- the programmable interconnect element (INT 511 ) also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of FIG. 5.
- a CLB 502 can include a configurable logic element (CLE 512) that can be programmed to implement user logic plus a single programmable interconnect element (INT 511 ).
- a BRAM 503 can include a
- BRAM logic element in addition to one or more programmable interconnect elements.
- the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used.
- a DSP tile 506 can include a DSP logic element (DSPL 514) in addition to an appropriate number of programmable interconnect elements.
- An IOB 504 can include, for example, two instances of an input/output logic element (IOL 515) in addition to one instance of the programmable interconnect element (INT 511 ).
- the actual I/O pads connected, for example, to the I/O logic element 515 are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element 515.
- a columnar area near the center of the die is used for configuration, clock, and other control logic.
- Some FPGAs utilizing the architecture illustrated in FIG. 5 include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA.
- the additional logic blocks can be programmable blocks and/or dedicated logic.
- the processor block PROC 510 shown in FIG. 5 spans several columns of CLBs and BRAMs.
- FIG. 5 is intended to illustrate only an exemplary FPGA architecture.
- the numbers of logic blocks in a column, the relative widths of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of FIG. 5 are purely exemplary.
- more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic.
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Abstract
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JP2011537483A JP5540007B2 (ja) | 2008-11-21 | 2009-10-23 | グリッドプレートを有する集積キャパシタ |
CN2009801465681A CN102224567B (zh) | 2008-11-21 | 2009-10-23 | 具有缆线平板的整合电容器 |
EP09741553.3A EP2347435B1 (fr) | 2008-11-21 | 2009-10-23 | Condensateur intégré à plaques de réseau |
KR1020117014063A KR101252989B1 (ko) | 2008-11-21 | 2009-10-23 | 그리드 판들을 갖는 집적 캐패시터 |
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US12/276,293 US8362589B2 (en) | 2008-11-21 | 2008-11-21 | Integrated capacitor with cabled plates |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110970561A (zh) * | 2016-10-10 | 2020-04-07 | 华为技术有限公司 | 电容单元、集成电容和谐振单元 |
CN112204735A (zh) * | 2018-03-13 | 2021-01-08 | 铠侠股份有限公司 | 用于选择性外合的电力岛分段 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8294240B2 (en) * | 2009-06-08 | 2012-10-23 | Qualcomm Incorporated | Through silicon via with embedded decoupling capacitor |
US8618635B2 (en) | 2010-10-27 | 2013-12-31 | Infineon Technologies Ag | Capacitors in integrated circuits and methods of fabrication thereof |
US8410579B2 (en) | 2010-12-07 | 2013-04-02 | Xilinx, Inc. | Power distribution network |
US8569861B2 (en) | 2010-12-22 | 2013-10-29 | Analog Devices, Inc. | Vertically integrated systems |
US8653844B2 (en) | 2011-03-07 | 2014-02-18 | Xilinx, Inc. | Calibrating device performance within an integrated circuit |
FR2976715B1 (fr) * | 2011-06-15 | 2013-06-28 | St Microelectronics Sa | Dispositif capacitif integre et convertisseur analogique numerique integre comprenant un tel dispositif |
US8941974B2 (en) | 2011-09-09 | 2015-01-27 | Xilinx, Inc. | Interdigitated capacitor having digits of varying width |
GB2526462B (en) * | 2013-03-15 | 2020-03-18 | Intel Corp | Integrated capacitor based power distribution |
US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
US10978387B2 (en) * | 2017-05-25 | 2021-04-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10730743B2 (en) | 2017-11-06 | 2020-08-04 | Analog Devices Global Unlimited Company | Gas sensor packages |
US10892099B2 (en) | 2017-12-18 | 2021-01-12 | Nxp Usa, Inc. | Fringe capacitor for high resolution ADC |
US10476514B1 (en) | 2018-05-30 | 2019-11-12 | Xilinx, Inc. | Circuit for and method of receiving data in an integrated circuit |
US11587839B2 (en) | 2019-06-27 | 2023-02-21 | Analog Devices, Inc. | Device with chemical reaction chamber |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003090280A1 (fr) * | 2002-04-19 | 2003-10-30 | Infineon Technologies Ag | Composant a semi-conducteur a structure de capacite integree et procede permettant de le produire |
US20050135042A1 (en) * | 2003-12-19 | 2005-06-23 | Broadcom Corporation | Scalable integrated circuit high density capacitors |
US20050161725A1 (en) * | 2002-04-19 | 2005-07-28 | Nicola Da Dalt | Semiconductor component comprising an integrated latticed capacitance structure |
US7013436B1 (en) * | 2003-05-25 | 2006-03-14 | Barcelona Design, Inc. | Analog circuit power distribution circuits and design methodologies for producing same |
US7038296B2 (en) * | 2003-02-06 | 2006-05-02 | Zarlink Semiconductor Limited | Electrical component structure |
US20070181973A1 (en) * | 2006-02-06 | 2007-08-09 | Cheng-Chou Hung | Capacitor structure |
US20070190760A1 (en) * | 2006-01-13 | 2007-08-16 | Coolbaugh Douglas D | Integrated parallel plate capacitors |
Family Cites Families (103)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1899176A (en) | 1929-10-24 | 1933-02-28 | Gen Electric | High frquency condenser |
GB1149569A (en) | 1966-09-01 | 1969-04-23 | Mini Of Technology | Capacitors and methods for their manufacture |
US3593319A (en) | 1968-12-23 | 1971-07-13 | Gen Electric | Card-changeable capacitor read-only memory |
GB1469944A (en) | 1975-04-21 | 1977-04-06 | Decca Ltd | Planar capacitor |
NL7609587A (nl) | 1975-09-08 | 1977-03-10 | Ncr Co | Elektrisch afstembare mnos-capaciteit. |
DE2548563A1 (de) | 1975-10-30 | 1977-05-05 | Licentia Gmbh | Verfahren zum herstellen eines kondensators |
US4249196A (en) | 1978-08-21 | 1981-02-03 | Burroughs Corporation | Integrated circuit module with integral capacitor |
US4427457A (en) | 1981-04-07 | 1984-01-24 | Oregon Graduate Center | Method of making depthwise-oriented integrated circuit capacitors |
US4409608A (en) | 1981-04-28 | 1983-10-11 | The United States Of America As Represented By The Secretary Of The Navy | Recessed interdigitated integrated capacitor |
US4470096A (en) | 1982-06-18 | 1984-09-04 | Motorola Inc. | Multilayer, fully-trimmable, film-type capacitor and method of adjustment |
US4470099A (en) | 1982-09-17 | 1984-09-04 | Matsushita Electric Industrial Co., Ltd. | Laminated capacitor |
US4571543A (en) | 1983-03-28 | 1986-02-18 | Southwest Medical Products, Inc. | Specific material detection and measuring device |
DE3326957C2 (de) | 1983-07-27 | 1986-07-31 | Telefunken electronic GmbH, 7100 Heilbronn | Integrierte Schaltung |
JPH0682783B2 (ja) | 1985-03-29 | 1994-10-19 | 三菱電機株式会社 | 容量およびその製造方法 |
US4827323A (en) | 1986-01-07 | 1989-05-02 | Texas Instruments Incorporated | Stacked capacitor |
US4831431A (en) | 1986-03-31 | 1989-05-16 | Honeywell Inc. | Capacitance stabilization |
JPS6370550A (ja) | 1986-09-12 | 1988-03-30 | Nec Corp | 半導体集積回路装置 |
US4878151A (en) | 1987-04-10 | 1989-10-31 | National Semiconductor Corporation | Anti-parallel capacitor |
US4731696A (en) | 1987-05-26 | 1988-03-15 | National Semiconductor Corporation | Three plate integrated circuit capacitor |
US4994688A (en) | 1988-05-25 | 1991-02-19 | Hitachi Ltd. | Semiconductor device having a reference voltage generating circuit |
US4914546A (en) | 1989-02-03 | 1990-04-03 | Micrel Incorporated | Stacked multi-polysilicon layer capacitor |
JPH02268439A (ja) | 1989-04-10 | 1990-11-02 | Hitachi Ltd | 半導体集積回路装置 |
US5089878A (en) | 1989-06-09 | 1992-02-18 | Lee Jaesup N | Low impedance packaging |
EP0412514A1 (fr) | 1989-08-08 | 1991-02-13 | Nec Corporation | Dispositif capacitif |
US5117114A (en) | 1989-12-11 | 1992-05-26 | The Regents Of The University Of California | High resolution amorphous silicon radiation detectors |
US5021920A (en) | 1990-03-30 | 1991-06-04 | Texas Instruments Incorporated | Multilevel integrated circuit capacitor and method of fabrication |
JPH0831392B2 (ja) | 1990-04-26 | 1996-03-27 | 株式会社村田製作所 | 積層コンデンサ |
JP2504606B2 (ja) | 1990-05-18 | 1996-06-05 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
JP2590618B2 (ja) | 1990-05-31 | 1997-03-12 | 松下電器産業株式会社 | 画像表示装置 |
US5005103A (en) | 1990-06-05 | 1991-04-02 | Samsung Electronics Co., Ltd. | Method of manufacturing folded capacitors in semiconductor and folded capacitors fabricated thereby |
US5077225A (en) | 1991-04-30 | 1991-12-31 | Micron Technology, Inc. | Process for fabricating a stacked capacitor within a monolithic integrated circuit using oxygen implantation |
US5189594A (en) | 1991-09-20 | 1993-02-23 | Rohm Co., Ltd. | Capacitor in a semiconductor integrated circuit and non-volatile memory using same |
US5166858A (en) | 1991-10-30 | 1992-11-24 | Xilinx, Inc. | Capacitor formed in three conductive layers |
US5155658A (en) | 1992-03-05 | 1992-10-13 | Bell Communications Research, Inc. | Crystallographically aligned ferroelectric films usable in memories and method of crystallographically aligning perovskite films |
US5275974A (en) | 1992-07-30 | 1994-01-04 | Northern Telecom Limited | Method of forming electrodes for trench capacitors |
US5208725A (en) | 1992-08-19 | 1993-05-04 | Akcasu Osman E | High capacitance structure in a semiconductor device |
AUPM596394A0 (en) | 1994-05-31 | 1994-06-23 | Dyksterhuis, Francis Henry | Games and puzzles |
US5583359A (en) * | 1995-03-03 | 1996-12-10 | Northern Telecom Limited | Capacitor structure for an integrated circuit |
US5646619A (en) * | 1995-04-26 | 1997-07-08 | Lucent Technologies Inc. | Self-calibrating high speed D/A converter |
US5872697A (en) | 1996-02-13 | 1999-02-16 | International Business Machines Corporation | Integrated circuit having integral decoupling capacitor |
US5939766A (en) | 1996-07-24 | 1999-08-17 | Advanced Micro Devices, Inc. | High quality capacitor for sub-micrometer integrated circuits |
US5712813A (en) | 1996-10-17 | 1998-01-27 | Zhang; Guobiao | Multi-level storage capacitor structure with improved memory density |
US6064108A (en) | 1997-09-02 | 2000-05-16 | Hughes Electronics Corporation | Integrated interdigitated capacitor |
US6066537A (en) | 1998-02-02 | 2000-05-23 | Tritech Microelectronics, Ltd. | Method for fabricating a shielded multilevel integrated circuit capacitor |
JP2000010000A (ja) * | 1998-06-24 | 2000-01-14 | Olympus Optical Co Ltd | 結像光学系 |
US6037621A (en) | 1998-07-29 | 2000-03-14 | Lucent Technologies Inc. | On-chip capacitor structure |
US6677637B2 (en) | 1999-06-11 | 2004-01-13 | International Business Machines Corporation | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same |
JP4446525B2 (ja) | 1999-10-27 | 2010-04-07 | 株式会社ルネサステクノロジ | 半導体装置 |
US6417556B1 (en) | 2000-02-02 | 2002-07-09 | Advanced Micro Devices, Inc. | High K dielectric de-coupling capacitor embedded in backend interconnect |
US6383858B1 (en) | 2000-02-16 | 2002-05-07 | Agere Systems Guardian Corp. | Interdigitated capacitor structure for use in an integrated circuit |
US6303456B1 (en) | 2000-02-25 | 2001-10-16 | International Business Machines Corporation | Method for making a finger capacitor with tuneable dielectric constant |
US6297524B1 (en) | 2000-04-04 | 2001-10-02 | Philips Electronics North America Corporation | Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS |
US6747307B1 (en) | 2000-04-04 | 2004-06-08 | Koninklijke Philips Electronics N.V. | Combined transistor-capacitor structure in deep sub-micron CMOS for power amplifiers |
US6822312B2 (en) | 2000-04-07 | 2004-11-23 | Koninklijke Philips Electronics N.V. | Interdigitated multilayer capacitor structure for deep sub-micron CMOS |
US6410954B1 (en) | 2000-04-10 | 2002-06-25 | Koninklijke Philips Electronics N.V. | Multilayered capacitor structure with alternately connected concentric lines for deep sub-micron CMOS |
US6570210B1 (en) | 2000-06-19 | 2003-05-27 | Koninklijke Philips Electronics N.V. | Multilayer pillar array capacitor structure for deep sub-micron CMOS |
US7259945B2 (en) | 2000-08-09 | 2007-08-21 | Server Technology, Inc. | Active arc-suppression circuit, system, and method of use |
US6635916B2 (en) | 2000-08-31 | 2003-10-21 | Texas Instruments Incorporated | On-chip capacitor |
US6625006B1 (en) | 2000-09-05 | 2003-09-23 | Marvell International, Ltd. | Fringing capacitor structure |
US6974744B1 (en) | 2000-09-05 | 2005-12-13 | Marvell International Ltd. | Fringing capacitor structure |
US6690570B2 (en) | 2000-09-14 | 2004-02-10 | California Institute Of Technology | Highly efficient capacitor structures with enhanced matching properties |
US6385033B1 (en) | 2000-09-29 | 2002-05-07 | Intel Corporation | Fingered capacitor in an integrated circuit |
US6653681B2 (en) * | 2000-12-30 | 2003-11-25 | Texas Instruments Incorporated | Additional capacitance for MIM capacitors with no additional processing |
US6980414B1 (en) | 2004-06-16 | 2005-12-27 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
JP2002299555A (ja) * | 2001-03-30 | 2002-10-11 | Seiko Epson Corp | 集積回路およびその製造方法 |
US6542351B1 (en) | 2001-06-28 | 2003-04-01 | National Semiconductor Corp. | Capacitor structure |
US6548400B2 (en) | 2001-06-29 | 2003-04-15 | Texas Instruments Incorporated | Method of fabricating interlevel connectors using only one photomask step |
US6437431B1 (en) | 2001-08-07 | 2002-08-20 | Lsi Logic Corporation | Die power distribution system |
US6740922B2 (en) | 2001-08-14 | 2004-05-25 | Agere Systems Inc. | Interdigitated capacitor and method of manufacturing thereof |
JP3987703B2 (ja) * | 2001-10-12 | 2007-10-10 | Necエレクトロニクス株式会社 | 容量素子及びその製造方法 |
JP3977053B2 (ja) * | 2001-10-30 | 2007-09-19 | 富士通株式会社 | 容量素子及びその製造方法 |
US6661079B1 (en) | 2002-02-20 | 2003-12-09 | National Semiconductor Corporation | Semiconductor-based spiral capacitor |
US6737698B1 (en) | 2002-03-11 | 2004-05-18 | Silicon Laboratories, Inc. | Shielded capacitor structure |
GB0207857D0 (en) | 2002-04-05 | 2002-05-15 | Zarlink Semiconductor Ltd | Integrated circuit capacitors |
US7271465B2 (en) | 2002-04-24 | 2007-09-18 | Qualcomm Inc. | Integrated circuit with low-loss primary conductor strapped by lossy secondary conductor |
TW541646B (en) | 2002-07-11 | 2003-07-11 | Acer Labs Inc | Polar integrated capacitor and method of making same |
DE10249192A1 (de) | 2002-10-22 | 2004-05-13 | Infineon Technologies Ag | Elektronisches Bauelement mit integriertem passiven elektronischen Bauelement und Verfahren zu dessen Herstellung |
DE10301243B4 (de) * | 2003-01-15 | 2009-04-16 | Infineon Technologies Ag | Verfahren zum Herstellen einer integrierten Schaltungsanordnung, insbesondere mit Kondensatoranordnung |
DE10303738B4 (de) | 2003-01-30 | 2007-12-27 | Infineon Technologies Ag | Speicherkondensator und Speicherzellenanordnung |
US6963122B1 (en) | 2003-02-21 | 2005-11-08 | Barcelona Design, Inc. | Capacitor structure and automated design flow for incorporating same |
US6819542B2 (en) | 2003-03-04 | 2004-11-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interdigitated capacitor structure for an integrated circuit |
US6765778B1 (en) | 2003-04-04 | 2004-07-20 | Freescale Semiconductor, Inc. | Integrated vertical stack capacitor |
US6880134B2 (en) | 2003-04-09 | 2005-04-12 | Freescale Semiconductor, Inc. | Method for improving capacitor noise and mismatch constraints in a semiconductor device |
US7132851B2 (en) * | 2003-07-11 | 2006-11-07 | Xilinx, Inc. | Columnar floorplan |
US6949781B2 (en) | 2003-10-10 | 2005-09-27 | Taiwan Semiconductor Manufacturing Co. Ltd. | Metal-over-metal devices and the method for manufacturing same |
US7050290B2 (en) | 2004-01-30 | 2006-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated capacitor |
US6903918B1 (en) | 2004-04-20 | 2005-06-07 | Texas Instruments Incorporated | Shielded planar capacitor |
FR2870042B1 (fr) | 2004-05-07 | 2006-09-29 | St Microelectronics Sa | Structure capacitive de circuit integre |
US7154734B2 (en) | 2004-09-20 | 2006-12-26 | Lsi Logic Corporation | Fully shielded capacitor cell structure |
JP4343085B2 (ja) | 2004-10-26 | 2009-10-14 | Necエレクトロニクス株式会社 | 半導体装置 |
US7009832B1 (en) | 2005-03-14 | 2006-03-07 | Broadcom Corporation | High density metal-to-metal maze capacitor with optimized capacitance matching |
US7202548B2 (en) | 2005-09-13 | 2007-04-10 | Via Technologies, Inc. | Embedded capacitor with interdigitated structure |
TWI296852B (en) | 2005-12-07 | 2008-05-11 | Winbond Electronics Corp | Interdigitized capacitor |
US7161228B1 (en) | 2005-12-28 | 2007-01-09 | Analog Devices, Inc. | Three-dimensional integrated capacitance structure |
US8169014B2 (en) * | 2006-01-09 | 2012-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interdigitated capacitive structure for an integrated circuit |
TWI271754B (en) * | 2006-02-16 | 2007-01-21 | Jmicron Technology Corp | Three-dimensional capacitor structure |
KR100876881B1 (ko) | 2006-02-24 | 2008-12-31 | 주식회사 하이닉스반도체 | 반도체 소자의 패드부 |
US7274085B1 (en) | 2006-03-09 | 2007-09-25 | United Microelectronics Corp. | Capacitor structure |
KR20090033177A (ko) | 2006-06-02 | 2009-04-01 | 케네트, 인크 | 개선된 금속-절연체-금속 캐패시터 |
US8330251B2 (en) | 2006-06-26 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device structure for reducing mismatch effects |
TWI320964B (en) * | 2006-12-29 | 2010-02-21 | Ind Tech Res Inst | Face center cube capacitor and manufacture method thereof |
JP2008226998A (ja) * | 2007-03-09 | 2008-09-25 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
US20090057826A1 (en) | 2007-09-04 | 2009-03-05 | Kim Sun-Oo | Semiconductor Devices and Methods of Manufacture Thereof |
-
2008
- 2008-11-21 US US12/276,293 patent/US8362589B2/en active Active
-
2009
- 2009-10-23 EP EP09741553.3A patent/EP2347435B1/fr active Active
- 2009-10-23 JP JP2011537483A patent/JP5540007B2/ja active Active
- 2009-10-23 KR KR1020117014063A patent/KR101252989B1/ko active IP Right Grant
- 2009-10-23 WO PCT/US2009/061958 patent/WO2010059336A1/fr active Application Filing
- 2009-10-23 CN CN2009801465681A patent/CN102224567B/zh active Active
- 2009-11-19 TW TW098139286A patent/TWI409838B/zh active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003090280A1 (fr) * | 2002-04-19 | 2003-10-30 | Infineon Technologies Ag | Composant a semi-conducteur a structure de capacite integree et procede permettant de le produire |
US20050161725A1 (en) * | 2002-04-19 | 2005-07-28 | Nicola Da Dalt | Semiconductor component comprising an integrated latticed capacitance structure |
US7038296B2 (en) * | 2003-02-06 | 2006-05-02 | Zarlink Semiconductor Limited | Electrical component structure |
US7013436B1 (en) * | 2003-05-25 | 2006-03-14 | Barcelona Design, Inc. | Analog circuit power distribution circuits and design methodologies for producing same |
US20050135042A1 (en) * | 2003-12-19 | 2005-06-23 | Broadcom Corporation | Scalable integrated circuit high density capacitors |
US20070190760A1 (en) * | 2006-01-13 | 2007-08-16 | Coolbaugh Douglas D | Integrated parallel plate capacitors |
US20070181973A1 (en) * | 2006-02-06 | 2007-08-09 | Cheng-Chou Hung | Capacitor structure |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110970561A (zh) * | 2016-10-10 | 2020-04-07 | 华为技术有限公司 | 电容单元、集成电容和谐振单元 |
CN112204735A (zh) * | 2018-03-13 | 2021-01-08 | 铠侠股份有限公司 | 用于选择性外合的电力岛分段 |
CN112204735B (zh) * | 2018-03-13 | 2024-02-20 | 铠侠股份有限公司 | 半导体芯片及其制造方法 |
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US8362589B2 (en) | 2013-01-29 |
EP2347435A1 (fr) | 2011-07-27 |
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TW201027575A (en) | 2010-07-16 |
JP2012509595A (ja) | 2012-04-19 |
US20100127348A1 (en) | 2010-05-27 |
CN102224567B (zh) | 2013-12-18 |
CN102224567A (zh) | 2011-10-19 |
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