Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
  • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
  • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/93—Batch processes
  • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73201—Location after the connecting process on the same surface
  • H01L2224/73203—Bump and layer connectors
  • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73251—Location after the connecting process on different surfaces
  • H01L2224/73253—Bump and layer connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/93—Batch processes
  • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/181—Encapsulation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/181—Encapsulation
  • H01L2924/1815—Shape
  • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
  • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

• the invention relates in general to a package, and more particularly to a semiconductor package and a manufacturing method thereof.
• the IC package structure typically comprises a substrate on which the semiconductor device is disposed.
• the substrate may be damaged due to, for example, cracks in the substrate when the substrate is subjected to stress.
• the substrate may be stressed during the coupling of the semiconductor device to the substrate or the handling of the IC package.
• the structure of the IC package may also be weakened due to additional stress on the substrate and hence renders the IC package more susceptible to damages. Damages in the substrate adversely affect the integrity of the IC package structure, leading to insufficient support for the semiconductor device. It is therefore desirable to provide a solution to address at least one of the foregoing problems of the conventional operations.
• a semiconductor package that includes a device carrier and a stiffener structure.
• the device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit.
• the stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit.
• the stiffener structure is also disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier.
• the manufacturing method includes the steps of: providing a base layer; forming a patterned trace layout on the base layer; forming an insulating layer on the base layer and covering the patterned trace layout for forming a semiconductor substrate; forming a plurality of stiffener structures on the insulating layer to form a plurality of cavities with the insulating layer; and, breaking the semiconductor substrate along a plurality of spaced areas between the stiffener structures for forming a plurality of device carriers.
• FIG. 1a shows a semiconductor package according to a preferred embodiment of the invention
• FIG. 1 b shows a cross-sectional view of the semiconductor package of FIG. 1a along the line A-A';
• FIG. 2a shows the stiffener structure with locking features
• FIG. 2b shows different shapes of the locking elements of FIG. 2a
• FIG. 3a shows the stiffener structure connecting to at least one package trace
• FIG. 3b shows cross-sectional views of the semiconductor package of FIG. 3a along the line B-B';.
• FIG. 4a shows a semiconductor assembly and a semiconductor package
• FIG. 4b shows the semiconductor assembly and the semiconductor package of FIG. 4a each further having a sealing cap
• FIG. 5a shows a carrier array of the semiconductor package
• FIG. 5b and FIG. 5c show different cross-sectional views of the semiconductor package of FIG. 5a along the line C-C;
• FIG. 6 shows the exemplary shapes of the locking elements and the guiding elements
• FIG. 7 shows different structures of the guiding elements
• FIGS. 8a to 8h show the processes of the manufacturing method of semiconductor package.
• FIGS. 9 and 10 show different manufacturing processes for dividing the carrier array.
• FIG. 1a shows a semiconductor package according to a preferred embodiment of the invention
• FIG. 1b shows a cross-sectional view of the semiconductor package of FIG. 1a along the line A-A'.
• the semiconductor package 100 includes a device carrier 110 and a stiffener structure 120.
• the device carrier 110 includes at least one insulating layer 114 and at least conductive layer.
• the device carrier 110 is, for example, a molding substrate and has a first surface 110a and a second surface 110b.
• the material of the insulating layer 114 is a dielectric material or a molding compound.
• the conductive layer has at least one trace layout unit 119a having a periphery 119b.
• the conductive layer includes a plurality of electro-isolated package traces 118a and a plurality of studs 118b.
• the location and number of the studs 118b are preferably in accordance with that of the package traces 118a.
• the package traces 118a are embedded in the first surface 110a
• the studs 118b are embedded in the second surface 110b and electrically connected to the package traces 118a.
• At least one of the studs 118b is used for electrically connecting to other element or any peripheral device.
• the peripheral device is a printed circuit board (PCB), for example, which has a plurality of contact pads in the form of an array.
• the semiconductor package 100 can be assembled to the PCB by welding the studs 118b to connect to the contact pads.
• the stiffener structure 120 is disposed on the first surface 110a and preferably formed during the manufacturing procedure of the device carrier as an integral part of the device carrier.
• the stiffener structure 120 is formed from copper or steel.
• the stiffener structure 120 can have one or more than two laminated layers of the same or different materials.
• the stiffener structure 120 has a first layer whose material is polymer, and has a second layer whose material is metal.
• the stiffener structure 120 is spaced away from the periphery 119b of the trace layout unit 119a and disposed along the periphery 119b for forming a ring-shaped structure.
• the stiffener structure 120 thus forms a cavity 130 with the device carrier 110.
• the stiffener structure 120 can be a continuous ring-shaped structure or a discontinuous ring-shaped structure having a plurality of disconnecting sections disposed along the periphery 119b of the trace layout unit 119a.
• the shape of the stiffener structure 120 can be rectangle, square, circle, etc, or irregular.
• FIG. 2a shows the stiffener structure with locking features
• FIG. 2b shows different shapes of the locking elements of FIG. 2a.
• at least one locking element 170 is embedded in the device carrier 110 and connected to the stiffener structure 120.
• the locking element 170 and the stiffener structure 120 can be formed into one piece in the manufacturing procedure.
• the locking element 170 is formed on the stiffener structure 120 by electroplating the chosen material of the locking element 170 on the stiffener structure 120.
• the locking element 170 is used for fixing the stiffener structure 120 on the device carrier 110 and enhancing the strength and durability of the structure.
• the locking element 170 extends through the insulating layer 114 and is exposed from the insulating layer 114. Moreover, as shown FIG. 2a (c), two locking elements 170 of different heights are embedded in the insulating layer 114.
• the shape of the locking element 170 can be cross, diamond, circle or square, as shown in FIG. 2b.
• the stiffener structure 120 (and the locking element 170) also connects to at least one package trace 118a.
• the locking element 170 is connected to the package trace 118a by the stiffener structure 120, and extends to the bottom surface of the insulating layer 114 to connect to other element such as a peripheral device.
• the stiffener structure 120 directly connects to the package trace 118a, and is connected to other element by the stud 118b disposed under the package trace 118a.
• the device carrier 110 of the semiconductor package receives one or more semiconductor chips for forming a semiconductor assembly.
• the semiconductor assembly 200 includes a chip 205 such as an integrated circuit chip.
• the chip 205 is disposed in the cavity 130 of the device carrier 110.
• the semiconductor assembly 200 further includes an interconnecting structure disposed in the cavity 130 for electrically connecting the chip 205 to the device carrier 110.
• an interconnecting structure disposed in the cavity 130 for electrically connecting the chip 205 to the device carrier 110.
• the transmission of signal between the studs 118b, which are electrically connected to other elements, and the chip 205 is achieved by the interconnecting structure 240.
• the interconnecting structure 240 includes one or more electrical paths. Each of the electrical paths has at least one interconnecting layer. Preferably, the electrical path has two interconnecting layers, one interconnecting layer is preferably formed from a conductive material such as copper, and the other interconnecting layer is preferably formed from a solder material such as lead or tin. Examples of the electrical paths are pillar bumps and solder bumps.
• the semiconductor assembly 200 is preferably combined with a filling structure for forming a semiconductor package 300.
• the filling structure used for filling the space within the semiconductor package 300 has at least a first filling material 250a and a second filling material 250b.
• the first filling material 250a fills the gap between the device carrier 110 and the chip 205.
• the second filling material 250b which is positioned above the first filling material 250a, fills the gap between chip 205 and the stiffener structure 120.
• the materials of the first filling material 250a and the second filling material 250b can be the same or different, and are preferably insulating materials or dielectric materials.
• the cavity 130 defined by the stiffener structure 120 facilitates the disposition of the filling structure, and easily controls the range and volume of the filling structure within the semiconductor package 300. Besides, the stiffener structure 120 and the filling structure thicken the structure of the device carrier 110, which reduces the possibility of flexure and crack on the device carrier 110 and provides additional support for the semiconductor package 300.
• the semiconductor package 300 further includes a sealing cap 310 disposed above the chip 205 and assembled to the stiffener structure 120 for encapsulating and protecting the chip 205 and the filling structure.
• the sealing cap 310 and the stiffener structure 120 are combined by an adhesive layer or a solder layer 315.
• the sealing cap 310 is preferably formed from metals and is used for applications such as electrostatic discharge protection, heat dissipation, and moisture proof.
• a heat conductive layer 320 is preferably disposed between the sealing cap 310 and the chip 205 to conduct the heat generated from the chip 205 to the external space.
• FIG. 5a shows a carrier array of the semiconductor package
• FIG. 5b and FIG. 5c show different cross-sectional views of the semiconductor package of FIG. 5a along the line C-C.
• the carrier array 500 includes a plurality of carrier units. Take the carrier units 500a and 500b for example.
• the device carrier 510 of the carrier units 500a and 500b has a plurality of electro-isolated package traces 518a, studs 518b and pads 518c, which form a plurality of trace layout units.
• the stiffener structures 520 are disposed along the peripheries 519b of the trace layout units and connected to the locking elements 570 for increasing the attachment to the device carrier 510.
• a plurality of guiding elements 540 are disposed on the device carrier 510 in accordance with the spaced areas 502 between the carrier units 500a and 500b.
• each stiffener structure 520 is connected to two locking elements 570a and 570b.
• the locking element 570b extends to the bottom surface of the device carrier 510 for assisting in dividing the device carrier 510 into the carrier units. Exemplary shapes of the locking elements 570b and the guiding elements 540 are disclosed in FIG. 6.
• the shape of the locking element 570b and the guiding elements 540 can be regular or irregular, such as sawteeth (a), disconnecting sections (b)-(d), or the guiding elements 540 can be disposed in parallel (e).
• the design of the locking element 570b and guiding elements 540 are used for increasing the interface adhesion of different materials within the device carrier 510 for process handling.
• FIG. 7 shows different structures of the guiding elements 540.
• the guiding elements 540 each have a single-layer structure (a), which is embedded in the device carrier 510 and its upper surface is exposed from the device carrier 510.
• the guiding elements can also have a multi-layer structure (b), which is at least consisted of a first guiding layer 540a and a second guiding layer 540b.
• the second guiding layer 540b is a discontinuous layer that connects to the first guiding layer 540a and extends to the bottom surface of the device carrier 510.
• the width of the first guiding layer 540a is larger than the width of the second guiding layer 540b.
• the guiding elements 540 are embedded in the device carrier 510 in the disclosure however the invention is not limited thereto.
• the guiding elements 540 can also be protruded from the upper surface of the device carrier 510 and partially embedded in the device carrier 510.
• a manufacturing method of semiconductor package includes the steps of: providing a base layer; forming a patterned trace layout on the base layer; forming an insulating layer on the base layer and covering the patterned trace layout for forming a semiconductor substrate; forming a plurality of stiffener structures on the insulating layer to form a plurality of cavities with the insulating layer; and, breaking the semiconductor substrate along a plurality of spaced areas between the stiffener structures for forming a plurality of device carriers.
• the carrier array 500 of FIG. 5a and FIG. 5b is taken for elaborating the detailed process of the manufacturing method but does not limit the scope of the invention.
• FIGS. 8a to 8h show the processes of the manufacturing, method of semiconductor package.
• a base layer 700 is provided.
• the base layer 700 is preferably a conductive structure whose material is metal such as copper or steel.
• a patterned trace layout is formed on the base layer 700.
• a first conductive layer 710 is formed on the base layer 700 by, for example, electroplating.
• the first conductive layer 710 includes the package traces 518a, the pads 518c, the locking elements 570 and the first guiding layers 540a of the guiding elements 540 (shown in FIG. 5b).
• the locking elements 570 are formed in accordance with the predetermined locations of the stiffener structures 520 (shown in FlG. 5b).
• the first guiding layers 540a are formed in accordance with the predetermined locations of the spaced areas 502 (shown in FIG. 5b) between the stiffener structures 520.
• a second conductive layer 720 is formed on the base layer 700 by electroplating, for example.
• the second conductive layer 720 includes the studs 518b and the second guiding layers 540b of the guiding elements 540 (shown in FIG. 5b).
• the manufacturing process of the patterned trace layout is initially completed.
• an insulating layer is formed on the patterned trace layout for forming a semiconductor substrate of the carrier array.
• the insulating layer is formed using a molding material.
• the molding material has a brittle nature.
• the molding material 725 is first disposed on the patterned trace layout (the first conductive layer 710 and the second conductive layer 720) and covers the patterned trace layout. After that, the molding material 725 is thinned by grinding to form an insulating layer 727, which is used as the semiconductor substrate of the device carrier 510 of FIG. 5b, that exposes the bottom surface of the second conductive layer 720, as shown in FIG. 8e.
• a plurality of stiffener structures are formed on the insulating layer 727.
• the base layer 700 is patterned for forming the stiffener structures 520, which are accordingly combined with the locking elements 570 and form a plurality of cavities 730 with the insulating layer 727.
• the base layer 700 is preferably patterned by the use of etchant and mask, which means, the base layer 700 is partially removed to form the stiffener structures 520. Alternatively, the base layer 700 is totally removed, and the stiffener structures 520 are additionally formed on the insulating layer 727.
• the upper surface of the first conductive layer 710 is exposed out of the insulating layer 727.
• stiffener structures 520 each have a multi-layer structure
• one layer of the stiffener structures 520 can be formed by patterning the base layer 700, and another layer of the stiffener structures 520 can be additionally formed in accordance with the previous layer.
• the manufacture of the carrier array 500 is hence finished. Before the step of separating the carrier array 500 to form a plurality of carrier units (such as the carrier units 500a and 500b of FIG. 5b), the manufacture of semiconductor packages can be proceeded in advance. As shown in FIG. 8f, a plurality of chips 805 are disposed in the cavities 730 and electrically connected to the pads 518c and/or the package traces 518a of the first conductive layer 710 of the patterned trace layout.
• a filling structure is then disposed in the cavities 730.
• a first filling material 815a is provided to fill the gaps between the semiconductor substrate and the chips 805
• a second filling material 815b is provided to fill the gaps between the chips 805 and the stiffener structures 520.
• a plurality of sealing caps can be provided to be disposed above the cavities 730 and assembled to the stiffener structures 520, so as to encapsulate and protect the chips 805 as well as the filling structures.
• the carrier array 500 of FIG. 5a is separated along the spaced areas 502 between the stiffener structures 520. Due to the fragile interface of the insulating layer 727 between the guiding elements 540 and the stiffener structures 520, the semiconductor substrate is easily separated along the breaking lines BL1 and BL2 by proper manufacturing process, thus producing the carrier units 500a and 500b as shown in FIG. 8h.
• FIGS. 9 and 10 show different manufacturing processes for dividing the carrier array.
• the carrier unit 500b and its stiffener structure 520, and the guiding element 540 are first fixed and positioned. Then, applying force to the carrier unit 500b and its stiffener structure 520 for generating a bending mechanism on the semiconductor substrate, so as to separate the carrier unit 500b.
• a shear mechanism is generated on the semiconductor substrate, such that the carrier unit 500 is separated.
• the stiffener structure is disposed on the device carrier for predetermining the location of the filling structure and controlling the volume of the filling structure in the subsequent process.
• the stiffener structure and the filling structure located between the chip and the device carrier provide additional support for the chip and the semiconductor package, enhancing the structural strength of the semiconductor package and impeding the flexure to the package, which largely increases the yield of the manufacturing process.
• the semiconductor substrate is separated via the bending or shear mechanism along predetermined spaced areas in which the guiding elements are located. Therefore, individual device carrier is produced without the use of blade, which is quite different from the conventional manufacturing method accompanied by the problem of worn blade.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Chemical & Material Sciences (AREA)
• Dispersion Chemistry (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Wire Bonding (AREA)

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• 2009
  • 2009-11-20 CN CN201410528376.XA patent/CN104392968B/zh active Active
  • 2009-11-20 CN CN200980144822.4A patent/CN102171815B/zh active Active
  • 2009-11-20 WO PCT/SG2009/000439 patent/WO2010059133A1/en active Application Filing
  • 2009-11-20 TW TW102142444A patent/TWI581378B/zh active
  • 2009-11-20 US US13/128,252 patent/US9847268B2/en active Active
  • 2009-11-20 TW TW098139520A patent/TWI421982B/zh active
• 2017
  • 2017-12-18 US US15/844,837 patent/US20180108584A1/en not_active Abandoned

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