US20180108584A1

US20180108584A1 - Semiconductor Substrate

Info

Publication number: US20180108584A1
Application number: US15/844,837
Authority: US
Inventors: Shoa-Siong Lim; Kian Hock Lim
Original assignee: Advanpack Solutions Pte Ltd
Current assignee: Advanpack Solutions Pte Ltd
Priority date: 2008-11-21
Filing date: 2017-12-18
Publication date: 2018-04-19
Also published as: US20110210439A1; TWI421982B; CN104392968B; TW201419461A; US9847268B2; CN102171815B; TWI581378B; TW201021163A; CN104392968A; CN102171815A; WO2010059133A1

Abstract

A semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units. The stiffener structures are disposed on the device carrier along the periphery of the trace layout units. The spaced areas are disposed between the stiffener structures.

Description

This application is a continuation application of U.S. patent application Ser. No. 13/128,252 filed May 9, 2011, which is a national stage of PCT application PCT/SG2009/000439, filed Nov. 20, 2009, claiming priority of U.S. Provisional Patent Application 61/116,703, filed Nov. 21, 2008, the subject matters of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates in general to a substrate, and more particularly to a semiconductor substrate.

Description of the Related Art

In the past, the semiconductor industry has seen integrated circuits (IC) being produced with fewer IC pads and interconnecting structures. This enables the spacing between the leads and interconnecting structures in the IC. However, recently, the IC packages have become more compact and require increased functions to be incorporated into a semiconductor chip. Additionally, the chip has to be dimensionally small to enable the IC packages to be compact. It is therefore desirable for the interconnecting structures to be spaced apart while increasing the number of interconnection due to the increased logic function on the chip. The increased logic function on the chip means an increase in circuit density of the chip. As circuit density increases on the small-sized chip, it becomes important to provide a thin, reliable and robust packaging for forming the miniature packages. Also, the mechanical, electrical and heat dissipation properties of such miniature packages need to be carefully considered without affecting the overall performance of the IC.
Furthermore, a general concern for IC packaging of a semiconductor device is on the integrity of the IC package structure. The IC package structure typically comprises a substrate on which the semiconductor device is disposed. Typically, the substrate may be damaged due to, for example, cracks in the substrate when the substrate is subjected to stress. The substrate may be stressed during the coupling of the semiconductor device to the substrate or the handling of the IC package.
Additionally, after coupling the semiconductor device to the substrate, the structure of the IC package may also be weakened due to additional stress on the substrate and hence renders the IC package more susceptible to damages. Damages in the substrate adversely affect the integrity of the IC package structure, leading to insufficient support for the semiconductor device. It is therefore desirable to provide a solution to address at least one of the foregoing problems of the conventional operations.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a semiconductor substrate. The semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units. The stiffener structures are disposed on the device carrier along the periphery of the trace layout units. The spaced areas are disposed between the stiffener structures.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a shows a semiconductor package according to a preferred embodiment of the invention;

FIG. 1b shows a cross-sectional view of the semiconductor package of FIG. 1a along the line A-A′;

FIG. 2a shows the stiffener structure with locking features;

FIG. 2b shows different shapes of the locking elements of FIG. 2 a;

FIG. 3a shows the stiffener structure connecting to at least one package trace;

FIG. 3b shows cross-sectional views of the semiconductor package of FIG. 3a along the line B-B′;

FIG. 4a shows a semiconductor assembly and a semiconductor package;

FIG. 4b shows the semiconductor assembly and the semiconductor package of FIG. 4a each further having a sealing cap;

FIG. 5a shows a carrier array of the semiconductor package;

FIG. 5b and FIG. 5c show different cross-sectional views of the semiconductor package of FIG. 5a along the line C-C′;

FIG. 6 shows the exemplary shapes of the locking elements and the guiding elements;

FIG. 7 shows different structures of the guiding elements;

FIGS. 8a to 8h show the processes of the manufacturing method of semiconductor package; and

FIGS. 9 and 10 show different manufacturing processes for dividing the carrier array.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1a and FIG. 1 b, FIG. 1a shows a semiconductor package according to a preferred embodiment of the invention, FIG. 1b shows a cross-sectional view of the semiconductor package of FIG. 1a along the line A-A′. The semiconductor package 100 includes a device carrier 110 and a stiffener structure 120. The device carrier 110 includes at least one insulating layer 114 and at least conductive layer. The device carrier 110 is, for example, a molding substrate and has a first surface 110 a and a second surface 110 b. The material of the insulating layer 114 is a dielectric material or a molding compound.
The conductive layer has at least one trace layout unit 119 a having a periphery 119 b. The conductive layer includes a plurality of electro-isolated package traces 118 a and a plurality of studs 118 b. The location and number of the studs 118 b are preferably in accordance with that of the package traces 118 a. Preferably, the package traces 118 a are embedded in the first surface 110 a, and the studs 118 b are embedded in the second surface 110 b and electrically connected to the package traces 118 a. At least one of the studs 118 b is used for electrically connecting to other element or any peripheral device. The peripheral device is a printed circuit board (PCB), for example, which has a plurality of contact pads in the form of an array. The semiconductor package 100 can be assembled to the PCB by welding the studs 118 b to connect to the contact pads.
As shown in FIG. 1 a, the stiffener structure 120 is disposed on the first surface 110 a and preferably formed during the manufacturing procedure of the device carrier as an integral part of the device carrier. Preferably, the stiffener structure 120 is formed from copper or steel. Alternatively, the stiffener structure 120 can have one or more than two laminated layers of the same or different materials. For example, the stiffener structure 120 has a first layer whose material is polymer, and has a second layer whose material is metal. As shown in FIG. 1 a, the stiffener structure 120 is spaced away from the periphery 119 b of the trace layout unit 119 a and disposed along the periphery 119 b for forming a ring-shaped structure. The stiffener structure 120 thus forms a cavity 130 with the device carrier 110. The stiffener structure 120 can be a continuous ring-shaped structure or a discontinuous ring-shaped structure having a plurality of disconnecting sections disposed along the periphery 119 b of the trace layout unit 119 a. The shape of the stiffener structure 120 can be rectangle, square, circle, etc, or irregular.
Referring to FIG. 2a and FIG. 2b , FIG. 2a shows the stiffener structure with locking features, FIG. 2b shows different shapes of the locking elements of FIG. 2a . As shown in FIG. 2a (a), at least one locking element 170 is embedded in the device carrier 110 and connected to the stiffener structure 120. The locking element 170 and the stiffener structure 120 can be formed into one piece in the manufacturing procedure. For example, the locking element 170 is formed on the stiffener structure 120 by electroplating the chosen material of the locking element 170 on the stiffener structure 120. The locking element 170 is used for fixing the stiffener structure 120 on the device carrier 110 and enhancing the strength and durability of the structure. As shown in FIG. 2a (b), the locking element 170 extends through the insulating layer 114 and is exposed from the insulating layer 114. Moreover, as shown FIG. 2a (c), two locking elements 170 of different heights are embedded in the insulating layer 114. The shape of the locking element 170 can be cross, diamond, circle or square, as shown in FIG. 2 b.
As shown in FIG. 3a , the stiffener structure 120 (and the locking element 170) also connects to at least one package trace 118 a. Preferably, as shown in FIG. 3b (a), the locking element 170 is connected to the package trace 118 a by the stiffener structure 120, and extends to the bottom surface of the insulating layer 114 to connect to other element such as a peripheral device. A shown in FIG. 3b (b), the stiffener structure 120 directly connects to the package trace 118 a, and is connected to other element by the stud 118 b disposed under the package trace 118 a.
The device carrier 110 of the semiconductor package receives one or more semiconductor chips for forming a semiconductor assembly. As shown in FIG. 4a (a), the semiconductor assembly 200 includes a chip 205 such as an integrated circuit chip. The chip 205 is disposed in the cavity 130 of the device carrier 110.
The semiconductor assembly 200 further includes an interconnecting structure disposed in the cavity 130 for electrically connecting the chip 205 to the device carrier 110. Preferably, the transmission of signal between the studs 118 b, which are electrically connected to other elements, and the chip 205 is achieved by the interconnecting structure 240.
The interconnecting structure 240 includes one or more electrical paths. Each of the electrical paths has at least one interconnecting layer. Preferably, the electrical path has two interconnecting layers, one interconnecting layer is preferably formed from a conductive material such as copper, and the other interconnecting layer is preferably formed from a solder material such as lead or tin. Examples of the electrical paths are pillar bumps and solder bumps.
Furthermore, as shown in FIG. 4a (b), the semiconductor assembly 200 is preferably combined with a filling structure for forming a semiconductor package 300. The filling structure used for filling the space within the semiconductor package 300 has at least a first filling material 250 a and a second filling material 250 b. The first filling material 250 a fills the gap between the device carrier 110 and the chip 205. The second filling material 250 b, which is positioned above the first filling material 250 a, fills the gap between chip 205 and the stiffener structure 120. The materials of the first filling material 250 a and the second filling material 250 b can be the same or different, and are preferably insulating materials or dielectric materials.
The cavity 130 defined by the stiffener structure 120 facilitates the disposition of the filling structure, and easily controls the range and volume of the filling structure within the semiconductor package 300. Besides, the stiffener structure 120 and the filling structure thicken the structure of the device carrier 110, which reduces the possibility of flexure and crack on the device carrier 110 and provides additional support for the semiconductor package 300.
The semiconductor package 300 further includes a sealing cap 310 disposed above the chip 205 and assembled to the stiffener structure 120 for encapsulating and protecting the chip 205 and the filling structure. The sealing cap 310 and the stiffener structure 120 are combined by an adhesive layer or a solder layer 315. The sealing cap 310 is preferably formed from metals and is used for applications such as electrostatic discharge protection, heat dissipation, and moisture proof. In the case of heat dissipation application, a heat conductive layer 320 is preferably disposed between the sealing cap 310 and the chip 205 to conduct the heat generated from the chip 205 to the external space.
Referring to FIG. 5a , FIG. 5b and FIG. 5c , FIG. 5a shows a carrier array of the semiconductor package, FIG. 5b and FIG. 5c show different cross-sectional views of the semiconductor package of FIG. 5a along the line C-C′. The carrier array 500 includes a plurality of carrier units. Take the carrier units 500 a and 500 b for example. The device carrier 510 of the carrier units 500 a and 500 b has a plurality of electro-isolated package traces 518 a, studs 518 b and pads 518 c, which form a plurality of trace layout units. The stiffener structures 520 are disposed along the peripheries 519 b of the trace layout units and connected to the locking elements 570 for increasing the attachment to the device carrier 510.
Preferably, as shown in FIG. 5b , a plurality of guiding elements 540 are disposed on the device carrier 510 in accordance with the spaced areas 502 between the carrier units 500 a and 500 b. Additionally, as shown in FIG. 5c , each stiffener structure 520 is connected to two locking elements 570 a and 570 b. The locking element 570 b extends to the bottom surface of the device carrier 510 for assisting in dividing the device carrier 510 into the carrier units. Exemplary shapes of the locking elements 570 b and the guiding elements 540 are disclosed in FIG. 6. The shape of the locking element 570 b and the guiding elements 540 can be regular or irregular, such as sawteeth (a), disconnecting sections (b)-(d), or the guiding elements 540 can be disposed in parallel (e). The design of the locking element 570 b and guiding elements 540 are used for increasing the interface adhesion of different materials within the device carrier 510 for process handling.
FIG. 7 shows different structures of the guiding elements 540. The guiding elements 540 each have a single-layer structure (a), which is embedded in the device carrier 510 and its upper surface is exposed from the device carrier 510. The guiding elements can also have a multi-layer structure (b), which is at least consisted of a first guiding layer 540 a and a second guiding layer 540 b. The second guiding layer 540 b is a discontinuous layer that connects to the first guiding layer 540 a and extends to the bottom surface of the device carrier 510. Preferably, the width of the first guiding layer 540 a is larger than the width of the second guiding layer 540 b.
The guiding elements 540 are embedded in the device carrier 510 in the disclosure however the invention is not limited thereto. The guiding elements 540 can also be protruded from the upper surface of the device carrier 510 and partially embedded in the device carrier 510.
A manufacturing method of semiconductor package is disclosed. The manufacturing method includes the steps of: providing a base layer; forming a patterned trace layout on the base layer; forming an insulating layer on the base layer and covering the patterned trace layout for forming a semiconductor substrate; forming a plurality of stiffener structures on the insulating layer to form a plurality of cavities with the insulating layer; and, breaking the semiconductor substrate along a plurality of spaced areas between the stiffener structures for forming a plurality of device carriers. The carrier array 500 of FIG. 5a and FIG. 5b is taken for elaborating the detailed process of the manufacturing method but does not limit the scope of the invention.
FIGS. 8a to 8h show the processes of the manufacturing method of semiconductor package. As shown in FIG. 8a , a base layer 700 is provided. The base layer 700 is preferably a conductive structure whose material is metal such as copper or steel.
Next, a patterned trace layout is formed on the base layer 700. As shown in FIG. 8b , a first conductive layer 710 is formed on the base layer 700 by, for example, electroplating. The first conductive layer 710 includes the package traces 518 a, the pads 518 c, the locking elements 570 and the first guiding layers 540 a of the guiding elements 540 (shown in FIG. 5b ). The locking elements 570 are formed in accordance with the predetermined locations of the stiffener structures 520 (shown in FIG. 5b ). The first guiding layers 540 a are formed in accordance with the predetermined locations of the spaced areas 502 (shown in FIG. 5b ) between the stiffener structures 520.
Then, as shown in FIG. 8c , a second conductive layer 720 is formed on the base layer 700 by electroplating, for example. The second conductive layer 720 includes the studs 518 b and the second guiding layers 540 b of the guiding elements 540 (shown in FIG. 5b ). Herein the manufacturing process of the patterned trace layout is initially completed.
Next, an insulating layer is formed on the patterned trace layout for forming a semiconductor substrate of the carrier array. Preferably the insulating layer is formed using a molding material. Preferably, the molding material has a brittle nature. As shown in FIG. 8d , the molding material 725 is first disposed on the patterned trace layout (the first conductive layer 710 and the second conductive layer 720) and covers the patterned trace layout. After that, the molding material 725 is thinned by grinding to form an insulating layer 727, which is used as the semiconductor substrate of the device carrier 510 of FIG. 5b , that exposes the bottom surface of the second conductive layer 720, as shown in FIG. 8 e.
Then, a plurality of stiffener structures are formed on the insulating layer 727. As shown in FIG. 8e , the base layer 700 is patterned for forming the stiffener structures 520, which are accordingly combined with the locking elements 570 and form a plurality of cavities 730 with the insulating layer 727. The base layer 700 is preferably patterned by the use of etchant and mask, which means, the base layer 700 is partially removed to form the stiffener structures 520. Alternatively, the base layer 700 is totally removed, and the stiffener structures 520 are additionally formed on the insulating layer 727. Herein the upper surface of the first conductive layer 710 is exposed out of the insulating layer 727.
If the stiffener structures 520 each have a multi-layer structure, one layer of the stiffener structures 520 can be formed by patterning the base layer 700, and another layer of the stiffener structures 520 can be additionally formed in accordance with the previous layer.
The manufacture of the carrier array 500 is hence finished. Before the step of separating the carrier array 500 to form a plurality of carrier units (such as the carrier units 500 a and 500 b of FIG. 5b ), the manufacture of semiconductor packages can be proceeded in advance. As shown in FIG. 8f , a plurality of chips 805 are disposed in the cavities 730 and electrically connected to the pads 518 c and/or the package traces 518 a of the first conductive layer 710 of the patterned trace layout.
A filling structure is then disposed in the cavities 730. In this step, as shown in FIG. 8g , a first filling material 815 a is provided to fill the gaps between the semiconductor substrate and the chips 805, and a second filling material 815 b is provided to fill the gaps between the chips 805 and the stiffener structures 520. Afterwards, a plurality of sealing caps (such as the sealing cap 310 of FIG. 3b ) can be provided to be disposed above the cavities 730 and assembled to the stiffener structures 520, so as to encapsulate and protect the chips 805 as well as the filling structures.
When forming individual carrier unit, the carrier array 500 of FIG. 5a is separated along the spaced areas 502 between the stiffener structures 520. Due to the fragile interface of the insulating layer 727 between the guiding elements 540 and the stiffener structures 520, the semiconductor substrate is easily separated along the breaking lines BL1 and BL2 by proper manufacturing process, thus producing the carrier units 500 a and 500 b as shown in FIG. 8 h.
FIGS. 9 and 10 show different manufacturing processes for dividing the carrier array. As shown in FIG. 9, the carrier unit 500 b and its stiffener structure 520, and the guiding element 540 are first fixed and positioned. Then, applying force to the carrier unit 500 b and its stiffener structure 520 for generating a bending mechanism on the semiconductor substrate, so as to separate the carrier unit 500 b. Alternatively, as shown in FIG. 10, a shear mechanism is generated on the semiconductor substrate, such that the carrier unit 500 b is separated. By repeating the above process, all the carrier units of the carrier array 500 can be divided. And the manufacture of a plurality of individual semiconductor packages is completed.
According to the semiconductor package and the manufacturing method thereof disclosed in the embodiment of the invention, the stiffener structure is disposed on the device carrier for predetermining the location of the filling structure and controlling the volume of the filling structure in the subsequent process. Besides, the stiffener structure and the filling structure located between the chip and the device carrier provide additional support for the chip and the semiconductor package, enhancing the structural strength of the semiconductor package and impeding the flexure to the package, which largely increases the yield of the manufacturing process. Furthermore, when manufacturing the semiconductor package, the semiconductor substrate is separated via the bending or shear mechanism along predetermined spaced areas in which the guiding elements are located. Therefore, individual device carrier is produced without the use of blade, which is quite different from the conventional manufacturing method accompanied by the problem of worn blade.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

What is claimed is:

1. A semiconductor substrate, comprising:

a device carrier comprising a plurality of trace layout units and a periphery around the trace layout units;

a plurality of stiffener structures disposed on the device carrier along the periphery of the trace layout units; and

a plurality of spaced areas disposed between the stiffener structures.

2. The semiconductor substrate according to claim 1, wherein the device carrier having a first surface and a second surface opposite to the first surface, the plurality of stiffener structures disposed on the first surface of the device carrier.

3. The semiconductor substrate according to claim 2, wherein the plurality of stiffener structures extend on the first surface in a direction away from the second surface to form a cavity with the device carrier.

4. The semiconductor substrate according to claim 2, further comprising:

a plurality of locking elements disposed below the plurality of stiffener structures and embedded within the device carrier, wherein the plurality of locking elements adjoins the plurality of stiffener structures and extends away from the stiffener structure towards the second surface of the device carrier.

5. The semiconductor substrate according to claim 4, wherein the plurality of locking elements extend from the first surface of the device carrier to the second surface of the device carrier, and exposed on the second surface of the device carrier.

6. The semiconductor substrate according to claim 2, wherein the device carrier comprises at least one conductive layer, wherein the at least one conductive layer connects the first surface of the device carrier to the second surface of the device carrier.

7. The semiconductor substrate according to claim 6, wherein the device carrier comprises a plurality of conductive layers disposed on the different locations of the device carrier.

8. The semiconductor substrate according to claim 7, wherein the plurality of conductive layers comprises:

a first conductive layer comprising a plurality of traces; and

a second conductive layer comprising a plurality of studs, wherein the plurality of studs are disposed correspondingly on the plurality of traces;

wherein the plurality of traces and studs are embedded in the insulating layer between the first and second surface of the device carrier, the plurality of traces and studs form the plurality of trace layout units.

9. The semiconductor substrate according to claim 7, wherein at least one of plurality of conductive layers is electrically connected to the stiffener structure.

10. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises at least one metallic material.

11. The semiconductor substrate according to claim 10, wherein the stiffener structure further comprises at least one polymeric material disposed between the first surface of the device carrier and the stiffener structure.

12. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a metallic material and a polymeric material.

13. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a metallic material and a solderable material.

14. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a continuous ring-shaped structure.

15. The semiconductor substrate according to claim 1, wherein the stiffener structure comprises a discontinuous ring-shaped structure.

16. The semiconductor substrate according to claim 1, wherein the stiffener structure is disposed on the edge of the semiconductor substrate.

17. The semiconductor substrate according to claim 1, further comprising:

a plurality of guiding elements disposed on the device carrier in accordance with the spaced areas.

18. The semiconductor substrate according to claim 17, wherein the guiding elements each have at least one portion embedded in the device carrier.

19. The semiconductor substrate according to claim 17, wherein the guiding elements each comprise a first guiding layer and a second guiding layer.

20. The semiconductor substrate according to claim 19, wherein the second guiding layer is a discontinuous guiding layer.

21. The semiconductor substrate according to claim 19, wherein the width of the first guiding layer is larger than the width of the second guiding layer.

22. The semiconductor substrate according to claim 17, wherein the shape of each guiding element is irregular.

23. The semiconductor substrate according to claim 17, wherein the plurality of trace layout units is in the form of array, the plurality of spaced areas forms at least one breaking line between the plurality of trace layout units.

24. The semiconductor substrate according to claim 23, wherein the breaking line is disposed between the stiffener structure and the guiding element.

25. The semiconductor substrate according to claim 24, wherein the semiconductor substrate is separated along the breaking line.

26. The semiconductor substrate according to claim 17, wherein the device carrier comprises:

at least one insulating layer formed using a molding material.

27. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is separated via the bending mechanism along the spaced area.

28. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is separated via the shear mechanism along the spaced area.