WO2010058581A1 - Registre à décalage - Google Patents

Registre à décalage Download PDF

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Publication number
WO2010058581A1
WO2010058581A1 PCT/JP2009/006227 JP2009006227W WO2010058581A1 WO 2010058581 A1 WO2010058581 A1 WO 2010058581A1 JP 2009006227 W JP2009006227 W JP 2009006227W WO 2010058581 A1 WO2010058581 A1 WO 2010058581A1
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WIPO (PCT)
Prior art keywords
region
electrode
tft
shift register
source
Prior art date
Application number
PCT/JP2009/006227
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English (en)
Japanese (ja)
Inventor
坂本真由子
守口正生
岩瀬泰章
齊藤裕一
吉田徳生
神崎庸輔
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シャープ株式会社
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Priority to US12/998,686 priority Critical patent/US20110274234A1/en
Publication of WO2010058581A1 publication Critical patent/WO2010058581A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention relates to a shift register, and more particularly to a shift register formed on an active matrix substrate of a liquid crystal display panel or an organic EL display panel.
  • TFT thin film transistor
  • amorphous silicon TFT amorphous silicon film as an active layer
  • polycrystalline silicon TFT amorphous silicon film as an active layer
  • a display panel is developed in which not only the pixel TFT but also part or all of the peripheral circuit TFT such as a driver is formed of a polycrystalline silicon TFT.
  • a driver formed on an insulating substrate (typically a glass substrate) constituting the display panel may be referred to as a monolithic driver.
  • the display panel refers to a portion having a display area in a liquid crystal display device or an organic EL display device, and does not include a backlight or a bezel of the liquid crystal display device.
  • polycrystalline silicon TFTs are mainly used for medium and small display devices, and amorphous silicon TFTs are used for large display devices.
  • microcrystalline silicon ( ⁇ c-Si) films which have higher performance and lower manufacturing costs than amorphous TFTs, are used as active layers.
  • TFTs have been proposed (Patent Document 1, Patent Document 2 and Non-Patent Document 1). Such a TFT is referred to as a “microcrystalline silicon TFT”.
  • the microcrystalline silicon film is a silicon film having a crystalline phase and an amorphous phase, and has a structure in which microcrystalline grains are dispersed in the amorphous phase.
  • the size of each microcrystal grain is smaller than the size of the crystal grain contained in the polycrystalline silicon film (several hundred nm or less), and may be a columnar crystal.
  • the microcrystalline silicon film can be formed using a plasma CVD method or the like, does not require heat treatment for crystallization, and can use a manufacturing facility for an amorphous silicon film as it is. Further, since the microcrystalline silicon film has higher carrier mobility than the amorphous silicon film, a TFT with higher performance than the amorphous silicon TFT can be obtained.
  • Patent Document 1 describes that by using a microcrystalline silicon film as an active layer of a TFT, an ON current 1.5 times that of an amorphous silicon TFT can be obtained.
  • Non-Patent Document 1 provides a TFT having an on / off current ratio of 10 6 , a mobility of about 1 cm 2 / Vs, and a threshold of about 5 V by using a semiconductor film made of microcrystalline silicon and amorphous silicon. It is described that
  • Patent Document 2 discloses an inverted stagger type TFT using microcrystalline silicon.
  • the microcrystalline silicon TFT has an advantage, it has not been put into practical use until now.
  • Patent Documents 3 and 4 disclose a liquid crystal display device and an organic EL display device using microcrystalline silicon TFTs having a multi-gate channel structure. In these display devices, by introducing a multi-channel structure to the pixel TFT, the off current of the pixel TFT is reduced and the voltage holding characteristics of the pixel are improved.
  • this problem is caused by a large leak current in the subthreshold region (gate voltage Vg ⁇ 0 V) of some TFTs constituting the shift register, which causes the gate electrode of the output transistor (pull-up transistor) of the shift register. It has been found that this is caused by the fact that the output voltage is reduced and the output waveform is distorted or the output transistor is not turned on.
  • the voltage Vds applied between the source and drain of some TFTs constituting the shift register is higher than the voltage Vds applied between the source and drain of the pixel TFT.
  • the voltage Vds reaches about 50 V at the maximum.
  • a large liquid crystal display panel may reach a maximum of around 70V.
  • the off-state current in the region where the gate voltage Vg (Vgs) is negative becomes a problem, whereas the gate voltage Vg (Vgs) of the TFT constituting the shift register is around 0V.
  • the present invention has been made in view of the above problems, and its main object is to improve the characteristics of the shift register constituting the monolithic gate driver.
  • Another object of the present invention is to provide a multi-channel TFT capable of reducing the off-current compared to the conventional multi-channel TFT described in Patent Document 3 or 4.
  • the shift register of the present invention is a shift register supported on an insulating substrate, and each of the shift registers has a plurality of stages for sequentially outputting output signals, and each of the plurality of stages outputs the output signal.
  • a multi-channel transistor having an active layer including a source region and a drain region.
  • the multi-channel transistor has the highest source-drain voltage among the plurality of second transistors.
  • the multi-channel transistor has a higher source-drain voltage than a non-multi-channel transistor.
  • each of the plurality of second transistors is the multi-channel transistor.
  • the active layer includes a semiconductor film having an amorphous phase.
  • the semiconductor film having an amorphous phase may be composed of only an amorphous semiconductor film, may be composed of a microcrystalline semiconductor film, or may be composed of a laminated film of an amorphous semiconductor film and a microcrystalline semiconductor film. .
  • the semiconductor film is a microcrystalline semiconductor film.
  • the semiconductor film may be a polycrystalline semiconductor film.
  • the active layer includes a polycrystalline semiconductor film.
  • the gate electrode of the multi-channel transistor has a portion overlapping the source region and the drain region, and an area of the portion where the gate electrode overlaps the drain region and the gate electrode is the source region.
  • the area of the portion overlapping with the gate electrode of the first transistor is different from the area of the portion overlapping with the gate electrode of the first transistor. Smaller than.
  • the source region and the drain region of the first transistor are different from each other, and the one not connected to the gate bus line is smaller than the one connected to the gate bus line.
  • the active layer of the multi-channel transistor further includes at least one intermediate region formed between the at least two channel regions, and the at least two channel regions include the source region and the source region.
  • a first channel region formed between the at least one intermediate region; a second channel region formed between the drain region and the at least one intermediate region;
  • a contact layer having a source contact region in contact with the source region, a drain contact region in contact with the drain region, and at least one intermediate contact region in contact with the at least one intermediate region, and a source electrode in contact with the source contact region In the drain contact region
  • at least one intermediate electrode in contact with the at least one intermediate contact region, and the gate electrode of the multi-channel transistor is connected to the at least two channel regions and the at least one intermediate region.
  • the entire portion of the at least one intermediate electrode that is located between the first channel region and the second channel region is opposed to the at least one intermediate region and the at least one intermediate region.
  • the gate electrode overlaps with the gate insulating film.
  • the gate electrode of the multi-channel transistor has a portion overlapping with the source region and the drain region, and is connected to the gate electrode of the first transistor in the source region and the drain region.
  • the area of the portion where the gate electrode overlaps with the gate electrode is smaller than the area of the portion where the at least one intermediate region and the gate electrode overlap.
  • the drain region is connected to the gate electrode of the first transistor, at least the area where the gate electrode overlaps the drain region is larger than the area where the at least one intermediate region overlaps the gate electrode. Is preferably small.
  • the area of the portion where the gate electrode overlaps the source region may be smaller than the area of the portion where the at least one intermediate region and the gate electrode overlap.
  • the at least one intermediate electrode of the multichannel transistor when viewed from the direction perpendicular to the substrate, has a recess, and the drain electrode protrudes into the recess of the at least one intermediate electrode. It has a part.
  • the source electrode of the multi-channel transistor when viewed from a direction perpendicular to the substrate, has a recess, and the at least one intermediate electrode has a portion protruding into the recess of the source electrode.
  • the at least one intermediate region of the multi-channel transistor has a first intermediate region and a second intermediate region, and the at least one intermediate contact region is a first intermediate contact region and a second intermediate contact region.
  • the at least one intermediate electrode includes a first intermediate electrode and a second intermediate electrode, the at least two channel regions further include a third channel region, and the first channel region is connected to the source electrode.
  • the second channel region is formed between the drain electrode and the second intermediate electrode, and the third channel region is formed between the first intermediate electrode and the first intermediate electrode. It is formed between the second intermediate electrode.
  • the at least one intermediate contact region of the multi-channel transistor also serves as the at least one intermediate electrode.
  • the multi-channel transistor includes at least one channel region supported by a substrate, a source region, a drain region, and at least one channel region formed between the at least two channel regions.
  • An active layer having an intermediate region; a source contact region in contact with the source region; a drain contact region in contact with the drain region; and a contact layer having at least one intermediate contact region in contact with the at least one intermediate region;
  • the channel region includes a first channel region formed between the source region and the at least one intermediate region, and a second channel region formed between the drain region and the at least one intermediate region. A portion of the at least one intermediate contact region existing between the first channel region and the second channel region is formed through the at least one intermediate region and the gate insulating film. It overlaps with.
  • the active layer is provided between the gate electrode and the substrate.
  • An active matrix substrate according to the present invention includes any one of the shift registers described above.
  • the display panel of the present invention includes any one of the shift registers described above.
  • characteristics of a shift register using a TFT having a semiconductor film containing an amorphous phase as an active layer can be improved.
  • a multi-channel TFT capable of reducing off-current compared to the conventional one is provided.
  • the characteristics of the shift register are further improved.
  • FIG. 1 is a schematic top view of the liquid crystal display panel 100 of embodiment by this invention
  • (b) is a top view which shows the typical structure of one pixel.
  • 2 is a block diagram illustrating a configuration of a shift register 110A included in a gate driver 110.
  • FIG. It is a schematic diagram which shows the conventional structure used for one stage of shift register 110A. It is a figure which shows the waveform of the input / output signal of each stage of the shift register 110A, and the voltage waveform of netA. It is a figure which shows the waveform of the output signal from the 4th stage of n-2 to n + 1 of the shift register 110A.
  • It is a circuit diagram of one stage of the shift register of the embodiment according to the present invention used in one stage of the shift register 110A.
  • FIG. 10 is a block diagram illustrating a configuration of another shift register 110B included in the gate driver 110. It is a schematic diagram which shows the conventional structure used for one stage of the shift register 110B. It is a figure which shows the waveform of the input / output signal of each stage of the shift register 110B, and the voltage waveform of netA. It is a figure which shows the waveform of the output signal from 5 steps
  • FIG. 5 is a circuit diagram of three successive stages of another shift register according to an embodiment of the present invention.
  • FIG. 15 is a circuit diagram illustrating an example of a shift register disclosed in Japanese Patent Laying-Open No. 2005-50502. It is a graph which shows the relationship between the source-drain current Ids with respect to the gate voltage Vg of the microcrystal silicon TFT of a single channel structure.
  • A is a schematic plan view of the TFT 10 of the embodiment according to the present invention
  • (b) is a schematic cross-sectional view taken along the line 21B-21B ′ in (a)
  • (c) is the TFT 10 FIG.
  • (A) is a schematic plan view of a TFT 90 having a conventional double gate structure
  • (b) is a schematic cross-sectional view taken along line 22B-22B 'in (a).
  • It is a graph which shows the example of the off-current characteristic of TFT10 and TFT90.
  • It is a graph which shows the relationship between the gate voltage Vg (V) and the current Ids (A) between source-drain about TFT which has a single channel structure, a dual channel structure, and a triple channel structure.
  • (A) to (f) are schematic cross-sectional views for explaining a method of manufacturing the active matrix substrate 101 including the TFT 10.
  • (A) is a typical top view of TFT10A of embodiment by this invention
  • (b) is a typical top view of TFT10B of embodiment by this invention. It is a graph which shows the relationship between gate voltage Vg (V) and source-drain current Ids (A) for TFT 10A and TFT 10B.
  • (A) is a schematic plan view of the TFT 10C of the embodiment according to the present invention
  • (b) is a schematic plan view of the TFT 10D of the embodiment according to the present invention
  • (c) is a schematic view of the embodiment according to the present invention. It is a typical top view of TFT10E.
  • FIG. 1 is a schematic plan view of a TFT 10F according to an embodiment of the present invention
  • FIG. 1 is a schematic plan view of a TFT 10G according to an embodiment of the present invention
  • FIG. 1 is a schematic view of the embodiment according to the present invention. It is a typical top view of TFT10H.
  • FIG. 1A is a schematic plan view of a liquid crystal display panel 100 according to an embodiment of the present invention, and FIG. 1B shows a schematic structure of one pixel.
  • FIG. 1A shows the structure of the active matrix substrate 101 of the liquid crystal display panel 100, and the liquid crystal layer and the counter substrate are omitted.
  • a liquid crystal display device can be obtained by providing the liquid crystal display panel 100 with a backlight, a power source, and the like.
  • a gate driver 110 and a source driver 120 are integrally formed on the active matrix substrate 101.
  • a plurality of pixels are formed in the display area of the liquid crystal display panel 100, and the area of the active matrix substrate 101 corresponding to the pixels is indicated by reference numeral 132.
  • the source driver 120 need not be formed integrally with the active matrix substrate 101.
  • a separately produced source driver IC or the like may be mounted by a known method.
  • the active matrix substrate 101 has a pixel electrode 101P corresponding to one pixel of the liquid crystal display panel 100.
  • the pixel electrode 101P is connected to the source bus line 101S via the pixel TFT 101T.
  • the gate electrode of the TFT 101T is connected to the gate bus line 101G.
  • the gate bus line 101G is connected to the output of the gate driver 110, and is scanned line-sequentially.
  • the output of the source driver 120 is connected to the source bus line 101S, and a display signal voltage (grayscale voltage) is supplied.
  • FIG. 2 is a block diagram illustrating the configuration of the shift register 110A included in the gate driver 110.
  • the shift register 110 ⁇ / b> A is supported on an insulating substrate such as a glass substrate that constitutes the active matrix substrate 101.
  • the TFT constituting the shift register 110A is preferably formed by the same process as the pixel TFT 101T formed in the display region of the active matrix substrate 101.
  • FIG. 2 schematically shows only four stages from n ⁇ 2 to n + 1 among a plurality of stages (stages) included in the shift register 110A.
  • the plurality of stages have substantially the same structure and are cascaded.
  • the output from each stage of the shift register 110A is given to each gate bus line 101G of the liquid crystal display panel 100.
  • Such a shift register 110A is described in, for example, Japanese Patent No. 2836642.
  • the disclosure of Japanese Patent No. 2836642 is incorporated herein by reference.
  • Each stage of the shift register 110A includes an input terminal S, an output terminal OUT, a terminal that receives any one of three clock signals CK1, CK2, and CK3 having different phases as a clock signal CK, and CK1, CK2. And a terminal for receiving any one of CK3 as a clock signal CKB. That is, for one stage of the shift register 110A, the clock signal input as the clock signal CK and the clock signal input as the clock signal CKB are different from each other.
  • a gate start pulse GSP is input to the input terminal S, one output terminal OUT is connected to the corresponding gate bus line 101G, and the other output terminal OUT is connected to the input terminal S of the next stage.
  • FIG. 3 is a schematic diagram showing a conventional configuration used in one stage of the shift register 110A
  • FIG. 4 shows a waveform of input / output signals and a voltage waveform of netA in each stage of the shift register 110A
  • FIG. 5 shows waveforms of output signals from four stages from n-2 to n + 1 of the shift register 110A. As shown in FIG. 5, the shift register 110A sequentially outputs an output signal Gout from each stage.
  • each stage of the shift register 110A includes a first transistor (TFTMA) that outputs an output signal Gout, and a source region or a drain region that is electrically connected to the gate electrode of the first transistor TFTMA. And a plurality of second transistors (TFTME and TFTMF).
  • TFTMA is a so-called pull-up transistor
  • TFTMB is a pull-down transistor
  • a wiring connected to the gate electrode of the TFTMA is called netA
  • a wiring connected to the gate electrode of the TFTMB is called netB.
  • the output signal Gout is output from each stage to the gate bus line 101G only during the pixel writing time.
  • the potential of the output signal Gout over most time in one frame period (a period until all the gate bus lines 101G are sequentially selected and the gate bus lines are selected again). Is configured to be fixed to VSS.
  • the netA is precharged by the S signal (previous stage output signal Gout (n-1)) and at the same time the netB is set low. This prevents the precharged netA potential from leaking through the TFTMF.
  • the clock signal CKB fixes the netA at the TFTMF and the potential of the Gout at the VSS MB at VSS.
  • the netB that is the wiring connected to the gate electrode of the pull-down transistor TFTMB is set to High. While the TFTMC is in the on state, the potential of the output signal Gout is kept low. TFTMD sets netB to Low when the S signal is input to the gate electrode. In order to precharge netA with the S signal, netB is set low to prevent leakage from the TFTMF.
  • VDD is a DC voltage and has the same potential as High of the clock signal CK.
  • FIG. 7A shows how the waveform of netA is rounded.
  • the comparative example in FIG. 7A is a case where the circuit of FIG. 3 is used.
  • FIG. 7B shows how the waveform of the output signal Gout is rounded.
  • the comparative example in FIG. 7B is a case where the circuit of FIG. 3 is used.
  • TFTME and TFTMF which are the second transistors, among the TFTs constituting the shift register.
  • FIG. 6 shows a circuit diagram of one stage of the shift register of the embodiment according to the present invention in which TFTME and TFTMF in FIG. 3 are replaced with TFTMEd and TFTMFd having a dual channel structure, respectively.
  • TFTMEd and TFTMFd have a dual channel structure
  • the leakage current in the TFT subthreshold region is smaller than that of conventional TFTME and TFTMF having a single channel structure, and the above problems can be solved. That is, as shown in FIGS. 7A and 7B, the waveform rounding of the netA and the output signal Gout is suppressed.
  • the effect of reducing the leakage current by introducing the multi-channel structure will be described in detail later with reference to FIGS.
  • the dual channel structure is introduced to all of the second transistors TFTME and TFTMF.
  • the present invention is not limited to this. If the dual channel structure is introduced to at least one TFT of the plurality of second transistors, The leakage current can be reduced for the transistor.
  • the dual channel structure is introduced to some of the TFTs of the plurality of second transistors, it is preferable to introduce the dual channel structure to the TFT MF having the highest source-drain voltage Vds.
  • the TFTMF has a gate electrode connected to the pull-down transistor (MB), and a source electrode or a drain electrode connected to the VSS or the gate electrode (netA) of the output transistor (MA).
  • the leakage current can be approximately 1 / n.
  • FIG. 8 schematically shows only five stages from n ⁇ 2 to n + 2 among a plurality of stages (stages) included in the shift register 110B.
  • the plurality of stages have substantially the same structure and are cascaded.
  • the output from each stage of the shift register 110B is given to each gate bus line 101G of the liquid crystal display panel 100.
  • Such a shift register 110B is described in, for example, JP-A-8-87893.
  • JP-A-8-87893 The disclosure content of JP-A-8-87893 is incorporated herein by reference.
  • FIG. 9 is a schematic diagram showing a conventional configuration used in one stage of the shift register 110B
  • FIG. 10 shows a waveform of input / output signals and a voltage waveform of netA in each stage of the shift register 110B
  • FIG. 11 shows waveforms of output signals from five stages from n-2 to n + 2 of the shift register 110B. As shown in FIG. 11, the shift register 110B sequentially outputs an output signal Gout from each stage.
  • each stage of the shift register 110B includes a first transistor (TFTMG) that outputs an output signal Gout, and a source region or a drain region that is electrically connected to the gate electrode of the first transistor TFTMG. And a plurality of second transistors (TFTMH, TFTMK, TFTMM, and TFTMN).
  • TFTMG is a so-called pull-up transistor, and the wiring connected to the gate electrode of TFTMG is referred to as netA.
  • the output signal Gout is output from each stage to the gate bus line 101G only during the pixel writing time. Focusing on one stage, the potential of Gout is VSS over most of the time in one frame period (a period until all the gate bus lines 101G are sequentially selected and the gate bus lines are selected again). It is comprised so that it may be fixed to.
  • NNetA is precharged by the S signal (previous output signal Gout (n ⁇ 1)). At this time, TFTMH, MK, and MN in which the source region or the drain region is connected to netA are off.
  • the clock signal CK and the clock signal CKB fix the netA at the TFT MK and the potential of the Gout at the VSS with the TFT ML.
  • the capacitor CAP1 keeps the potential of netA and assists the output.
  • the TFT MJ sets the potential of the output signal Gout to Low.
  • TFTML sets the potential of the output signal Gout to Low in response to the clock signal CKB.
  • the clear signal CLR is transmitted to all stages of the shift register once in one frame (vertical scanning period) and in the vertical blanking period (from the output of the last stage of the shift register to the output of the first stage). Supplied, netA of all stages is set to Low.
  • the clear signal CLR also serves as a reset signal for the final stage of the shift register.
  • a multi-channel structure is introduced into the second transistors TFTMH, TFTMK, TFTMM and TFTMN among the TFTs constituting the shift register.
  • FIG. 12 shows a circuit diagram of one stage of the shift register of the embodiment according to the present invention in which TFTMH, TFTMK, TFTMM and TFTMN of FIG. 9 are replaced with TFTMHd, TFTMKd, TFTMMd and TFTMNd having a dual channel structure, respectively. .
  • TFTMHd, TFTMKd, TFTMMd and TFTMNd have a dual channel structure, the leakage current in the TFT subthreshold region is smaller than that of the conventional TFTMH, TFTMK, TFTMM and TFTMN having a single channel structure, thus solving the above problem. Can do.
  • the dual channel structure is introduced to all of the second transistors TFTMH, TFTMK, TFTMM and TFTMN.
  • the present invention is not limited to this, and at least one TFT of the plurality of second transistors has a dual channel structure. If introduced, the leakage current of the transistor can be reduced.
  • a dual channel structure is introduced into some TFTs of the plurality of second transistors, it is preferable to introduce a dual channel structure into TFTMH, TFTML, and TFTMM having the highest source-drain voltage Vds.
  • the TFTMH has a gate electrode connected to the previous output (Gout (n ⁇ 1)), and a source electrode or drain electrode connected to the gate electrode (netA) or VSS of the output transistor TFTMG.
  • the TFT MK has a gate electrode connected to the wiring of the clock signal CK, and a source electrode or a drain electrode connected to the gate electrode (netA) or VSS of the output transistor TFTMG.
  • the gate electrode and the source electrode are connected to each other (diode connection), and the previous output (S signal) is supplied to the gate electrode.
  • the drain electrode of TFTMM is connected to the gate electrode (netA) of TFTMG.
  • the present invention can be applied to various shift registers. Examples of shift registers to which the present invention can be applied will be described with reference to FIGS.
  • FIG. 13A shows a one-stage circuit diagram of another shift register according to the embodiment of the present invention.
  • This shift register is configured by cascading a plurality of stages having substantially the same circuit as the circuit shown in FIG.
  • FIGS. 13B, 13C, and 13D show examples of timing charts of clock signals applicable to the shift register shown in FIG.
  • the present invention is applied to the shift registers described in Japanese Patent Application No. 2008-037625 and Japanese Patent Application No. 2008-068279. The entire disclosure content of these applications is incorporated herein by reference.
  • the TFT M1 is a first transistor, and the second transistors TFT M2d and TFT M3d have a dual channel structure. Therefore, this shift register can also solve the above problem.
  • the source electrode or the drain electrode of the TFT M1 is connected to a wiring of a clock signal (CKA) or a gate bus line that outputs an output signal Gout.
  • the source electrode or drain electrode of the TFT M2d is connected to the gate electrode or VSS of the TFT M1, and the gate electrode of the TFT M2d is connected to the output (Qn + 1) of the next stage.
  • the TFT M2d sets netA to Low at reset timing.
  • the drain electrode of the TFT M3d is connected to the gate electrode of the TFT M1.
  • the output (Qn-1) of the previous stage is input to the diode-connected source electrode and gate electrode of the TFT M3d.
  • the gate electrode of the TFT M4 is connected to the wiring of the clock signal (CKB), and the source electrode or the drain electrode is connected to the gate bus line (Gout) or VSS.
  • the TFT M4 plays a role of preventing potential fluctuation of the output signal Gout when not selected.
  • the capacitor C1 is a capacitor for assisting output, and prevents the potential of the netA from being lowered when selected.
  • FIG. 14A shows a one-stage circuit diagram of another shift register according to the embodiment of the present invention.
  • FIG. 14B shows an example of a timing chart of a clock signal applicable to the shift register shown in FIG.
  • TFT M5 is the first transistor
  • TFT M8d and TFT M9d which are the second transistors, have a dual channel structure. Therefore, this shift register can also solve the above problem.
  • the source electrode or the drain electrode of the TFT M5 is connected to the wiring of the clock signal (CKA) or the gate bus line (Gout).
  • the source electrode or drain electrode of the TFT M8d is connected to the gate electrode of the TFT M5 or VSS.
  • the gate electrode of the TFT M8d is connected to the output (Q n + 1 ) of the next stage, and sets netA to Low at the reset timing.
  • the drain electrode of the TFT M9d is connected to the gate electrode of the TFT M5, and the output signal (Q n-1 ) of the previous stage is input to the diode-connected source electrode and gate electrode of the TFT M9d.
  • the source electrodes or drain electrodes of the TFTs M6, M7 and M10 are connected to a gate bus line (Gout) or VSS, and the respective gate electrodes are connected to wirings of clock signals having different phases.
  • the capacitor C2 is a capacitor for assisting output, and prevents the potential of the netA from being lowered when selected.
  • the TFT can be prevented from being deteriorated, and at the same time, the Gout at the time of non-output can be kept low with the duty 3/4.
  • FIG. 15 shows a continuous three-stage circuit diagram of another shift register according to the embodiment of the present invention.
  • TFT M11 is the first transistor, and the second transistors TFT M12d and TFT M13d have a dual channel structure. Therefore, this shift register can also solve the above problem.
  • the TFT M11 has a source electrode or a drain electrode connected to a clock signal (CK1) wiring or a gate bus line (OUT1, 2 or 3).
  • the source electrode or drain electrode of the TFT M13d is connected to the gate electrode or VSS of the TFT M11.
  • the gate electrode of the TFT M13d is connected to the next stage output (the output of the next stage TFT M11).
  • the TFT M13d sets netA to Low at the reset timing.
  • the drain electrode of the TFT M12d is connected to the gate electrode of the TFT M11, and the output of the previous stage (the output signal of the TFT M11 of the previous stage) is input to the diode-connected source electrode and gate electrode of the TFT M12d.
  • FIG. 16-18 shows a circuit diagram of another shift register according to the embodiment of the present invention.
  • the present invention is applied to a shift register described in Japanese Patent Application No. 2008-037626. The entire disclosure of this application is incorporated herein by reference.
  • TFT M15 is the first transistor
  • the second transistors TFT M16d, TFT M19d, TFT M21d, and TFT M22d have a dual channel structure. Therefore, this shift register can also solve the above problem.
  • the TFT M15 has a source electrode or a drain electrode connected to a clock signal (CKA) wiring or a gate bus line (Gout (n) ).
  • the source electrode or drain electrode of the TFT M16d is connected to the gate electrode or VSS of the TFT M15.
  • the gate electrode of the TFT M16d is connected to the next stage output (Gout (n + 1) ).
  • the TFT M16d sets netA to Low at the reset timing.
  • the gate electrode of the TFT M21d is connected to the TFT M15, and the output (Gout (n-1) ) of the previous stage is input to the diode-connected source electrode and gate electrode of the TFT M21d.
  • the source electrode or drain electrode of the TFT M19d is connected to the gate electrode or gate bus line (Gout (n) ) of the TFT M15, and the gate electrode of the TFT M19d is connected to the wiring of the clock signal (CKA).
  • the source electrode or drain electrode of the TFT M22d is connected to the gate electrode or VSS of the TFT M15, and the clear signal CLR is input to the gate electrode of the TFT M22d.
  • the clear signal CLR is transmitted to all stages of the shift register once in one frame (vertical scanning period) and in the vertical blanking period (from the output of the last stage of the shift register to the output of the first stage). Supplied, netA of all stages is set to Low.
  • the clear signal CLR also serves as a reset signal for the final stage of the shift register.
  • the source electrode or drain electrode of the TFT M17 is connected to the gate bus line (Gout (n) ) or VSS, and the gate electrode is connected to the output (Gout (n + 1) ) of the next stage.
  • the source electrodes or drain electrodes of the TFTs M18 and TFTM20 are connected to a gate bus line (Gout (n) ) or VSS, and these gate electrodes are connected to clock signal wirings having different phases.
  • the shift register shown in FIG. 17 is the same as the shift register shown in FIG. 16 except for the following points.
  • the drain electrode of the TFT M21d is connected to the gate electrode of the TFT M15.
  • the output (Gout (n ⁇ 2) ) of the previous stage is input to the diode-connected source electrode and gate electrode of the TFT M21d.
  • the source electrodes or drain electrodes of the TFTs M18 and TFTM20 are connected to a gate bus line (Gout (n) ) or VSS, and these gate electrodes are connected to clock signal wirings having the same phase.
  • TFT M15 is the first transistor
  • the second transistors TFT M16d, TFT M19d, TFT M21d, and TFT M22d have a dual channel structure. Therefore, these shift registers can also solve the above problem.
  • the circuit shown in FIG. 17 uses three clock signals CKA, CKB, and CCK having different phases in the circuit shown in FIG. 16, while using a common clock signal CKB for the transistors TFTM20 and TFTM18.
  • the clock signal CKC is omitted.
  • the output signal Gout (n ⁇ 2) of the previous stage is used for the TFT M21d.
  • FIG. 18 shows the structure of a shift register in which the present invention is applied to the shift register disclosed in this publication.
  • the TFT M23 is a first transistor
  • the second transistors TFT M24d and TFT M25d have a dual channel structure. Therefore, these shift registers can also solve the above problem.
  • the source electrode or drain electrode of the TFT M23 is connected to the wiring of the clock signal ⁇ 1 or the gate bus line (Gout (n) ).
  • the gate electrode of the TFT M23 is connected to a node to be bootstrapped (net A in FIG. 17, node G in FIG. 18).
  • the TFT M24d charges the node G.
  • the source electrode and the gate electrode of the TFT M24d are diode-connected, and are connected to the output signal Gout (n ⁇ 1) or the node G in the previous stage.
  • the TFT M25d discharges the node G.
  • the source electrode or drain electrode of the TFT M25d is connected to the node G or VSS (DC), and the gate electrode of the TFT M25d is connected to the wiring of the output signal Gout (n + 1) at the next stage.
  • a capacitor C4 represents a parasitic capacitance. Capacitor C6 prevents node G from changing when not selected. One end of the capacitor C6 is connected to the node G, and the clock signal ⁇ 2 is input to the other end.
  • the clock signal ⁇ 2 is a clock signal having a phase opposite to that of the clock signal ⁇ 1.
  • the clock signals ⁇ 1 and ⁇ 2 correspond to the clock signals CKA and CKB in FIG.
  • the capacitor C5 assists the output (prevents the output from being weakened by the capacitor C6).
  • the present invention can also be applied to a shift register disclosed in Japanese Patent Application Laid-Open No. 2005-50502. The entire disclosure of this publication is incorporated herein by reference.
  • the TFT Q2 is the first transistor
  • the TFT Q5, which is the second transistor is multi-channeled, so that the effect of the present invention can be obtained.
  • the source electrode or drain electrode of the TFT Q2 is connected to a clock signal (CK) wiring or a gate bus line (OUT).
  • the drain electrode of the TFT Q1 is connected to the gate electrode of the TFT Q2.
  • the output signal of the previous stage is input as an input signal to the diode-connected source electrode and gate electrode of the TFT Q1.
  • the source electrode or drain electrode of the TFT Q5 is connected to the gate electrode or gate bus line (OUT) of the TFT Q2, and the gate electrode of the TFT Q5 is connected to the wiring of the clock signal (CK).
  • the source electrode or drain electrode of the TFT Q4 is connected to the gate electrode of the TFT Q2 or VOFF (DC), and, for example, an output signal of the next stage is input as an input signal of the gate electrode of the TFT Q4.
  • the source electrode or drain electrode of the TFT Q3 is connected to the gate bus line (OUT) or VOFF (DC), and for example, the output signal of the next stage is input to the gate electrode of the TFT Q3 as an input signal.
  • the multi-channel TFT used in the shift register described above may be disclosed in Patent Document 3 or 4 or the like, but the multi-channel TFT according to the embodiment of the present invention described below may be used. preferable.
  • Multi-channel TFT Embodiments of a semiconductor device of the present invention will be described below with reference to the drawings.
  • a TFT including a microcrystalline silicon film as an active layer is illustrated, but the present invention is not limited to this.
  • FIG. 21 schematically shows a TFT 10 according to an embodiment of the present invention.
  • FIG. 21A is a schematic plan view of the TFT 10
  • FIG. 21B is a schematic cross section taken along line 21B-21B ′ in FIG. 21A
  • FIG. 2 is an equivalent circuit diagram of the TFT 10.
  • FIG. 21A is a schematic plan view of the TFT 10
  • FIG. 21B is a schematic cross section taken along line 21B-21B ′ in FIG. 21A
  • FIG. 2 is an equivalent circuit diagram of the TFT 10.
  • the TFT 10 has a dual channel structure, and electrically has a structure equivalent to two TFTs connected in series as shown in the equivalent circuit diagram of FIG.
  • the TFT 10 has an active layer 14 supported by a substrate (for example, a glass substrate) 11.
  • the active layer 14 is a semiconductor layer, and here includes a microcrystalline silicon film.
  • the active layer 14 includes channel regions 14c1 and 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1 and 14c2.
  • the case of having one intermediate region 14m and two channel regions 14c1 and 14c2 is illustrated, but the present invention is not limited to this, and has two or more intermediate regions and three or more channel regions. Also good.
  • the TFT 10 further contacts the source contact region 16s, a contact layer 16 having a source contact region 16s in contact with the source region 14s, a drain contact region 16d in contact with the drain region 14d, and an intermediate contact region 16m in contact with the intermediate region 14m.
  • the source electrode 18s, the drain electrode 18d in contact with the drain contact region 16d, the intermediate electrode 18m in contact with the intermediate contact region 16m, and the two channel regions 14c1, 14c2 and the intermediate region 14m are opposed to each other with the gate insulating film 13 therebetween.
  • the intermediate electrode 18m is a so-called floating electrode that does not form an electrical connection anywhere.
  • the TFT 10 further has a protective film 19 covering these.
  • the first channel region 14c1 is formed between the source region 14s and the intermediate region 14m
  • the second channel region 14c2 is formed between the drain region 14d and the intermediate region 14m.
  • the two channel regions 14c1 and 14c2, the source region 14s, the drain region 14d, and the intermediate region 14m are all formed in one continuous active layer 14. Further, the entire portion of the intermediate electrode 18m existing between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 with the intermediate region 14m and the gate insulating film 13 interposed therebetween.
  • the entire intermediate electrode 18m overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13, but the present invention is not limited to this.
  • the intermediate electrode 18m extends to the outside of the region between the first channel region 14c1 and the second channel region 14c2 located on both sides of the intermediate electrode 18m, for example, in FIG.
  • the portion existing outside the region between the first channel region 14c1 and the second channel region 14c2 does not need to overlap the gate electrode 12 with the intermediate region 14m and the gate insulating film 13 interposed therebetween.
  • the TFT 10 is that the entire portion of the intermediate electrode 18m existing between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 with the intermediate region 14m and the gate insulating film 13 interposed therebetween. Unlike the TFTs described in Patent Documents 3 and 4 (TFT 90 shown in FIG. 22 as a comparative example), the TFT has advantages such as excellent off-current reduction effect.
  • the TFT 10 is a bottom gate type (reverse stagger type) in which the gate electrode 12 is provided between the active layer 14 and the substrate 11, and This is a channel etching type in which channel regions 14c1 and 14c2 are formed in a region where the active layer 14 is etched.
  • the active layer 14 of the TFT 10 is formed of a microcrystalline silicon film or a laminated film of a microcrystalline silicon film and an amorphous silicon film, and can be manufactured by using a conventional amorphous silicon TFT manufacturing process.
  • the microcrystalline silicon film can be formed using, for example, a plasma CVD method similar to the method for forming an amorphous silicon film, using silane gas diluted with hydrogen gas as a source gas.
  • microcrystalline silicon film will be described in detail.
  • the microcrystalline silicon film has a structure in which a crystalline silicon phase and an amorphous silicon phase are mixed.
  • the volume ratio of the amorphous phase in the microcrystalline silicon film can be controlled in the range of 5% to 95%, for example.
  • the volume ratio of the amorphous phase is preferably 5% or more and 40% or less, whereby the on / off ratio of the TFT can be more effectively improved.
  • the spectrum has the highest peak at a wavelength of 520 cm ⁇ 1 , which is the peak of crystalline silicon, and the peak of amorphous silicon. And has a broad peak at a wavelength of 480 cm ⁇ 1 .
  • 480cm peak height of the amorphous silicon around -1 becomes less crystalline 1 for example 1/30 or more peak height of silicon found in the vicinity of 520 cm -1.
  • the Raman scattering spectrum analysis is performed on the polycrystalline silicon film, almost no amorphous component is confirmed, and the peak height of the amorphous silicon becomes almost zero.
  • an amorphous phase may remain locally depending on crystallization conditions. Even in such a case, the volume ratio of the amorphous phase in the polycrystalline silicon film is approximately It is less than 5%, and the peak height of amorphous silicon by Raman scattering spectrum analysis is approximately less than 1/30 of the peak height of polycrystalline silicon.
  • the microcrystalline silicon film includes crystal grains and an amorphous phase.
  • a thin amorphous layer (hereinafter referred to as “incubation layer”) may be formed on the substrate side of the microcrystalline silicon film.
  • the thickness of the incubation layer is, for example, several nm although it depends on the film formation conditions of the microcrystalline silicon film. However, there are cases where the incubation layer is hardly seen depending on the deposition conditions and deposition method of the microcrystalline silicon film, particularly when using high-density plasma CVD.
  • the crystal grains contained in the microcrystalline silicon film are generally smaller than the crystal grains constituting the polycrystalline silicon film.
  • the average grain size of the crystal grains is approximately 2 nm to 300 nm.
  • the crystal grains may take a form extending in a column shape from the incubation layer to the upper surface of the microcrystalline silicon film.
  • the diameter of the crystal grains is about 10 nm and the volume ratio of the crystal grains to the whole microcrystalline silicon film is 60% or more and 85% or less, a high-quality microcrystalline silicon film with few defects in the film can be obtained. .
  • the TFT 10 of the embodiment according to the present invention can reduce the off current of the TFT by a novel multi-gate structure.
  • FIG. 22 is a schematic diagram of a TFT 90 having a double gate structure described in Patent Documents 3 and 4,
  • FIG. 22 (a) is a schematic plan view
  • FIG. 22 (b) is a schematic diagram of FIG. FIG. 22 is a schematic cross-sectional view taken along line 22B-22B ′.
  • the gate electrode 92 of the TFT 90 is bifurcated and has two gate branch portions 92a and 92b. Active layers 94a and 94b corresponding to the two gate branch portions 92a and 92b are separately formed through a gate insulating film 93 covering the gate electrode 92. A source region 94s, a first channel region 94c1, and a first intermediate region 94ma are formed in the active layer 94a. A drain region 94d, a second channel region 94c2, and a second channel region 94ma are formed in the active layer 94b. An intermediate region 94mb is formed.
  • the source electrode 98s is formed to face the source region 94s through the source contact layer 96s, and the drain electrode 98d is formed to face the drain region 94d through the drain contact layer 96d.
  • the TFT 90 further has a protective film 99 covering these.
  • the intermediate electrode 98m of the TFT 90 is formed to face the intermediate region 94ma through the intermediate contact layer 96ma and to face the intermediate region 94mb through the intermediate contact layer 96mb.
  • the intermediate electrode 98m is formed so as to straddle between the two active layers 94a and 94b and between the two gate branches 92a and 92b.
  • the intermediate electrode 98m includes the first channel region 94c1 and the first channel region 94c1. There is a portion that does not overlap any of the active layers 94 a and 94 b and the gate electrode 92 in the portion existing between the two-channel regions 94 c 2.
  • the equivalent circuit of the TFT 90 is the same as the equivalent circuit of the TFT 10 shown in FIG. 21C, but the TFT 10 has the following advantages over the TFT 90 due to the difference in the configuration of the intermediate electrode and the active layer. Yes.
  • the TFT 10 can reduce the off current more than the TFT 90. The reason will be described below.
  • the TFT 90 only the both end portions of the intermediate electrode 98m are electrically connected to the active layers 94a and 94b via the intermediate contact layers 96ma and 96mb. It is connected. Accordingly, in the TFT 90, one end (the intermediate contact layer 96ma side) of the intermediate electrode 98m functions as a drain electrode for the source electrode 98s, and the other end (the intermediate contact layer 96mb side) of the intermediate electrode 98m is a source for the drain electrode 98d. It will function as an electrode. That is, the electric field concentrates on both end portions of the intermediate electrode 98m.
  • the entire intermediate electrode 18m is electrically connected to the active layer 14 through the intermediate contact layer 16m. Therefore, the intermediate electrode 18m itself functions as a drain electrode for the source electrode 18s and also functions as a source electrode for the drain electrode 18d. Therefore, the degree of electric field concentration at the intermediate electrode 18m of the TFT 10 is more relaxed than the degree of electric field concentration at both ends of the intermediate electrode 98m of the TFT 90. As a result, the off current of the TFT 10 is further smaller than the off current of the TFT 90, and the reliability of the TFT 10 is superior to the reliability of the TFT 90.
  • FIG. 23 shows an example of off current characteristics of the TFT 10 and the TFT 90.
  • FIG. 23 also shows off current characteristics of a TFT having a single channel structure.
  • the horizontal axis of FIG. 23 is the source-drain voltage Vds (V), and the vertical axis is the source-drain current Ids (A).
  • the gate voltage is 0 V
  • Ids indicates an off current.
  • the semiconductor layers of the TFT 10 and the TFT 90 used here are microcrystalline silicon films formed by a high density PECVD method.
  • the crystallinity of the microcrystalline silicon film is about 70% by Raman measurement, and the particle size is about 5 nm to 10 nm.
  • the TFT having the conventional dual channel structure has a smaller off current than the TFT having the single channel structure, and the TFT having the new dual channel structure according to the present invention further has an off current. small.
  • the dual channel structure according to the present invention since the electric field concentration in the intermediate electrode is relaxed, the off-current can be reduced particularly when a high electric field is applied.
  • the horizontal axis of FIG. 24 is the gate voltage Vg (V), and the vertical axis is the source-drain current Ids (A).
  • the source-drain voltage Vds is 10V.
  • the dual channel structure is the same structure as the TFT 10 shown in FIG. 21, the single channel structure is a structure that does not have the intermediate electrode 18m of the TFT 10, and the triple channel structure has two intermediate electrodes 18m of the TFT 10. It is a structure arranged in parallel. All channel lengths were 6 ⁇ m. That is, the single channel structure has one channel with a channel length of 6 ⁇ m (L6-SG), the dual channel structure has two channels with a channel length of 3 ⁇ m (L6-DG), and the triple channel structure has each channel It has three channels with a channel length of 2 ⁇ m (L6-TG).
  • L6-SG channel with a channel length of 6 ⁇ m
  • L6-DG channel length of 3 ⁇ m
  • the off-current can be reduced by adopting the dual channel structure and the triple channel structure. It can also be seen that the triple channel structure is more effective in reducing the off-current than the dual channel structure.
  • Table 1 shows the value of off-current between the source and drain when the gate voltage is 0 V and the source-drain voltage Vds is 40 V, and when the gate voltage is -29 V and the source-drain voltage Vds is 10 V. Indicates.
  • the off-current when the gate voltage Vg is 0 V is 1 to 2 digits more than the single channel structure by adopting the dual channel structure or the triple channel structure. Can be reduced.
  • Vds is 10 V
  • the off-state current when the gate voltage Vg is ⁇ 29 V can be reduced by about one digit as compared with the single channel structure by adopting the dual channel structure or the triple channel structure.
  • the off-current of the TFT can be effectively reduced.
  • the leakage current in the off region as well as the leakage current in the sub-threshold region of the TFT can be reduced. Therefore, by configuring a shift register using the TFT of the present invention, the characteristics of the shift register can be improved. Further, by using the TFT of the present invention for a pixel TFT as in Patent Document 3 or 4, the voltage holding characteristics of the pixel can be improved.
  • the TFT can be made smaller than the TFT having the conventional multi-channel structure.
  • the TFT 10 has a smaller length in the channel direction than the TFT 90.
  • the length of the TFT 10 in the channel direction (the direction from the source electrode 18s to the drain electrode 18d) is given by 2L1 + 2L2 + L3, as can be seen from FIG.
  • L1 is the length of the region where the source electrode 18s overlaps the gate electrode 12 with the active layer 14 interposed therebetween, or the length of the region where the drain electrode 18d overlaps the gate electrode 12 with the active layer 14 interposed therebetween.
  • L2 is the length of each of the channel regions 14c1 and 14c2.
  • the length of the TFT 90 in the channel direction (the direction from the source electrode 98s to the drain electrode 98d) is given by 2L1 + 2L2 + 2L4 + L5, as can be seen from FIG.
  • L1 is the length of the region where the source electrode 98s overlaps the gate branch portion 92a with the active layer 94a interposed therebetween, or the length of the region where the drain electrode 98d overlaps the gate branch portion 92b with the active layer 94b interposed therebetween.
  • L2 is the length of each of the channel regions 94c1 and 94c2.
  • L4 is the length of the region where the intermediate electrode 98m overlaps the gate branch portion 92a with the active layer 94a interposed therebetween, or the length of the region where the intermediate electrode 98m overlaps the gate branch portion 92b with the active layer 94b interposed therebetween.
  • L1 3 ⁇ m
  • L2 4 ⁇ m
  • L4 3 ⁇ m
  • L5 5 ⁇ m
  • the TFT can be miniaturized by adopting the novel dual channel structure according to the present invention.
  • the active matrix substrate 101 exemplified here is used in a liquid crystal display device.
  • the gate electrode 12 is formed on the glass substrate 11.
  • the gate electrode 12 is formed by, for example, patterning a Ti / Al / Ti laminated film (for example, a thickness of 0.2 ⁇ m).
  • a gate bus line and a CS bus line can be formed using the same conductive film as the gate electrode 12.
  • a gate insulating film 13, a microcrystalline silicon film 14, and an N + silicon film 16 are successively formed in this order.
  • the gate insulating film 13 is formed, for example, by depositing a SiN x film (for example, a thickness of 0.4 ⁇ m) 13 by a parallel plate type plasma CVD method.
  • a microcrystalline silicon film (for example, a thickness of 0.12 ⁇ m) 14 is formed by a high-density plasma CVD method.
  • the N + silicon film (for example, having a thickness of 0.05 ⁇ m) 16 is formed by a high density plasma CVD method or a parallel plate type plasma CVD method.
  • the SiN x film 13 is formed by using, for example, a film forming chamber having a parallel plate type (capacitive coupling type) electrode structure, a substrate temperature: 300 ° C., a pressure: 50 to 300 Pa, and a power density: 10 to 20 mW / Performed under conditions of cm 2 . Further, a mixed gas of silane (SiH 4 ), ammonia (NH 3 ), and nitrogen (N 2 ) is used as a film forming gas.
  • SiH 4 silane
  • NH 3 ammonia
  • N 2 nitrogen
  • the microcrystalline silicon film 14 is formed using ICP type high density PECVD under the conditions of substrate temperature: 250 to 350 ° C., pressure: 0.5 to 5 Pa, power density: 100 to 200 mW / cm 2 , Silane gas diluted with hydrogen gas is used as a film forming gas.
  • the flow ratio of silane (SiH 4 ) and hydrogen (H 2 ) is 1: 1 to 1:10.
  • the N + silicon film 16 is formed using a film formation chamber having a parallel plate type (capacitive coupling type) electrode structure, substrate temperature: 250 to 300 ° C., pressure: 50 to 300 Pa, and power density: 10 to 20 mW. / Cm 2 . Further, as a film forming gas, a mixed gas of silane (SiH 4 ), hydrogen (H 2 ), and phosphine (PH 3 ) is used.
  • the microcrystalline silicon film 14 and the N + silicon film 16 are patterned to obtain the active layer 14 and the contact layer 16.
  • a metal film (so-called source metal) is formed so as to cover the N + silicon film 16, and the source electrode 18s, the drain electrode 18d, and the intermediate electrode 18m are formed by patterning.
  • the metal film for example, a laminated film of Al / Mo can be used.
  • a contact layer (N + silicon layer) 16 is etched by dry etching using a mask (for example, a photoresist layer) used for etching the metal film, thereby providing a source contact region 16s, a drain contact region 16d, and an intermediate contact. Separated into area 16m. At this time, a part of the active layer (microcrystalline silicon film) 14 is also etched (channel etch). The remaining film thickness of the active layer 14 is about 40 nm.
  • a protective film 19 is formed.
  • the protective film 19 for example, a SiN x film formed by plasma CVD can be used. In this way, the TFT 10 is obtained.
  • a planarizing film 22 is formed.
  • the planarization film 22 is formed using, for example, an organic resin film.
  • Contact holes 22 a are formed in the planarizing film 22 and the protective film 19.
  • a pixel electrode 24 is formed by forming a transparent conductive film (for example, ITO film) and patterning it. The pixel electrode 24 is connected to the drain electrode 18d in the contact hole 22a.
  • the active matrix substrate 101 having the TFT 10 connected to the pixel electrode 24 is obtained.
  • FIG. 26 (a) is a schematic plan view of the TFT 10A
  • FIG. 26 (b) is a schematic plan view of the TFT 10B.
  • the cross-sectional structures of the TFT 10A and TFT 10B are the same as the cross-sectional structure of the TFT 10 shown in FIG.
  • the TFT 10A shown in FIG. 26A has a dual channel structure similar to that of the TFT 10 shown in FIG.
  • the TFT 10A has a gate electrode 12, an active layer 14, a source electrode 18sa, a drain electrode 18da, and an intermediate electrode 18ma formed on a substrate (not shown).
  • Contact layers are formed between the electrodes 18sa, 18da and 18ma and the active layer 14, respectively.
  • a region where the active layer 14 overlaps the source electrode 18sa via the contact layer is a source region
  • a region where the active layer 14 overlaps the drain electrode 18da via the contact layer is a drain region
  • the active layer 14 is A region overlapping the intermediate electrode 18ma through the contact layer is an intermediate region.
  • the source region has the same shape as the source electrode 18sa
  • the drain region has the same shape as the drain electrode 18da
  • the intermediate region has the same shape as the intermediate electrode 18ma. .
  • the TFT 10A is characterized in that the area of the portion where the gate electrode 12 overlaps the drain region is smaller than the area of the portion where the gate electrode 12 overlaps the source region.
  • the intermediate electrode 18ma has a concave portion 18ma2, and the drain electrode 18da has a portion 18da1 protruding into the concave portion 18ma2 of the intermediate electrode 18ma.
  • a portion where the drain electrode 18da overlaps with the gate electrode 12 through the active layer 14 (that is, the drain region) is a portion 18da1 protruding thinly from the main body.
  • the drain electrode 18d of the TFT 10 shown in FIG. 21A the drain electrode 18da of the TFT 10A has a small area where it overlaps the gate electrode 12 with the active layer 14 in between.
  • the source electrode 18sa has a recess 18sa1
  • the intermediate electrode 18ma has a portion 18ma1 protruding into the recess 18sa1 of the source electrode 18sa.
  • the source electrode 18sa of the TFT 10A has a large area where it overlaps the gate electrode 12 through the active layer 14.
  • the drain electrode 18da, the intermediate electrode 18ma, and the source electrode 18sa have the shapes as described above. Therefore, the area of the portion where the gate electrode 12 overlaps the drain region is as follows. The area of the portion where the gate electrode 12 overlaps the source region is smaller. The area of the portion where the gate electrode 12 overlaps the drain region is smaller than the area of the portion where the gate electrode 12 overlaps the intermediate region.
  • the configuration on the right side of the intermediate electrode 18ma of the TFT 10A in FIG. 26A is the same as the configuration on the right side of the intermediate electrode 18m of the TFT 10 shown in FIG.
  • the area of the portion overlapping the drain electrode 18d is smaller than the area of the portion where the gate electrode 12 overlaps the source electrode 18sa via the active layer 14.
  • the gate electrode 12 overlaps the drain region.
  • a configuration in which the area of the portion is smaller than the area of the portion where the gate electrode 12 overlaps the source region can be obtained.
  • FIG. 27 shows the relationship between the gate voltage Vg (V) and the source-drain current Ids (A) for the TFT 10A shown in FIG. 26A and the TFT 10B shown in FIG. Show.
  • the horizontal axis in FIG. 27 is the gate voltage Vg (V)
  • the vertical axis is the source-drain current Ids (A).
  • the results show that the source-drain voltage Vds (V) is 5V and 10V.
  • the TFT 10B illustrated in FIG. 26B corresponds to a TFT 10A illustrated in FIG. 26A in which the source side and the drain side are interchanged.
  • the drain electrode 18db has a recess 18db1
  • the intermediate electrode 18mb has a portion 18mb2 protruding into the recess 18db1 of the drain electrode 18db.
  • the intermediate electrode 18mb has a recess 18mb1
  • the source electrode 18sb has a portion 18sb1 protruding into the recess 18mb1 of the intermediate electrode 18mb. Accordingly, in the TFT 10B, the area of the portion where the gate electrode 12 overlaps the drain region is larger than the area of the portion where the gate electrode 12 overlaps the source region.
  • the TFT 10A has a smaller off-current than the TFT 10B when the source-drain voltage Vds (V) is 5 V or 10 V. From this, it can be seen that the off-current of the TFT can be reduced by reducing the area of the portion where the gate electrode 12 overlaps the drain region.
  • Vds source-drain voltage
  • the TFT 10A is used as the second transistor of the shift register described above, it is preferable to connect the drain electrode 18da to the netA (gate electrode of the first transistor).
  • the source electrode 18sa is connected to VSS, for example.
  • the magnitude of the off-current depends on the area of the portion where the gate electrode 12 overlaps the drain region. In that sense, the relative magnitude relationship with the area of the portion where the gate electrode 12 overlaps the source region is not important. Absent. However, if the area of the portion where the gate electrode 12 overlaps the drain region is reduced in order to reduce the off-current of the TFT, the area of the portion where the gate electrode 12 overlaps the drain region becomes smaller than the portion where the gate electrode 12 overlaps the source region. The asymmetric configuration is smaller than the area.
  • the TFT characteristics depend on the channel width, and it is preferable that the channel width is large.
  • the channel region can be made U-shaped and the channel width can be increased.
  • FIG. 28 (a) shows a schematic plan view of a TFT 10C according to an embodiment of the present invention.
  • the TFT 10C has a dual channel structure like the TFT 10 shown in FIG.
  • the intermediate electrode 18mc included in the TFT 10C has an H shape, and has U-shaped concave portions on the drain side and the source side.
  • the drain electrode 18dc and the source electrode 18sc each have a portion protruding into the recess of the intermediate electrode 18mc.
  • the area where the gate electrode 12 overlaps the drain region and the area where the gate electrode 12 overlaps the source region are both smaller than the area where the gate electrode 12 overlaps the intermediate region.
  • the TFT 10C has a smaller area where the gate electrode 12 overlaps the drain region and a larger width of the two channel regions than the TFT 10. Therefore, the TFT 10C has a smaller off-current and superior TFT characteristics than the TFT 10.
  • FIG. 28B shows a schematic plan view of the TFT 10D according to the embodiment of the present invention.
  • the TFT 10D has a triple channel structure including two intermediate electrodes 18md1 and 18md2, whereas the TFT 10A shown in FIG. 26A has a dual channel structure. That is, the first channel region is formed between the source electrode 18sd and the first intermediate electrode 18md1, the second channel region is formed between the drain electrode 18dd and the second intermediate electrode 18md2, and the first channel region is formed. A third channel region is formed between the intermediate electrode 18md1 and the second intermediate electrode 18md2.
  • a first intermediate contact region is formed in the contact layer under the first intermediate electrode 18md1, and the first intermediate region is formed in the active layer under the first intermediate contact region. Is formed.
  • a second intermediate contact region is formed in the contact layer under the second intermediate electrode 18 md 2, and a second intermediate region is formed in the active layer under the second intermediate contact region.
  • the portion functioning as the drain electrode for each of the three channels of the TFT 10D is a protruding portion (the protruding portion of the intermediate electrodes 18md1 and 18md2 and the protruding portion of the drain electrode 18dd), and the area overlapping the gate electrode 12 Therefore, the effect of reducing off-state current is large.
  • the area where the gate electrode 12 overlaps the drain region and the area where the gate electrode 12 overlaps the source region are both smaller than the area where the gate electrode 12 overlaps the intermediate region.
  • each of the three channels functions as a source electrode having a U-shaped concave portion, and a protruding portion of the intermediate electrodes 18md1 and 18md2 or a protruding portion of the drain electrode 18dd exists in each concave portion. Yes. Therefore, the width of the three channel regions is large and has excellent TFT characteristics.
  • the TFT 10D is used as the second transistor of the shift register described above, it is preferable to connect the drain electrode 18dd to the netA (gate electrode of the first transistor).
  • FIG. 28 (c) shows a schematic plan view of the TFT 10E according to the embodiment of the present invention.
  • the TFT 10E has a triple channel structure including two intermediate electrodes 18me1 and 18me2 similarly to the TFT 10D shown in FIG. That is, a first channel region is formed between the source electrode 18se and the first intermediate electrode 18me1, and a second channel region is formed between the drain electrode 18de and the second intermediate electrode 18me2. A third channel region is formed between the intermediate electrode 18me1 and the second intermediate electrode 18me2.
  • the second intermediate electrode 18me2 has an H shape, and has U-shaped concave portions on the drain side and the source side.
  • the protruding portion of the drain electrode 18de exists in one recess of the second intermediate electrode 18me2, and one end of the rectangular first intermediate electrode 18me1 exists in the other recess of the second intermediate electrode 18me2.
  • the source electrode 18se has a U-shaped recess, and the other end of the first intermediate electrode 18me1 exists in the recess of the source electrode 18se.
  • the TFT 10E also has an advantage that the area of the portion where the gate electrode 12 overlaps the drain region is smaller than the area of the portion where the gate electrode 12 overlaps the source region, and the off current is small. In addition, the area where the gate electrode 12 overlaps the drain region and the area where the gate electrode 12 overlaps the source region are both smaller than the area where the gate electrode 12 overlaps the intermediate region.
  • the drain electrode 18de is preferably connected to netA (gate electrode of the first transistor).
  • FIG. 29A shows a schematic cross-sectional view of a TFT 10F according to an embodiment of the present invention.
  • the TFT 10 shown in FIG. 21 is a channel etching type TFT, but the TFT 10F is different in that it has an etch stop layer 17.
  • the TFT 10F is manufactured by adding a step of forming an etch stop layer 17 after forming the microcrystalline silicon film 14 in the manufacturing process of the TFT 10 shown in FIG.
  • the etch stop layer 17 is formed, for example, by depositing and patterning a SiN x film (for example, a thickness of 0.15 ⁇ m).
  • the active layer (microcrystalline silicon) is separated when the contact layer (N + silicon layer) 16 is etched to be separated into the source contact region 16s, the drain contact region 16d, and the intermediate contact region 16m.
  • the film 14 is not etched. Therefore, there is an advantage that the thickness of the active layer 14 can be controlled by the film forming process. Further, there is an advantage that the active layer 14 is not damaged by etching. Furthermore, since the gate insulating film 13, the active layer 14, and the etch stop layer 17 can be continuously formed, an advantage that the process stability is high is also obtained.
  • the TFT of the embodiment according to the present invention may be a top gate type (stagger type) TFT as shown in FIGS. 29B and 29C.
  • the TFT 10G shown in FIG. 29B includes a source electrode 18sg, an intermediate electrode 18mg, and a drain electrode 18dg formed on the glass substrate 11, and a source contact region 16sg and a drain contact region 16dg formed so as to cover them. And an intermediate contact region 16 mg.
  • An active layer 14g is formed so as to cover the source contact region 16sg, the drain contact region 16dg, and the intermediate contact region 16mg, and a gate insulating film 13g is formed thereon.
  • the gate electrode 12g is formed so as to overlap the entire intermediate electrode 18mg (the portion existing between the two channels), a part of the source electrode 18sg, and a part of the drain electrode 18dg through the gate insulating film 13g. ing.
  • the TFT 10G also has a double gate structure like the TFT 10.
  • a source lead electrode 18sg1 and a drain lead electrode 18dg1 are formed from the same conductive layer as the gate electrode 12g, and in the contact holes formed in the gate insulating film 13g, the active layer 14g, and the contact regions 16sg and 16dg, Each is electrically connected to the source electrode 18sg and the drain electrode 18dg.
  • the top gate type when the top gate type is adopted, there is an advantage that the vicinity of the uppermost surface of the active layer 14 formed of the microcrystalline silicon film can be used as the channel region.
  • a microcrystalline silicon film is formed on a substrate, a layer made of an amorphous phase called an incubation layer may be formed in the lowermost layer.
  • the portion in contact with the substrate is formed at the initial stage of film formation, it easily contains voids and has low mobility.
  • the top gate type since the incubation layer is not included in the channel region, the high mobility of the microcrystalline silicon film can be fully utilized.
  • the TFT 10H shown in FIG. 29C has an active layer 14h formed on the substrate 11, a source contact region 16sh formed on the active layer 14h, a drain contact region 16dh, and an intermediate contact region 16mh. Yes. Each contact region is divided by channel etching like the TFT 10.
  • a gate insulating film 13h is formed so as to cover the active layer 14h, the source contact region 16sh, the drain contact region 16dh, and the intermediate contact region 16mh.
  • the gate electrode 12h is connected to the whole intermediate contact region 16mh (here also serving as the intermediate electrode) (a portion existing between two channels), a part of the source contact region 16sh, and the drain contact region via the gate insulating film 13h.
  • the TFT 10H also has a double gate structure like the TFT 10.
  • a source lead electrode (source electrode) 18sh and a drain lead electrode (drain electrode) 18dh are formed from the same conductive layer as the gate electrode 12h, and are formed on the gate insulating film 13h, the active layer 14h, and the contact layers 16sh and 16dh. In the formed contact holes, they are electrically connected to the source lead electrode 18sh and the drain lead electrode 18dh, respectively.
  • the TFT 10H also has a top gate structure, the advantage that the vicinity of the uppermost surface of the active layer 14h formed from the microcrystalline silicon film can be used as a channel region is obtained as in the TFT 10G. Further, in the TFT 10H, since the intermediate contact region 16mh also serves as the intermediate electrode, there is an advantage that the step of forming the intermediate electrode can be omitted.
  • the configuration in which the intermediate contact region also serves as the intermediate electrode is not limited to the TFT 10H, and can be applied to other TFTs described above.
  • the TFT according to the embodiment of the present invention may be either a bottom gate type or a top gate type, and can reduce an off-current.
  • the TFT according to the embodiment of the present invention can have high mobility and low off-state current by including a microcrystalline silicon film as an active layer. This is effective not only when the active layer has only a microcrystalline silicon film but also when it has a laminated film of a microcrystalline silicon film and an amorphous silicon film. Note that in order to utilize the high mobility of the microcrystalline silicon film, it is preferable to dispose the microcrystalline silicon film closer to the gate electrode than the amorphous silicon film so that a channel is formed in the microcrystalline silicon film. .
  • the TFT according to the embodiment of the present invention has been described by taking the semiconductor film formed only of silicon as an example.
  • the embodiment according to the present invention is not limited to the type of the semiconductor film, and it is desirable to reduce the off current.
  • the present invention can be applied to a TFT having another microcrystalline semiconductor film, for example, a microcrystalline SiGe film or a microcrystalline SiC film.
  • amorphous silicon or microcrystalline silicon is advantageous in mass production as described above, but polycrystalline silicon can also be used.
  • the semiconductor element of the present invention includes a circuit substrate such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, and a flat panel X-ray image sensor device.
  • a circuit substrate such as an active matrix substrate
  • a liquid crystal display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device
  • EL organic electroluminescence
  • inorganic electroluminescence display device an inorganic electroluminescence display device
  • flat panel X-ray image sensor device a flat panel X-ray image sensor device.
  • the present invention can be widely applied to devices including thin film transistors, such as electronic devices such as imaging devices, image input devices, and fingerprint readers.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Liquid Crystal (AREA)

Abstract

L'invention porte sur un registre à décalage supporté par un substrat isolant et formé d'une pluralité d'étages. Chacun des étages émet de manière successive un signal de sortie, et comprend : un premier transistor (MA) qui émet un signal de sortie ; et une pluralité de seconds transistors (ME, MF) possédant chacun une région de source ou une région de drain connectée électriquement à l'électrode de grille du premier transistor (MA). Les seconds transistors comprennent un transistor à multiples canaux possédant une couche active contenant au moins deux régions de canal, une région de source et une région de drain. Ceci améliore une caractéristique du registre à décalage constituant le pilote de grille monolithique.
PCT/JP2009/006227 2008-11-20 2009-11-19 Registre à décalage WO2010058581A1 (fr)

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