Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
  • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
  • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Definitions

• non-volatile devices such as flash memory devices
• flash memory devices for storage of data
• USB flash drives universal serial bus
• flash devices are used as solid state drives (SSDs) for hard disk drive (HDD) replacement
• SSDs solid state drives
• HDD hard disk drive
• multimedia and SSD applications require large amounts of memory which can increase the form factor size and weight of their products Therefore, consumer product manufacturers compromise by limiting the amount of physical memory included in the product to keep its size and weight acceptable to consumers
• flash memory has a higher density per unit area than DRAM or SRAM, its performance is limited due to its relatively low I/O bandwidth that negatively impacts its read and write throughput
• a composite memory device including a bridge device and discrete memory devices is disclosed
• the devices are, for example, memory devices, such as flash memories, dynamic random access memories (DRAMs), and static random access memories (SRAMs), DiNOR Flash EEPROM dev ⁇ ce(s), Serial Flash EEPROM dev ⁇ ce(s), Ferro RAM dev ⁇ ce(s), Magneto RAM dev ⁇ ce(s), Phase Change RAM dev ⁇ ce(s), or any suitable combination of these and/or other devices
• a composite memory device comprising at least one discrete memory device and a bridge device
• the at least one discrete memory device executes memory operations in response to local memory control signals having a first format
• the bridge device receives global memory control signals having a second format and converts the global memory control signals into the local memory control signals
• the bridge device can include a local input/output port connected to the at least one discrete memory device, a global input port for receiving the global memory control signals, and a global output port for providing one of the global memory control signals and read data from the at least one discrete memory device
• the at least one discrete memory device and the bridge device can be encapsulated in a package
• the global input port and the global output port can be electrically coupled to leads of the package Electrical conductors can be used couple the local input/output port to the at least one discrete memory device Alternatively, the local input/output port can be wirelessly coupled to the at least one discrete memory device
• the at least one discrete memory device can be a packaged memory device and the bridge device can be a packaged bridge device
• the packaged memory device and the packaged bridge device can be mounted onto a printed circuit board
• the local input/output port, the global input port and the global output port can be electrically coupled to leads of the packaged bridge device
• the packaged memory device can have memory leads electrically connected to the local input/output port of the packaged bridge device
• the global memory control signals, in the composite memory device can be received in a global command
• the global command can further include an address header
• the address header can include a global device address corresponding to a selected composite memory device and a local device address corresponding to a selected discrete memory device of the at least one discrete memory device in the selected composite memory device
• the first format can include a serial data interface format or an ONFi specification interface format and the second format can include an asynchronous flash memory format
• a memory system comprising a memory controller and n composite memory devices connected serially with each other and the memory controller in a ring topology configuration
• the memory controller provides a global command corresponding to a memory operation
• Each of the n composite memory devices has m discrete memory devices and a bridge device
• the bridge device of a selected composite memory device of the n composite memory devices receives the global command and provides local memory control signals corresponding to the memory operation to a selected discrete memory device of the m discrete memory devices, where n and m are integer values greater than 0
• each of the n composite memory devices can be a system in package (SIP) or a printed circuit board (PCB)
• SIP system in package
• PCB printed circuit board
• the m discrete memory devices and the bridge device can be packaged devices having package leads connected to conductive tracks in the PCB
• the bridge device can include a bridge device input/output interface, a format conversion circuit and a memory device interface
• the bridge device input/output interface has an input port for receiving the global command and an output port for providing the global command
• the bridge device compares the global device address to a predetermined address stored in a global device address register and when the global device address matches the predetermined address, the format conversion circuit converts the global memory control signals of the global command from a first format to the local memory control signals having a second format
• the memory device interface then provides the local memory control signals to the selected discrete memory device in response to the local device address
• the format conversion circuit comprises a command format converter and a data format converter
• the command format converter converts the global memory control signals in the first format to the local memory control signals having the second format
• the data format converter converts read data from the selected discrete memory device from the second format to the first format In a write operation, the data format converter converts write data from the first format to the second format
• a composite memory device in the memory system can have different types of discrete memory devices
• the bridge device can include a number of format conversion circuits corresponding to each type of the different types of discrete memory devices
• a composite memory device package The composite memory device package includes at least one discrete memory device and a bridge device The at least one discrete memory device executes memory operations in response to local memory control signals having a first format The bridge device receives global memory control signals having a second format and converts the global memory control signals into the local memory control signals The bridge device and the at least one discrete memory device are positioned in a stacked manner in relation to each other
• the memory module includes at least one packaged discrete memory device and a packaged bridge device
• the at least one packaged discrete memory device has memory device leads bonded to conductive tracks of a printed circuit board
• the at least one packaged memory device executes memory operations in response to local memory control signals having a first format
• the packaged bridge device has bridge device leads bonded to the conductive tracks of the printed circuit board
• the at least one packaged bridge device receives global memory control signals having a second format and for converting the global memory control signals into the local memory control signals
• a bridge device to access a discrete memory device in response to global signals having a global format
• the bridge device includes a bridge device input/output interface and a bridge device memory device interface
• the bridge device input/output interface communicates the global signals having the global format to and from the bridge device
• the bridge device memory device interface communicates local signals having a local format between the bridge device and the discrete memory device
• the local signals correspond in function to the global signals and have a local format different from the global format
• a memory system having a memory controller and n composite memory devices
• the memory controller provides a global command corresponding to a memory operation
• the n composite memory devices are connected in parallel with each other and the memory controller, where each of the n composite memory devices has m discrete memory devices and a bridge device
• the bridge device of a selected composite memory device of the n composite memory devices receives the global command for providing local memory control signals corresponding to the memory operation to a selected discrete memory device of the m discrete memory devices, where n and m are integer values greater than 0
• Fig 1 A is a block diagram of an example non-volatile memory system
• Fig 1 B is a diagram of a discrete flash memory device used in the example memory system of Figure 1A
• Fig 1A is a block diagram of an example non-volatile memory system
• Fig 2A is a block diagram of an example serial memory system
• Fig 2B is a diagram of a discrete serial interface flash memory device used in the example memory system of Figure 2A,
• Fig 3A is a block diagram of a composite memory device having four discrete memory devices and a bridge device in accordance with an embodiment
• Fig 3B is an illustration of a global command, according to a present embodiment
• Fig 4 is a block diagram of a bridge device in accordance with an embodiment
• Fig 5A is a cross-section of a composite memory device in a package in accordance with another embodiment
• Fig 5B is a cross-section of an alternate composite memory device in a package in accordance with another embodiment
• Fig 6 is a block diagram of a memory system having a number of discrete memory devices connected to a bridge device in a module in accordance with another embodiment
• Fig 7 is a block diagram of a memory system having a number of composite memory devices connected to a controller in a serial interconnected memory system in accordance with an embodiment
• Fig 8 is a block diagram showing memory mapping of the bridge device of Figure 3A to NAND flash memory devices, according to a present embodiment
• Figs 9A, 9B and 9C illustrate an example read operation from one NAND flash memory device using the bridge device of Figure 3A
• Figs 1 OA, 1 OB, 10C and 10D illustrate example virtual page configurations for each memory bank of the bridge device of Figure 3A
• Fig 11 is a flow chart illustrating a method for reading data from a composite memory device, according to a present embodiment.
• Fig 12 is a flow chart illustrating a method for writing data to a composite memory device, according to a present embodiment DETAILED DESCRIPTION
• the embodiments of the present invention are directed to a composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices
• the discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices, which respond to native, or local memory control signals
• the global and local memory control signals include commands and command signals each having different formats
• the bridge device includes a bridge device input/output interface, a format conversion circuit, and, a memory device interface
• the bridge device input/output interface communicates with a memory controller or another composite memory device in a global format
• the format conversion circuit converts global memory control signals from the global format to a corresponding local format compatible with discrete memory devices connected to it
• the global format is followed only by the global memory control signals received by the bridge devices, while the local format is followed only by the local memory control signals used by the discrete memory devices
• the memory device interface communicates with each discrete memory device connected to the bridge device in the local format
• the system and device in accordance with the techniques described herein are applicable to a memory system having a plurality of devices connected in series
• the devices are, for example, memory devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), flash memories, DiNOR Flash EEPROM memories, Serial Flash EEPROM memories, Ferro RAM memories, Magneto RAM memories, Phase Change RAM memories, and any other suitable type of memory
• Figure 1A is a block diagram of a non-volatile memory system 10 integrated with a host system 12
• the system 10 includes a memory controller 14 in communication with host system 12, and a plurality of non-volatile memory devices 16-1, 16-2, 16-3 and 16-
• the non-volatile memory devices 16-1 - 16-4 can be discrete asynchronous flash memory devices
• the host system 12 includes a processing device such as a microcontroller, microprocessor, or a computer system
• the system 10 of Figure 1 A is organized to include one channel 18, with the memory devices 16-1 - 16-4 being connected in parallel to channel 18
• the system 10 can have more or fewer than four memory devices connected to it
• the memory devices 16-1 - 16-4 are asynchronous and connected in parallel with each other
• Channel 18 includes a set of common buses, which include data and control lines that are connected to all of its corresponding memory devices Each memory device is enabled or disabled with respective chip select (enable) signals CE1#, CE2#, CE3# and CE4#, provided by memory controller 14 In this and following examples, the "#" indicates that the signal is an active low logic level signal In this scheme, one of the chip select signals is typically selected at one time to enable a corresponding one of the non-volatile memory devices 16-1 - 16-4
• the memory controller 14 is responsible for issuing commands and data, via the channel 18, to a selected memory device in response to the operation of the host system 12 Read data output from the memory devices is transferred via the channel 18 back to the memory controller 14 and host system 12
• the system 10 is generally said to include a multi-drop bus, in which the memory devices 16-1 - 16-4 are connected in parallel with respect to channel 18
• Figure 1 B is a diagram of one of the discrete flash memory devices 16-1 - 16-
• This flash memory device includes several input and output ports, which include for example power supply, control ports and data ports
• the term "ports" refers to a generic input or output terminals into the memory device, which includes package pins, package solder bumps, chip bond pads, and wireless transmitters and receivers for example
• the power supply ports include VCC and VSS for supplying power to all the circuits of the flash memory device Additional power supply ports can be provided for supplying only the input and output buffers, as is well known in the art Table 1 below provides a listing of the control and data ports, their corresponding descriptions, definitions, and example logic states It is noted that that package pins and ball grid arrays are physical examples of a port, which is used for interconnecting signals or voltages of a packaged device to a board
• the ports can include other types of connections, such as for example, terminals and contacts for embedded and system-in-package (SIP) systems
• I/O[n] I/O Port are used as a port for transferring address, command and input/output data to and from the device
• Variable n can be any non-zero integer value
• All the signals noted in Table 1 are generally referred to as the memory control signals for operation of the example flash memory device illustrated in Figure 1 B It is noted that the last port I/O[n] is considered a memory control signal as it can receive commands which instruct the flash memory device to execute specific operations Because a command asserted on port I/O[n] is a combination of logic states applied to each individual line making up I/O[n], the logic state of each signal of I/O[n] functions in the same manner as one of the other memory control signals, such as WP# for example The main difference being that it is a specific combination of I/O[n] logic states controls the flash memory device to perform a function The commands are received via its I/O ports and the command signals include the remaining control ports Those skilled in the art understand that operational codes (op codes) are provided in the command for executing specific memory operations With the exception of the chip enable CE#, all the other ports are coupled to respective global lines that make up channel 18 Individual chip enable signals are provided to each flash memory device by the memory controller 14 All
• Each of the non-volatile memory devices of Figure 1 A has one specific data interface for receiving and providing data
• this is a parallel data interface commonly used in asynchronous flash memory devices
• Standard parallel data interfaces providing multiple bits of data in parallel are known to suffer from well known communication degrading effects such as cross-talk, signal skew and signal attenuation, for example, which degrades signal quality, when operated beyond their rated operating frequency
• FIG. 2A is a block diagram illustrating the conceptual nature of a serial memory system
• the serial ring-topology memory system 20 includes a memory controller 22 having a set of output ports Sout and a set of input ports Sm, and memory devices 24, 26, 28 and 30 that are connected in series
• the memory devices can be serial interface flash memory devices for example While not shown in Figure 2A, each memory device has a set of input ports Sin and a set of output ports Sout These sets of input and output ports includes one or more individual input/output ports, such as physical pins or connections, interfacing the memory device to the system it is a part of
• the memory devices can be flash memory devices Alternately, the memory devices can be DRAM, SRAM, DiNOR Flash EEPROM, Serial Flash EEPROM, Ferro RAM, Magneto RAM, Phase Change RAM, or any other suitable type of memory device that has an input/output interface compatible with a specific command structure, for executing commands or for passing commands and data through to the next memory device
• FIG. 2B is a diagram of the serial interface flash memory device (24 to 30 for example) which can be used in the memory system of Figure 2A
• This example serial interface flash memory device includes power supply ports, control ports and data ports
• the power supply ports include VCC and VSS for supplying power to all the circuits of the flash memory device Additional power supply ports can be provided for supplying only the input and output buffers, as is well known in the art.
• Table 2 below provides a listing of the control and data ports, their corresponding descriptions, and example logic states [0036] Table 2
• the echo signal DSO is a re-transmitted version of the source signal DSI
• Table 2 are the memory control signals for operation of the example flash memory device illustrated in Figure 2B CSO and DSO are retransmitted versions of CSI and DSI, and Q[n] is an output for providing commands and data
• the commands are received via its D[n] ports and the command signals include the control ports RST#, CE#, CK, CK#, CSI and DSI
• all signals are passed serially from the memory controller 22 to each memory device in series, with the exception of CE# and RST#, which are provided to all the memory devices in parallel
• the serial interface flash memory device of Figure 2B thus receives memory control signals having its own format or protocol, for executing memory operations therein
• Figure 1 B and the serial interface flash memory devices of Figure 2B allows a memory system manufacturer to provide both types of memory systems
• this will likely introduce higher cost to the memory system manufacturer since two different types of memory devices must be sourced and purchased
• Those skilled in the art understand that the price per memory device decreases when large quantities are purchased, hence large quantities are purchased to minimize the cost of the memory system Therefore, while a manufacturer can provide both types of memory systems, it bears the risk of having one type of memory device fall out of market demand due the high market demand of the other This may leave them with purchased supplies of a memory device that cannot be used
• the functional port assignments or definitions of the asynchronous and serial interface flash memory devices are substantially different from each other, and are accordingly, incompatible with each other
• the functional port definitions and sequence, or timing, of sets of signals used for controlling the discrete memory devices is referred to as a protocol or format Therefore the asynchronous and serial flash memory devices operate in response to different memory control signal formats This means that the serial interface flash memory device of Figure 2B cannot be used in a multidrop memory system, and correspondingly, the asynchronous flash memory device of Figure 1 B cannot be used in a serial connected ring topology memory system
• serial interface flash memory devices as shown in Figure 2A and Figure 2B are desirable for their improved performance over the asynchronous flash memory devices of Figures 1 A and 1 B, memory system manufacturers may not wish to dispose of their supplies of asynchronous flash memory devices Furthermore, due to their ubiquitous use in the industry, asynchronous flash memory devices are inexpensive to purchase relative to lesser known alternative flash memory devices such as the serial interface flash memory device of Figure 2A Presently, memory system manufacturers do not have a solution for taking advantage of the performance benefits of serially interconnected devices with minimal cost overhead
• At least some example embodiments provide a high performance composite memory device with a high-speed interface chip or a bridge device in conjunction with discrete memory devices, in a multi-chip package (MCP) or system in package (SIP)
• MCP multi-chip package
• SIP system in package
• the bridge device provides an I/O interface with the system it is integrated within, and receives global memory control signals following a global format, and converts the commands into local memory control signals following a native or local format compatible with the discrete memory devices
• the bridge device thereby allows for re-use of discrete memory devices, such as NAND flash devices, while providing the performance benefits afforded by the I/O interface of the bridge device
• the bridge device can be embodied as a discrete logic die integrated with the discrete memory device dies in the package
• the global format is a serial data format compatible with the serial flash memory device of Figures 2A and 2B
• the local format is a parallel data format compatible with the asynchronous flash memory device of Figures 1A and 2B
• the embodiments of the present invention are not limited to the above example formats, as any pair of memory control signal formats can be used, depending the type of discrete memory devices used in the composite memory device and the type of memory system the composite memory device is used within
• the global format of the memory system can follow the Open NAND Flash Interface (ONFi) standard
• the local format can follow the asynchronous flash memory device memory control signal format
• ONFi Open NAND Flash Interface
• the local format can follow the asynchronous flash memory device memory control signal format
• one specific ONFi standard is the ONFi 2 O Specification
• the global format can follow the asynchronous flash memory device memory control signal format and the local format can follow the ONFi 2 O Specification format
• the ONFi specification is a multi-drop synchronous protocol where data and commands are provided to the compliant memory device via its data input
• FIG. 3A is a block diagram of a composite memory device, according to a present embodiment
• composite memory device 100 includes a bridge device 102 connected to four discrete memory devices 104
• Each of the discrete memory devices 104 can be asynchronous flash memory devices having a memory capacity of 8Gb, for example, but any capacity discrete flash memory device can be used instead of 8Gb devices
• composite memory device 100 is not limited to having four discrete memory devices Any suitable number of discrete memory devices can be included, when bridge device 102 is designed to accommodate the maximum number of discrete memory devices in the composite memory device 100
• Composite memory device 100 has an input port GLBCMDJN for receiving a global command, and an output port GLBCMD_OUT for passing the received global command and read data
• Figure 3B is a schematic illustrating the hierarchy of a global command, according to a present embodiment
• the global command 110 includes global memory control signals (GMCS) 112 having a specific format, and an address header (AH) 114
• GMCS global memory control signals
• AH address header
• the address header 114 includes addressing information used at the system level and the composite memory device level
• This additional addressing information includes a global device address (GDA) 116 for selecting a composite memory device to execute an op code in the memory command, and a local device address (LDA) 118 for selecting a particular discrete device within the selected composite memory device to execute the op code
• GDA global device address
• LDA local device address
• the global command includes all the memory control signals corresponding to one format, and further addressing information which may be required for selecting or controlling the composite memory device or
• bridge device 102 does not execute the op code or access any memory location with the row and address information
• the bridge device 102 uses the global device address 116 to determine if it is selected to convert the received global memory control signals 112 If selected, bridge device 102 then uses the local device address 118 to determine which of the discrete memory devices the converted global memory control signals 112 is sent to
• bridge device 102 includes four sets of local I/O ports (not shown), each connected to a corresponding discrete memory device, as will be discussed later Each set of local I/O ports includes all the signals that the discrete memory device requires for proper operation, and thereby functions as a local device interface
• Read data is provided by any one of a flash memory device 104 from composite memory device 100, or from a previous composite memory device
• the bridge device 102 can be connected to a memory controller of a memory system, or to another bridge device of another composite memory device in a system of serially interconnected devices
• the input port GLBCMDJN and output port GLBCMD_OUT can be package pins, other physical conductors, or any other circuits for transmitting/receiving the global command signals and read data to and from the composite memory device 100, and in particular, to and from bridge device 102
• the bridge device 102 therefore has corresponding connections to the input port GLBCMDJN and the output port GLBCMD_OUT to enable communication with an external controller, such as memory controller 22 of Figure 2A, or with the bridge devices from other composite memory devices in the system
• an external controller such as memory controller 22 of Figure 2A
• FIG. 4 is a block diagram of a bridge device 200 in accordance with an embodiment, which corresponds to the bridge device 102 shown in Figure 3A
• the bridge device 200 has a bridge device input/output interface 202, a memory device interface 204, and a format converter 206
• the format converter 206 includes a command format converter 208 for converting global memory control signals, which include global commands and global command signals in a first format to a second format, and a data format converter 210 for converting data between the first format and the second format
• the command format converter 208 further includes a state machine (not shown) for controlling the discrete memory devices, such as discrete memory devices 104 of Figure 3A in accordance with the second format in response to the global memory control signals in the first format
• the bridge device input/output interface 202 communicates with external devices, such as for example, with a memory controller or another composite memory device
• the bridge device input/output interface 202 receives global commands from a memory controller or another composite memory device in the global format, such as for example in a serial command format
• logic in the input/output interface 202 processes the global device address 116 of the global command 110 to determine if the global command 110 is addressed to the corresponding composite memory device, and processes the local device address 118 in the global command 110 to determine which of the discrete memory devices of the corresponding composite memory device is to receive the converted command, which includes an op code and optional row and column addresses and optional write data
• the command format converter 208 in the format converter 206 converts the global memory control signals 112, which provides the op code and command signals and any row and address information from the global format to the local format, and forwards it to the memory device interface 204 This converted local command
• command format converter 208 can include control logic at least substantially similar to that of a memory controller of a memory system, which is used for controlling the discrete memory devices with memory control signals having a native format
• command format converter 208 may include effectively the same control logic of memory controller 14 of Figure 1A if the discrete memory devices are asynchronous memory devices, such as memory devices 16-1 to 16-4 This means that the control logic in command format converter 208 provides the timing and sequencing of the memory control signals in the local format native to the discrete memory devices
• the data format converter 210 in the format converter 206 converts the data from the global format to the local format, and forwards it to the memory device interface 204
• the bits of read or write data do not require logical conversion, hence data format converter 210 ensures proper mapping of the bit positions of the data between the first data format and the second data format Format converter 206 functions as a data buffer for storing read data from the discrete memory devices or write data received from the bridge device input/output interface 202 Therefore, data width mismatches between the global format and the local format can be accommodated Furthermore, different data transmission rates between the discrete memory devices and the bridge device 200, and the bridge device 200 and other composite memory devices are accommodated due to the buffering functionality of data format converter 210
• command path 212 includes i sets of dedicated local I/O ports LCCMD-i, or channels, connected between each discrete memory device in the composite memory device and the memory device interface 204
• the variable i is an integer number corresponding to the number of discrete memory devices in the composite memory device
• each LCCMD-i channel includes all the ports shown in Figure 1 B and Table 1
• an LCCMD-i channel includes all the ports of an ONFi compliant device, including a clock signal that can be generated in a clock circuit of the command format converter 208
• clock dividers or multipliers can be included to generate clock signals having a desired frequency from a single "master" clock signal
• a global command such as a global read command arriving at the bridge device input/output interface 202 through input port GLBCMDJN
• This global read command includes the global memory control signals that provide an op code and row and column information in the global format, for data to be read out from a discrete memory device 104 connected to the bridge device 200
• the command format converter 208 converts the global read command into the local format compatible with the discrete memory device 104 on which the read data command is to be executed
• the composite memory device can have an assigned address
• the local device address 118 of the global read command is forwarded to the memory device interface 204, and the converted read data command is provided to the discrete memory device addressed by the local device address via
• Data referred to as read data is read from the selected discrete memory device 104 and provided to the data format converter 210 via the same local I/O ports of memory device interface 204 in the local format
• the data format converter 210 then converts the read data from the local format to the global format and provides the read data from the selected discrete memory device 104 to the memory controller through output port GLBCMD_OUT of bridge device interface 202
• Bridge device interface 202 includes internal switching circuitry for coupling either the read data from data format converter 210 or the input port GLBCMDJN to the output port GLBCMDJDUT
• Figure 3A described above is a functional representation of a composite memory device, according to one embodiment
• Figure 5 shows a composite memory device manufactured as a system in package (SIP), which corresponds to the composite memory device shown in Figure 3A
• Figure 5 shows a cross- section of a composite memory device stacked in a package
• the package 300 includes bridge device 302 corresponding to bridge device 102 of Figure 3A, and four discrete memory devices 304 corresponding respectively to discrete memory devices 104 also from Figure 3A In the present embodiment, these devices are fabricated semiconductor chips, or dies
• the bridge device 302 communicates with memory devices 304 via memory device interface 306 in a local format such as the parallel asynchronous NAND format for example
• the bridge device 302 communicates with a memory controller (not shown) or with another composite memory devices' bridge device via the bridge device input/output interface 308 in a global format, such as for example, the previously described serial data format
• the format converter 310 includes the previously mentioned command format converter 208 and data format converter 210 of Figure
• the composite memory device package 300 is referred to as an SIP system, or a multi-chip package (MCP) system
• the package encapsulates bridge device 302 and all four discrete memory devices 304 Local communication terminals, represented by wires 312, connect the I/O ports of each discrete memory device 304 to the memory device interface 306 of bridge device 302
• Each wire 312 represents one channel LCCMD-i carrying all the signals corresponding to the local format
• One example local format is the asynchronous flash memory format including the signals shown in Table 1
• Global communication terminals, represented by wires 314 and 316 connect input port GLBCMD-IN and output port GLBCMD_OUT respectively, to package leads 318 via optional package substrate 320
• the physical arrangement of bridge device 302 and discrete memory devices 304 relative to each other depends on the position of the bond pads of discrete memory devices 304 and the position of the bond pads of the bridge device 302
• each discrete memory device 304 has its data bond pads connected directly to the bond pads of the bridge device 302
• the data bond pads of each discrete memory device 304 forms a channel, which can be connected to dedicated corresponding data bond pads of the bridge device 302
• each discrete memory device 304 is connected to the bridge device 302 through conductive tracks formed in the package substrate 320 More specifically, the bond wires 312 are electrically connected to bond wires 314 through such conductive tracks formed in the substrate 320
• each discrete memory device 304 is electrically connected to corresponding data bond pads of the bridge device 302 via a respective channel such as in the embodiment of Figure 5A
• the bridge device 302 includes only one set of data bond pads that are connected in parallel to the data bond pads of each discrete memory device 304 Therefore, there is one channel shared between all the discrete memory devices 304
• the conductive tracks formed in the substrate 320 can be coupled in parallel to the bridge device 302
• the discrete memory devices 304 are placed with their bond pads facing in the upwards direction and stacked upon each other in a staggered step pattern for exposure so as not to obstruct the bond pads of the devices which are located proximate to an edge of the chip
• Bridge device 302 is placed with its bond pads facing in the upwards direction, and is stacked on the upper-most discrete memory device 304 of the stack
• Other configurations are possible, depending on the placement of the discrete memory device bond pads, and different communication terminals can be used instead of bond wires
• wireless communication via inductive coupling technology can be used, or through silicon via (TSV) interconnection can be used instead of bond wires
• TSV through silicon via
• FIG. 6 shows another embodiment of the composite memory device of Figure 3A, formed as a module or on a printed circuit board (PCB)
• composite memory device 400 includes a bridge device 402 and four discrete memory devices 404
• the bridge device 402 and the discrete memory devices 404 are packaged devices, meaning that each encapsulates a semiconductor die and has package leads bonded to preformed conductive tracks in the PCB
• the bridge device 402 is connected to individual discrete memory devices 404 via the conductive tracks organized as dedicated local I/O ports or channels LCCMD-i for each memory device 404
• the module or the PCB including the bridge device includes an input port GLBCMDJN, for receiving global commands, and an output port GLBCMD_OUT for providing read data and global commands received at the input port
• These input and output ports can be connected to a controller (not shown) or to other composite memory devices
• the individual discrete memory devices 404 can be each connected directly to bridge device 402, or alternately the individual memory devices
• the composite memory device embodiments of Figures 5A, 5B and Figure 6 can be used in a memory system, such as the serial memory system of Figure 2A, according to another embodiment
• the memory system 500 of Figure 7 is similar to the serial memory system 20 of Figure 2A
• Memory system 500 includes a memory controller 502 and composite memory devices 504-1 to 504-j, where j is an integer number
• the individual composite memory devices 504-1 - 504-j are serially interconnected with the memory controller 502
• composite memory device 504-1 is the first composite memory device of memory system 500 as it is connected to an ouput port Sout of memory controller 410
• memory device 504-n is the last device as it is connected to an input port Sm of memory controller 410
• Composite memory devices 504-2 to 504-7 are then intervening serially connected memory devices connected between the first and last composite memory devices
• the Sout port provides a global command in a global format
• the Sin port receives read data in the global format, and the global command as it propagates through all the
• each of the composite memory devices shown in Figure 7 is similar to the composite memory device 100 shown in Figure 3A
• Each of the composite memory devices has a bridge device 102 and four discrete memory devices 104
• each bridge device 102 in each of the composite memory device is connected to respective discrete memory devices 104, and to either the memory controller 502 and/or a previous or subsequent composite memory device in the serial-ring topology or serial interconnection configuration
• the function of each composite memory device 504-1 to 504-j is the same as previously described for the embodiments of Figure 3A and Figure 4
• each composite memory device is assigned a unique global device address
• This unique global device address can be stored in a device address register of the bridge device 102, and more specifically in a register of the input/output interface 202 of the bridge device block diagram shown in Figure 4
• This address can be assigned automatically during a power up phase of memory system 500 using a device address assignment scheme, as described in commonly owned U S Patent Publication No 20080192649 entitled "Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection"
• each composite memory device 504 can include a discrete device register for storing information about the number of discrete memory devices in each composite memory device 504
• the memory controller can query each discrete device register and record the number of discrete memory devices within each composite memory device Hence the memory controller can selectively address individual discrete memory devices 104 in each composite memory device 504 of memory system 500
• memory system 500 is a serially connected memory system similar to the system shown in Figure 2, and each of the discrete memory devices 104 are assumed to be asynchronous NAND flash memory devices Therefore the bridge devices 102 in each of the composite memory devices 504-1 to 504-j are designed for receiving global commands in a global format issued by memory controller 502, and converting them into a local format compatible with the NAND flash memory devices It is further assumed that memory system has powered up and addresses for each composite memory device have been assigned
• the memory controller 502 issues a global command from its Sout port, which includes a global device address 116 corresponding to composite memory device 504-3
• the first composite memory device 504-1 receives the global command, and its bridge device 102 compares its assigned global device address to that in the global command Because the global device addresses mismatch, bridge device 102 for composite memory device ignores the global command and passes the global command to the input port of composite memory device 504-2 The same action occurs in composite memory device 504-2 since its assigned global device address mismatches the one in the global command Accordingly the global command is passed to composite memory device 504-3
• bridge device 102 of composite memory device 504-3 determines a match between its assigned global device address and the one in the global command Therefore, bridge device 102 of composite memory device 504-3 proceeds to convert the global memory control signals into the local format compatible with the NAND flash memory devices The bridge device then sends the converted command to the NAND flash memory device selected by the local device address 118, which is included in the global command The selected NAND flash device then executes the operation corresponding to the local memory control signals it has received
• bridge device 102 of composite memory device 504-3 While bridge device 102 of composite memory device 504-3 is converting the global command, it passes the global command to the next composite memory device The remaining composite memory devices ignore the global command, which is eventually received at the Sin port of memory controller 502 If the global command corresponds to a read operation, the selected NAND flash memory device of composite memory device 504-3 provides read data to its corresponding bridge device 102 in the local format Bridge device 102 then converts the read data into the global format, and passes it through its output port to the next composite memory device The bridge devices 102 of all the remaining composite memory devices pass the read data to the Sin port of memory controller 502 Those skilled in the art should understand that other global commands may be issued for executing the read operation, all of which are converted by the bridge device 102 of selected composite memory device 102
• the global command is propagated to all the composite memory devices in memory system 500
• the bridge devices 102 include additional logic for inhibiting the global command from propagating to further composite memory devices in the memory system 500 More specifically, once the selected composite memory device determines that the global device is addressed to it, its corresponding bridge device 102 drives its output ports to a null value, such as a fixed voltage level of VSS or VDD for example Therefore, the remaining unselected composite memory devices conserve switching power since they would not execute the global command Details of such a power saving scheme for a serially connected memory system are described in commonly owned U S Patent Publication No 20080201588 entitled "Apparatus and Method for Producing Identifiers Regardless of Mixed Device Type in a Serial Interconnection", the contents of which are incorporated by reference in their entirety
• each composite memory device 504-1 to 504-N having the same type of discrete memory devices therein, such as for example asynchronous NAND flash memory devices
• a homogeneous memory system because all the composite memory devices are the same
• a heterogeneous memory system is possible, where different composite memory devices have different types of discrete memory devices
• some composite memory devices include asynchronous NAND flash memory devices while others can include NOR flash memory devices
• all the composite memory devices follow the same global format, but internally, each composite memory device has its bridge device 200 designed to convert the global format memory control signals to the local format memory control signals corresponding to the NOR flash memory devices or NAND flash memory devices
• a single composite memory device could have different types of discrete memory devices
• a single composite memory device could include two asynchronous NAND flash memory devices and two NOR flash memory devices
• This "mixed” or “heterogeneous” composite memory device can follow the same global format described earlier, but internally, its bridge device can be designed to convert the global format memory control signals to the local format memory control signals corresponding to the NAND flash memory devices and the NOR flash memory devices
• Such a bridge device can include one dedicated format converter for each of the NAND flash memory device and the NOR flash memory device, which can be selected by previously described address information provided in the global command
• the address header 114 includes addressing information used at the system level and the composite memory device level
• This additional addressing information includes a global device address (GDA) 116 for selecting a composite memory device to execute an op code in the memory command, and a local device address (LDA) 118 for selecting a particular discrete device within the selected composite memory device to execute the op code
• GDA global device address
• LDA local device address
• the bridge device can have a selector that uses LDA 118 to determine which of the two format converters the global command should be routed to
• composite memory devices can be used in a multi-drop configured memory system, such as the multi-drop memory system shown in Figure 1A
• each composite memory device is connected in parallel to each other and the memory controller via a single channel, such as channel 18 of
• the bridge device of each composite memory device is configured to receive commands and data through data input/output ports, such as data input/output ports I/O[n] of Figure 1 B, while providing read data through the same data input/output ports
• the bridge device of each composite memory device is configured to receive asynchronous control signals or synchronous control signals
• the memory controller provides a source synchronous clock signal that is received by the bridge devices of each composite memory device
• the bridge devices are configured to receive ONFi standard commands, which can be converted by the bridge devices into a format compatible with the discrete memory devices
• the bridge device is configured to receive write data and to provide read data at a frequency greater than the maximum rated frequency of the discrete memory devices
• the discrete memory devices selected for use within the composite memory device they may not be able to provide its read data fast enough to the bridge device in real time so that the bridge device can output the read data at its higher data rate
• the bridge device includes virtual page buffers to temporarily store at least a portion of a page of data read from the page buffer of a discrete memory device, or to be written to the page buffer of a discrete memory device
• these virtual page buffers include memory for storing either read data from the discrete memory devices or write data to be written to the discrete memory devices
• data format converter 210 includes such memory, which
• FIG 8 is a block diagram of a composite memory device 600 illustrating the relationship between page buffers of four NAND flash memory devices and the memory of a bridge device
• Composite memory device 600 is similar to composite memory device 100 shown in Figure 3A, and includes four NAND flash memory devices 602 in the example embodiment of Figure 8, and a bridge device 604
• the bridge device 604 is shown as a simplified version of bridge device 400 of Figure 4, where only the memory 606 is shown
• the other components of bridge device 400 are omitted from Figure 8, but should be understood to be present in order to ensure proper operation of bridge device 600
• memory 606 is logically organized into groups that correspond with the page buffer of each of the four NAND flash memory device 602
• Each NAND flash memory device 602 has a memory array organized as two planes 608 and 610, labeled "Plane 0" and "Plane 1 " respectively While not shown, row circuits drive wordhnes that extend horizontally through each of planes 608 and 610, and page buffers 612 and 614 which may include column access and sense circuits, are connected to bitlines that extend vertically through each of planes 608 and 610 The purpose and function of these circuits are well known to those skilled in the art For any read or write operation, one logical wordhne is driven across both planes 608 and 610, meaning that one row address drives the same physical wordhne in both planes 608 and 610 In a read operation, the data stored in the memory cells connected to the selected logical wordline are sensed and stored in page buffers 612 and 614 Similarly, write data is stored in page buffers 612 and 614 for programming to the memory cells connected to the selected logical wordline
• Memory 606 of bridge device 604 is divided into logical or physical sub-memories 616 each having at least the same storage capacity of a page buffer 612 or 614
• a logical sub- memory can be an allocated address space in a physical block of memory while a physical sub-memory is a distinctly formed memory having a fixed address space
• the sub-memories 616 are grouped into memory banks 618, labeled BankO to Bank3, where the sub-memories 616 of a memory bank 618 are associated with only the page buffers of one NAND flash memory device 602
• sub-memories 616 of a memory bank 618 are dedicated to respective page buffers 612 and 614 of one NAND flash memory device 602
• read data in page buffers 612 and 614 are transferred to sub-memories 616 of the corresponding memory bank 618
• write data stored in sub-memories 616 of a memory bank 618 is transferred to the page buffers 612 and 6
• the present example of Figure 8 has NAND flash devices 602 with at total of 8KB of page buffer space, organized as two separate 4KB page buffers Each separate 4KB page buffer is coupled to the bitlines of a respective plane, such as plane 608 or plane 610 for example Those skilled in the art understand that page buffer sizes have gradually increased as the overall capacity of NAND flash memory devices has increased, thus future NAND flash devices may have even larger page buffers
• the larger page buffers allow for faster overall read and program operations because the core read and program times of the NAND flash memory device is substantially constant, and independent of the page buffer size which is well known to persons skilled in the art
• a larger page buffer enables a relatively constant burst read of twice as much read data before another core read operation is needed to access another page of data stored in a different row of the memory array Similarly, twice as much write data can be programmed to the memory array at the same time before another page of write data needs to be loaded into the page buffer Therefore, larger page buffers are suited for
• the total core read time includes the NAND flash memory device core read time, earlier referred to as Tr, plus a transfer time Ttr
• the transfer time Ttr is the time required for the NAND flash memory device to output, or read out, the contents of the page buffers 612 and 614 so that they can be written to corresponding sub-memories 616 of one memory bank 618
• the total core program time includes a program transfer time Ttp plus the NAND flash memory device core program time earlier referred to as Tpgm
• the program transfer time Ttp is the time required for the bridge device 608 to output, or read out, the contents of sub-memories 616 of one memory bank 618 so that they can be loaded into corresponding page buffers 612 and 614 of a NAND flash memory device 602 prior to a programming operation
• the data can be stored across different NAND flash memory devices and concurrently operated to mask core operations of one NAND flash memory device while data corresponding to another NAND flash memory device 602 is being output
• the transfer time Ttr in such scenarios may not be acceptable for certain applications due to its significant contribution to the total core read time of the composite memory device
• Such applications include SSD where read operations should be performed as fast as possible
• the transfer time Ttr for transferring the entire contents to the sub- memories 616 is directly dependent on the page buffer size
• the transfer time Ttr of the composite memory device can be minimized by configuring the sub-memories 616 of a memory bank 618 to have a virtual maximum page size, referred to as a virtual page size, that is less than the maximum physical size of the page buffer of a NAND flash memory device within the composite memory device
• the bridge device 604 issues read commands where only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the corresponding sub-memories 616 This segment of the page buffer is referred to as a page segment
• Figures 9A to 9C illustrates how data corresponding to a set virtual page size is read from a discrete memory device, such as a flash memory device, is read out of a composite memory device, according to a present embodiment
• Figures 9A to 9C shows a composite memory device 700 having one fully shown first NAND flash memory device 702, a portion of a second NAND flash memory device 704, and a portion of bridge device 706
• the NAND flash memory devices of this example have a single plane 708 having bitlines connected to a single page buffer 710
• the shown portion of bridge device 706 includes a first sub-memory 712, a second sub-memory 714, and a bridge device input/output interface 716
• First sub- memory 712 corresponds to a first bank, which is associated with first NAND flash memory device 702 while second sub-memory 714 corresponds to a second bank, which is associated with second NAND flash memory device 704
• First sub- memory 712 corresponds to a first bank, which
• bridge device 706 has received global memory control signals representing a read operation to access data stored in first NAND flash memory device 702, and has encoded and provided the appropriate local memory control signals to first NAND flash memory device 702
• first NAND flash memory device 702 activates a row or wordlme 718 selected by address information in the local memory control signals
• FIG 9B when the wordlme 718 is activated, or driven to a voltage level effective for accessing the stored data of the memory cells connected to it, a current or voltage generated on the bitlines connected to each accessed memory cell is sensed by sense circuitry within page buffer 710
• NAND flash memory device 702 outputs data stored within a specific range of bit positions of page buffer 710 to bridge device 706, and in particular to first sub-memory 712 This data output process is executed at up to the maximum rated speed or
• NAND flash memory device 702 a burst read command including column addresses corresponding to this specific range of bit positions is provided by bridge device 706 automatically once NAND flash memory device 702 reports or signals to bridge device 706 that the read data from the selected row 718 is stored in page buffer 710, usually by way of a ready/busy signal
• the column addresses are determined based on the configured virtual page size for first sub-memory 712
• the data stored in first sub-memory 712 is then output through output data ports of composite memory device 700 via bridge device input/output interface 716 at the higher speed or data rate
• an output data port includes pins or leads corresponding to the Q[n] data output port previously shown in Table 2
• first sub-memory 712 of the bridge device 706 can be configured via a recognized command to have any one of preset virtual page sizes
• the page buffer 710 of the corresponding NAND flash memory device is logically subdivided into equal sized page segments corresponding to the configured virtual page size
• Figures 10A to 10D are schematic representations of a NAND flash memory device page buffer 750 with differently sized page segments based on a configured virtual page size It is noted that the page segments represent a virtual address space in page buffer 750 In the present examples of Figures 1 OA to 10D, the NAND flash page buffer, and the sub-memory of the bridge device, both have a maximum 4K physical size.
• the virtual page size is set to the maximum, or full 4K size such that there is only one page segment 752.
• the VPS is set to 2K, resulting in two 2K page segments 754.
• the VPS is set to 1 K, resulting in four 1 K page segments 756.
• the VPS is set to 612 bytes (B), resulting in eight page segments 758 that are 612B in size.
• Those skilled in the art will understand that even smaller sized VPS and corresponding page segments are possible, and that the total number of page segments depends on the maximum size of the NAND flash memory device page buffer 750.
• each page segment is addressable by a virtual page address provided in the global command to the bridge device. For example, two address bits are used to select one of four page segments 756 in Figure 10C. Once selected, the desired data may not occupy all bit positions in the selected page segment of page buffer 750. Thus a virtual column address is used to select the first bit position within the selected page segment where read data is to be read out, typically in a burst read operation. Table 3 below summarizes example addressing schemes based on the example page segments shown in Figures 10A to 10D.
• Example addressing schemes are shown in Table 3 by example, but those skilled in the art should understand that different addressing schemes can be used depending on the size of the page buffer of the NAND flash memory device
• each addressing scheme includes a first number of bits for addressing two or more page segments, and a second number of bits for addressing a column in the selected page segment
• the first number of bits is referred to as a virtual page address (VPA)
• the second number of bits is referred to as a virtual column address (VCA)
• VPS configuration of each sub-memory or bank of sub-memories is known to the memory controller or other host system that requests read data and provides write data to the composite memory device Therefore a virtual address for reading a page segment from the page buffer of the NAND flash memory device is provided in the global command to the composite memory device with a corresponding addressing scheme for accessing a particular NAND flash memory device therein
• VPS configuration of each sub-memory or bank of sub-memories is known to the memory controller or other host system that requests
• Figure 1 1 is a flow chart outlining a method for reading data from a composite memory device according to a present embodiment
• Figure 12 is a flow chart outlining a method for writing data to a composite memory device
• the bridge device receives a global page read command to read data from a specific virtual page (VP) from a physical page (PP) of the selected discrete memory device
• VP virtual page
• PP physical page
• X a specific virtual page all the virtual pages that make up the physical page
• the bridge device converts the global read command into a local read command, and issues it to the selected discrete memory device
• the bridge device clears its virtual page buffers, which can include setting all their states
• step 900 a global page program command is received by the bridge device
• step 906 the bridge device issues another burst data load command to the discrete memory device This command transfers data corresponding to another virtual page, such as
• the bridge device 200 can be designed to receive global memory control signals having one format, for providing local memory control signals having the same format to the discrete memory devices
• such a composite memory device is configured to receive memory control signals that are used to control the discrete memory devices
• Such a configuration allows multiple discrete memory devices to each function as a memory bank operating independently of the other discrete memory device in the composite memory device Therefore, each discrete memory device can receive its commands from the bridge device 200, and proceed to execute operations substantially in parallel with each other This is also referred to as concurrent operations
• the design of bridge device 200 is therefore simplified, as no command conversion circuitry is required
• the previously described embodiments illustrate how discrete memory devices in a composite memory device can respond to a foreign command format This is achieved through the bridge device that converts the received global command into a native command format compatible with the discrete memory devices
• a serial command format can be converted into an asynchronous NAND flash format
• the embodiments are not limited to these two formats, as any pair of command formats can be converted from one to the other

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