WO2010023846A1 - Substrat semi-conducteur et son procédé de fabrication - Google Patents

Substrat semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2010023846A1
WO2010023846A1 PCT/JP2009/003960 JP2009003960W WO2010023846A1 WO 2010023846 A1 WO2010023846 A1 WO 2010023846A1 JP 2009003960 W JP2009003960 W JP 2009003960W WO 2010023846 A1 WO2010023846 A1 WO 2010023846A1
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substrate
plane
surface portion
gan
crystal growth
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PCT/JP2009/003960
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Japanese (ja)
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只友一行
岡田成仁
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国立大学法人山口大学
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Priority to JP2010526523A priority Critical patent/JP5392855B2/ja
Publication of WO2010023846A1 publication Critical patent/WO2010023846A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02642—Mask materials other than SiO2 or SiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Definitions

  • the present invention relates to a semiconductor substrate, a manufacturing method thereof, an electronic device using the same, and a semiconductor light emitting element.
  • the piezoelectric polarization generated by the compressive strain applied to the InGaN quantum well layer is superimposed on the InGaN quantum well layer.
  • a large internal polarization electric field is generated in the c-axis direction.
  • the spontaneous polarization works in the ⁇ c plane direction and the piezo polarization works in the + c plane direction, but the piezo polarization is overwhelmingly large in the InGaN well layer. Due to the influence, problems such as a decrease in light emission efficiency and a shift in peak wavelength of light emission accompanying an increase in necessary injection current occur.
  • the cause of this problem is the quantum confined Stark effect, in which the wave function of electrons and holes in the quantum well layer is spatially separated due to the polarization electric field and the emission probability is drastically reduced. : QCSE).
  • FIG. 3 is an explanatory diagram showing crystal growth of GaN on the sapphire substrate of Embodiment 1.
  • A)-(e) is explanatory drawing which shows the manufacturing method of the semiconductor light-emitting device of Embodiment 1.
  • FIG. (A)-(e) is explanatory drawing which shows the relationship between the groove side surface of the ditch
  • (A) And (b) is an expanded sectional view of the ditch
  • FIG. 6 is a cross-sectional view of a sapphire substrate of Embodiment 2.
  • FIG. 6 is a cross-sectional view of a semiconductor substrate according to Embodiment 2. It is sectional drawing of the sapphire substrate of Embodiment 3.
  • FIG. 10 is a cross-sectional view showing a sapphire substrate according to a modification of Embodiment 3.
  • FIG. 10 is a cross-sectional view showing a sapphire substrate according to another modification of Embodiment 3.
  • FIG. 6 is a cross-sectional view of a semiconductor substrate according to Embodiment 3.
  • FIG. (A)-(e) is explanatory drawing which shows the manufacturing method of the semiconductor light-emitting device of Embodiment 3.
  • FIG. It is a graph which shows the relationship between OFF angle (theta) 2 and a full width at half maximum. It is a schematic diagram which shows a GaN crystal.
  • Embodiment 1 A method for manufacturing the semiconductor light emitting device 10 according to Embodiment 1 will be described with reference to FIGS.
  • the substrate main surface portion 12a is covered with the crystal growth blocking layer 13 on the substrate surface 12, and the surface exposure is different from that of the substrate main surface portion 12a.
  • the sapphire substrate 11 on which the crystal growth surface portion 12b is formed is used.
  • the sapphire substrate 11 has an overwhelmingly low cost compared to the GaN substrate, and has a device performance that considers light transmittance over the Si substrate.
  • Examples of the crystal growth prevention layer 13 that covers the substrate main surface portion 12a include, for example, oxide films and nitride films such as Si, Ti, Ta, and Zr, specifically, SiO 2 films, SiN x films, and SiO 2 films. An xN y film, a TiO 2 film, a ZrO 2 film, and the like can be given.
  • the crystal growth preventing layer 13 has a thickness of 0.01 to 3 ⁇ m.
  • the crystal growth blocking layer 13 can be formed on the cleaned sapphire substrate 11 by a method such as vacuum deposition, sputtering, or CVD (Chemical Vapor Deposition).
  • the crystal growth blocking layer 13 may be composed of a single layer or a plurality of layers.
  • the sapphire substrate 11 having the configuration 2 has an a-plane main surface portion 12a, and the extending direction of the U-shaped concave groove 14 is the m-plane orientation, that is, the m-axis. What is the direction.
  • the c-plane is exposed as the side surface of the groove 14 serving as the crystal growth surface portion 12b.
  • the sapphire substrate 11 having the configuration 5 has a c-plane as the substrate main surface portion 12a and the extending direction of the U-shaped groove 14 having a U-shaped cross section. What is the direction.
  • the m-plane is exposed as the side surface of the groove 14 serving as the crystal growth surface portion 12b.
  • the substrate main surface portion 12a is a surface in which the a-plane and c-plane are inclined by 45 ° around the m-axis, that is, miscut with an off-angle of 45 °.
  • An example is a miscut substrate in which the direction in which the groove and the U-shaped concave groove 14 extend is the m-plane orientation, that is, the m-axis direction.
  • a surface obtained by inclining the c-plane around the m-axis by 45 ° in the a-axis direction is exposed as the side surface of the groove 14 serving as the crystal growth surface portion 12b.
  • the concave groove 14 may have a configuration in which one of both side surfaces is exposed and the other is coated so as to prevent GaN crystal growth, in addition to the configuration in which both side surfaces are exposed. Since sapphire has a crystal structure without + c and ⁇ c planes, there is a possibility that GaN having the same polarity will grow when crystals are grown from both sides of the groove, in which case those GaN Thus, an inversion domain (a kind of crystal defect) whose crystal orientation is reversed at the meeting point is formed. However, in the case of a configuration in which one of both side surfaces is exposed and the other is covered, this inversion domain can be completely eliminated.
  • the side surface of the ridge 14 ′ formed so as to extend to the substrate surface 12 of the sapphire substrate 11 can also be mentioned.
  • the top surface of the ridge as well as the substrate main surface portion 12 a on the base end side of the ridge 14 ′ are covered with the crystal growth blocking layer 13.
  • the protrusion 14 ′ may have a configuration in which one of both side surfaces is exposed and the other surface is coated so as to prevent crystal growth of GaN.
  • GaN is grown from the crystal growth surface portion 12b on the substrate surface 12 of the sapphire substrate 11 prepared as described above, whereby the normal direction of the substrate main surface portion 12a is obtained.
  • the u-GaN layer 15 is formed so as to grow to obtain a semiconductor substrate S, an n-type GaN layer 16, a multiple quantum well layer 17 as a light emitting layer, and a p-type GaN layer 18 are sequentially formed thereon. To do.
  • metalorganic vapor phase epitaxy Metal-Organic-Vapor-Phase Epitaxy: MOVPE
  • molecular beam epitaxy Molecular-Beam Epitaxy: MBE
  • hydride vapor phase epitaxy Hydride-Vapor-Phase
  • MOVPE Metal-Organic-Vapor-Phase Epitaxy
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • metal organic vapor phase epitaxy is the most common.
  • Examples of the carrier gas include H 2 and N 2 .
  • An example of the group V element supply source is NH 3 .
  • Examples of the group III element supply source include trimethylgallium (TMG), trimethylindium (TMI), trimethylaluminum (TMA), and the like.
  • Examples of the n-type doping element supply source include SiH 4 (silane), Si 2 H 6 (disilane), and GeH 4 (germane).
  • Examples of the p-type doping element supply source include Cp 2 Mg (biscyclopentadienyl magnesium).
  • ⁇ Formation of u-GaN layer> First, after setting the sapphire substrate 11 on the quartz tray so that the substrate surface 12 faces upward, the sapphire substrate 11 is heated to 1050 to 1150 ° C. and the pressure in the reaction vessel is set to 10 to 100 kPa. The sapphire substrate 11 is thermally cleaned by circulating H 2 as a carrier gas in a flow channel installed inside and maintaining that state for several minutes.
  • the temperature of the sapphire substrate 11 is set to 1050 to 1150 ° C.
  • the pressure in the reaction vessel is set to 10 to 100 kPa
  • the carrier gas H 2 is circulated in the reaction vessel at a flow rate of 10 L / min.
  • a group element supply source (NH 3 ) and a group III element supply source (TMG) are flowed so that the respective supply amounts are 0.1 to 5 L / min and 50 to 150 ⁇ mol / min.
  • the substrate main surface portion 12a of the substrate surface 12 of the sapphire substrate 11 is covered with the crystal growth blocking layer 13, no GaN crystal growth occurs.
  • the ungrown GaN is heteroepitaxially grown on the crystal growth surface portion 12b exposed to the surface starting from the crystal growth surface portion 12b.
  • growth of the GaN layer proceeds in the normal direction of the substrate main surface portion 12a, and as shown in FIG. 7A, a u-GaN layer (undoped GaN layer) 15 is formed on the sapphire substrate 11.
  • a semiconductor substrate S is obtained.
  • the thickness of the u-GaN layer 15 grown on the crystal growth blocking layer 13 is about 2 to 20 ⁇ m.
  • the u-GaN layer 15 when the crystal growth surface portion 12 b is formed by the side surface of the groove 14 and a plurality of grooves 14 are formed so as to extend in parallel at intervals, the u-GaN layer 15 has grown from each groove 14. It is constituted by an aggregate of a plurality of band-shaped GaN crystals or by an integrated body in which band-shaped GaN crystals grown from the respective concave grooves 14 are linked together.
  • the pressure in the reaction vessel (from a reduced pressure state ( ⁇ 10 kPa) to a normal pressure state (100 kPa)), crystal growth temperature, material flow rate It is preferable to optimize the crystal growth conditions such as and / or take a sufficiently long crystal growth time.
  • the crystal growth surface portion 12b is constituted by the side surfaces of the concave grooves 14, the concave grooves 14 may be filled by crystal growth of GaN, or voids may remain.
  • the u-GaN layer 15 has various plane orientations depending on the configuration of the sapphire substrate 11.
  • the sapphire a-axis and the GaN c-axis are parallel to each other and the sapphire c-axis and the GaN m-axis are parallel on the crystal growth surface portion 12b which is the a-plane.
  • Crystal orientation-related GaN grows. Therefore, on the substrate surface 12 of the sapphire substrate 11, m-plane GaN grows in a crystal orientation relationship in which the c-axis of sapphire and the m-axis of GaN are parallel, and thus the main surface of the u-GaN layer 15.
  • the plane parallel to the substrate main surface portion 12a (hereinafter the same) is the m plane.
  • the sapphire c-axis and the GaN c-axis are parallel on the c-plane crystal growth surface portion 12b, and the sapphire a-axis and the GaN m-axis are parallel.
  • GaN crystal grows. Therefore, on the substrate surface 12 of the sapphire substrate 11, m-plane GaN grows, so that the main surface of the u-GaN layer 15 is the m-plane.
  • the side surface of the concave groove 14 is a c-plane miscut in the a-axis direction, but the c-axis of the sapphire substrate 11 and the c-axis of GaN are similar to those of the sapphire substrate 11 of the configuration 2.
  • GaN grows in a crystal orientation relationship in which the a-axis of sapphire and the m-axis of GaN are parallel to each other, and m-plane GaN grows on the substrate surface 12 of the sapphire substrate 11.
  • the main surface of the -GaN layer 15 is an m-plane.
  • the GaN crystal has a crystal structure in which a Ga atom plane containing only Ga atoms and an N atom plane containing only N atoms are alternately stacked in the c-axis direction as shown in FIG.
  • the c-axis direction having the spontaneous polarization of the u-GaN layer 15 is not the layer thickness direction but the layer in-plane direction.
  • the main surface 15 is a nonpolar surface (m-plane) having no polarity in the layer thickness direction.
  • m-plane nonpolar surface
  • the u-GaN layer 15 is polarized in various layer thickness directions depending on the GaN crystal growth mode on the substrate surface 12 of the sapphire substrate 11.
  • the sapphire substrate 11 having configuration 6 GaN grows in a crystal orientation relationship in which the c-axis of sapphire and the c-axis of GaN are parallel, and the a-axis of sapphire and the m-axis of GaN are parallel.
  • the main surface of the u-GaN layer 15 is a semipolar surface intermediate between the c-plane and the m-plane.
  • GaN grows in the c-axis direction, but the main surface of u-GaN layer 15 is a semipolar surface with better crystallinity.
  • the GaN crystal growth surface can be manipulated by setting the crystal main surface portion 12a of the substrate surface 12 of the sapphire substrate 11 and the crystal growth surface portion 12b exposed to the substrate surface 12. It is possible to control the polarization state of GaN formed on 12.
  • the degree of freedom of the crystal main surface portion 12 a of the substrate surface 12 and the crystal growth surface portion 12 b exposed to the substrate surface 12 is higher than that of the Si substrate, and thus can be adopted in the u-GaN layer 15.
  • the polarization state also has a high degree of freedom.
  • the (11-22) plane is faceted.
  • the u-GaN layer 15 which is a surface is obtained.
  • the angle formed by the (11-22) plane with respect to the substrate main surface portion 12a is -0.8 ° (the direction approaching the c-plane of GaN is positive, the same applies hereinafter). Accordingly, a facet surface is obtained by using a miscut substrate of the sapphire substrate 11 in which the substrate main surface portion 12a is a surface having an off angle with respect to the (10-12) surface so as to cancel the angle (11 ⁇ ). 22)
  • the u-GaN layer 15 whose surface is the main surface can be obtained.
  • the description of the Miller index using parentheses also means general notation.
  • the (10-11) plane grows as a facet plane.
  • the u-GaN layer 15 whose (10-11) plane is facet is obtained.
  • the angle formed by the (10-11) plane with respect to the substrate main surface portion 12a is ⁇ 0.74 °, and the u-GaN layer 15 having the (10-11) plane as the main surface can be obtained.
  • a miscut substrate of the sapphire substrate 11 that cancels an angle formed with respect to the substrate main surface portion 12a of the (10-11) plane, a high surface where the (10-11) surface which is the facet surface is the main surface.
  • a quality u-GaN layer 15 can be obtained.
  • the u-GaN layer 15 in which the (10-12) plane is a facet plane is obtained under the growth conditions in which the (10-12) plane grows as a facet plane.
  • the angle formed by the (10-12) plane with respect to the substrate main surface 12a is + 18.03 °.
  • u-GaN whose facet surface (10-12) surface is the main surface.
  • Layer 15 is obtained. Further, by using the miscut substrate or the sapphire substrate 11 which is not the miscut substrate, the u-GaN layer 15 obtained by the growth is surface-polished so as to be parallel to the substrate main surface portion 12a, thereby having an off angle.
  • a (10-11) plane GaN template can be obtained.
  • the (10-11) plane grows as a facet plane.
  • the u-GaN layer 15 whose (10-11) plane is a facet plane is obtained.
  • the angle formed by the (10-11) plane with respect to the substrate main surface portion 12a is + 7.93 °. Therefore, by using a miscut substrate of the sapphire substrate 11 that cancels out the angle formed with respect to the substrate main surface portion 12a of the (10-11) plane, the (10-11) surface which is the facet surface is the main surface u.
  • a GaN layer 15 can be obtained.
  • u-GaN so 15 having the (10-12) plane as a facet plane is obtained.
  • the angle formed by the (10-12) plane with respect to the substrate main surface 12a is + 26.7 °. Therefore, similarly to the growth of the (10-11) plane, by using a miscut substrate of the sapphire substrate 11 that cancels the angle formed with respect to the substrate main surface portion 12a of the (10-12) plane, the facet plane (10 -12) The u-GaN layer 15 whose surface is the main surface is obtained.
  • the grown u-GaN layer 15 is subjected to surface polishing so as to be parallel to the substrate main surface portion 12a (10-11).
  • a GaN template having a plane GaN off of 7.93 ° can be obtained.
  • the (10-11) plane is the facet plane.
  • a GaN layer 15 is obtained.
  • the angle formed by the (10-11) plane with respect to the substrate main surface portion 12a is + 17.66 °. Therefore, by using a miscut substrate of the sapphire substrate 11 that cancels the angle, the u-GaN layer 15 whose (10-11) plane as the facet plane is the main surface can be obtained.
  • the (11-21) plane is a facet plane and the u-GaN layer 15 whose (11-21) plane is a plane inclined by ⁇ 0.5 ° with respect to the substrate main surface portion 12a is obtained.
  • a miscut substrate of the sapphire substrate 11 that cancels out the angle of ⁇ 0.5 °, it is possible to obtain a u-GaN layer 15 having a higher-quality (10-21) plane as a main surface.
  • the growth conditions of the u-GaN layer 15 in which the (20-21) plane is the facet plane are as follows.
  • u-GaN which is a (20-21) facet surface having an angle formed with respect to the substrate main surface portion 12a of + 4.53 ° is obtained. Therefore, by using a miscut substrate of the sapphire substrate 11 that cancels the angle, the u-GaN layer 15 whose (20-21) plane is the main surface can be obtained.
  • Tables 1 to 4 show the angle between the plane orientation of the sapphire substrate 11 and the c plane, the angle between the plane orientation of GaN and the c plane, and the deviation of the orientation of the sapphire substrate with the desired plane orientation of GaN and various plane orientations. Shown together.
  • n-type GaN layer The pressure in the reaction vessel is 10 to 100 kPa, and the carrier gas H 2 is in the reaction vessel at a flow rate of 5 to 15 L / min (hereinafter, the gas flow rate is a value in a standard state (0 ° C., 1 atm)).
  • a group V element supply source (NH 3 ), a group III element supply source 1 (TMG), and an n-type doping element supply source (SiH 4 ) are supplied in amounts of 0.1 to 5 L, respectively. / Min, 50 to 150 ⁇ mol / min, and 1 to 5 ⁇ 10 ⁇ 3 ⁇ mol / min.
  • the n-type GaN is epitaxially grown in the same plane direction as the u-GaN layer 15 continuously with the u-GaN layer 15 to form the n-type GaN layer 16.
  • the layer thickness of the n-type GaN layer 16 grown on the u-GaN layer 15 is about 2 to 10 ⁇ m.
  • the temperature of the sapphire substrate 11 is set to about 800 ° C.
  • the pressure in the reaction vessel is set to 10 to 100 kPa
  • the carrier gas N 2 is circulated at a flow rate of 5 to 15 L / min in the reaction vessel, and there
  • An element supply source (NH 3 ), a group III element supply source 1 (TMG), and a group III element supply source 2 (TMI) are supplied at a supply amount of 0.1 to 5 L / min, 5 to 15 ⁇ mol / min, and Flow at 2 to 30 ⁇ mol / min.
  • an InGaN layer 17a (well layer) is formed by epitaxial growth in the same plane orientation as the n-type GaN layer 16 and thus the same plane orientation as the u-GaN layer 15 in succession to the n-type GaN layer 16.
  • the thickness of the InGaN layer 17a grown on the n-type GaN layer 16 is 1 to 20 nm.
  • a group V element supply source (NH 3 ) and a group III element supply source (TMG) are flowed so that the respective supply amounts are 0.1 to 5 L / min and 5 to 15 ⁇ mol / min.
  • the GaN layer 17b (barrier layer) is formed by epitaxial growth in the same plane orientation as that of the InGaN layer 17a and thus the same plane orientation as that of the n-type GaN layer 16 and the u-GaN layer 15 in succession to the InGaN layer 17a.
  • the thickness of the GaN layer 17b grown on the InGaN layer 17a is 5 to 20 nm.
  • the emission wavelength of the multiple quantum well layer 17 depends on the InN mixed crystal ratio and the layer thickness of the InGaN layer 17a. If the layer thickness is the same, the higher the InN mixed crystal ratio, the longer the emission wavelength.
  • any of the above InGaN layers 17a and GaN layers 17b have principal surfaces in the same plane orientation as the n-type GaN layer 16 and the u-GaN layer 15. Therefore, when the sapphire substrate 11 having configurations 1 and 2 is used, the main surface of the GaN layer 17b is a nonpolar surface having no polarity in the layer thickness direction, and the InGaN layer 17a is formed on the nonpolar surface. Therefore, the influence of piezo polarization can be avoided, and by avoiding the influence of piezo polarization, problems such as a decrease in light emission efficiency and a shift in peak wavelength of light emission accompanying an increase in injection current can be improved.
  • the multi-quantum well layer 17 is a green light emitting layer (light emitting layer having an emission wavelength of about 520 nm) with a high InN mixed crystal ratio of the InGaN layer 17a, it is strongly affected by piezoelectric polarization, so that a remarkable improvement effect can be obtained. Can do.
  • a current blocking layer made of p-type AlGaInN may be inserted after the active layer is formed in order to prevent current leakage from the active layer to the p-type GaN layer 18 described later.
  • ⁇ Formation of p-type GaN layer> The temperature of the sapphire substrate 11 is set to 1000 to 1100 ° C., the pressure in the reaction vessel is set to 10 to 100 kPa, and the carrier gas H 2 is passed through the reaction vessel at a flow rate of 5 to 15 L / min.
  • Supply amounts of Group V element supply source (NH 3 ), Group III element supply source (TMG), and p-type doping element supply source (Cp 2 Mg) are 0.1 to 5 L / min, 50 to 150 ⁇ mol / min, respectively. And 0.03 to 30 ⁇ mol / min.
  • GaN is epitaxially grown continuously on the multiple quantum well layer 17 to form a p-type GaN layer 18.
  • the p-type GaN layer 18 grown on the multiple quantum well layer 17 has a thickness of about 100 nm.
  • the p-type GaN layer 18 may be composed of a plurality of layers having different doping element concentrations.
  • n-type GaN layer 16 is exposed by partially reactive ion etching a sapphire substrate 11 on which a semiconductor layer is formed.
  • vacuum deposition, sputtering, CVD (Chemical Vapor) is performed.
  • the n-type electrode 19n is formed on the n-type GaN layer 16 and the p-type electrode 19p is formed on the p-type GaN layer 18 by a method such as Deposition.
  • examples of the electrode material of the n-type electrode 19n include a laminated structure of Ti / Al, Ti / Al / Mo / Au, Hf / Au, or an alloy.
  • examples of the p-type electrode 19p include a laminated structure such as Pd / Pt / Au, Ni / Au, Pd / Mo / Au, an alloy, or an oxide-based transparent conductive material such as ITO (indium tin oxide). It is done.
  • each semiconductor light emitting element 10 is about 300 ⁇ 300 ⁇ m.
  • the semiconductor light emitting device 10 manufactured as described above has a substrate main surface portion 12a whose surface is covered with a crystal growth blocking layer 13 that blocks crystal growth of GaN, and the substrate main surface portion 12a.
  • a sapphire substrate 11 having a crystal growth surface portion 12b capable of crystal growth of GaN having different orientations and surface-exposed, and GaN is grown from the crystal growth surface portion 12b on the substrate surface 12 of the sapphire substrate 11 as a starting point.
  • the structure includes a u-GaN layer 15 formed by growing in the normal direction of the substrate main surface portion 12a, and is used as, for example, a GaN-based light emitting diode or a GaN-based semiconductor laser.
  • Embodiment 2 A method for manufacturing the semiconductor light emitting device 10 according to the second embodiment will be described with reference to FIGS. In addition, the part of the same name as Embodiment 1 is shown with the same code
  • symbol as Embodiment 1. FIG. 1 A method for manufacturing the semiconductor light emitting device 10 according to the second embodiment will be described with reference to FIGS. In addition, the part of the same name as Embodiment 1 is shown with the same code
  • the substrate surface 12 uses the sapphire substrate 11 having the substrate main surface portion 12a and the crystal growth surface portion 12b having a different plane orientation from the substrate main surface portion 12a. .
  • Substrate main surface portion 12a on substrate surface 12 is a-plane ⁇ 11-20 ⁇ plane>, c-plane ⁇ (0001) plane>, m-plane ⁇ 1-100 ⁇ plane>, or r-plane ⁇ 1-102].
  • the substrate main surface portion 12a is a miscut surface in which the a axis is inclined at a predetermined angle (for example, 45 °, 60 °, or a minute angle within several degrees) with respect to the normal direction of the substrate main surface portion 12a.
  • the sapphire substrate 11 may be a miscut substrate.
  • the plane directions of the a-plane, c-plane, and m-plane are orthogonal to each other.
  • the crystal growth surface portion 12b on the substrate surface 12 has a different plane orientation from the substrate main surface portion 12a, the a-plane ⁇ 11-20 ⁇ plane>, c-plane ⁇ (0001) plane>, m-plane ⁇ 1-100 ⁇ Plane>, or r plane ⁇ 1-102 ⁇ plane>, or a crystal plane of another plane orientation capable of crystal growth of GaN.
  • the crystal growth surface portion 12b for example, it can be constituted by a side surface of the concave groove 14 formed so as to extend on the sapphire substrate 11 as in the first embodiment.
  • the concave groove 14 may be a U-shaped groove, a V-shaped groove, or a trapezoidal groove as long as it has a side surface (etched side surface).
  • the groove width of the concave groove 14 is not particularly limited, but is preferably 0.5 to 10 ⁇ m, and the groove depth is 0.75 to 100 ⁇ m.
  • the concave groove 14 has an angle ⁇ of, for example, 70 to 120 ° on the side surface of the groove with respect to the substrate main surface portion 12a. Therefore, as shown in FIG. It may be tapered outwardly so as to widen the groove width toward the opening. Also, as shown in FIG. 9B, the inner width is narrowed from the groove bottom toward the groove opening. A reverse tapered shape inclined in the direction may be used.
  • the angle is not limited as long as GaN crystal can be grown from the side surface.
  • the c-plane GaN is grown from c-plane sapphire from the side, from the viewpoint of reducing defects appearing on the surface by not reaching the surface of defects such as stacking faults and dislocations
  • the angle ⁇ formed with respect to the substrate main surface portion 12a on the side surface of the groove is preferably larger than the angle ⁇ formed with respect to the substrate main surface portion 12a on the c-plane.
  • the concave groove 14 has a bottom surface, the groove depth is preferably 1.5 times or more the groove opening width from the viewpoint of suppressing GaN crystal growth from the bottom surface. Only one groove 14 may be formed, or a plurality of grooves 14 may be formed in parallel.
  • the distance between the grooves that is, the distance between the substrate main surface portions 12a between the adjacent concave grooves 14 is 1 to 100 ⁇ m.
  • the groove 14 is formed by patterning a photoresist in which only a portion of the sapphire substrate 11 to be formed is an opening, and the sapphire substrate 11 is subjected to dry etching such as reactive ion etching (RIE) or the like using the photoresist as an etching resist. It can be formed by wet etching.
  • RIE reactive ion etching
  • the substrate main surface portion 12a is an r-plane, or the r-plane is an a-axis ([11-20] axis) as a rotation axis.
  • the miscut which is the crystal growth surface portion 12b in which the extending direction of the concave groove 14 is the surface orientation of the a-plane, that is, the a-axis direction, and one of the side surfaces has an inclination angle of 57 ⁇ 20 ° with respect to the r-axis.
  • a substrate is mentioned.
  • 57 ° is an angle formed between the r-plane and the c-plane, and an angle formed between the side surface and the c-plane is allowed up to ⁇ 20 °, but the range of this angle is not limited as long as crystal growth occurs. .
  • examples of the sapphire substrate 11 include a substrate whose substrate main surface portion 12a is a (11-22) plane, or a miscut substrate that is a miscut surface thereof.
  • the off angle is an angle formed by the substrate main surface portion 12a and the crystal plane of the substrate main surface. That is, when the substrate main surface portion 12a is the (1-102) plane or its miscut surface, the angle is formed by the substrate main surface and the (1-102) plane, and the substrate main surface portion 12a is (11-22). In the case of a surface or its miscut surface, it is an angle formed by the substrate main surface and the (11-22) surface.
  • examples of the sapphire substrate 11 include a substrate whose substrate main surface portion 12a is a-plane, or a miscut substrate that is a miscut surface thereof.
  • the one side surface which is the crystal growth surface portion 12b is preferably a surface capable of growing c-plane of GaN, and more preferably c-plane.
  • GaN is crystal-grown starting from the crystal growth surface portion 12b on the substrate surface 12 of the sapphire substrate 11 prepared as described above.
  • the u-GaN layer 15 is formed so as to grow in the normal direction of the substrate main surface portion 12a to obtain the semiconductor substrate S.
  • the substrate main surface portion 12a is the (1-102) plane or a miscut surface thereof, and one side surface of the groove 14 which is the crystal growth surface portion 12b is a surface capable of growing the c-plane of GaN.
  • GaN grows in crystals starting from the substrate main surface portion 12a and the crystal growth surface portion 12b.
  • the crystal growth rate from the crystal growth surface portion 12b is higher than the crystal growth rate from the substrate main surface portion 12a, the growth of the layer in the normal direction of the substrate main surface portion 12a is achieved.
  • GaN crystal growth from the crystal growth surface portion 12b has priority, and as a result, as shown in FIG.
  • an n-type GaN layer 16, a multiple quantum well layer 17 as a light emitting layer, a p-type GaN layer 18, a p-type electrode 19p, and an n-type electrode 19n are formed thereon.
  • Each forming method is the same as that of the first embodiment.
  • the substrate main surface portion 12a on the substrate surface 12 is an r-plane or a (11-22) plane.
  • the ⁇ 1-102 ⁇ plane in addition to the ⁇ 1-102 ⁇ plane, has an off-angle ⁇ 1 with the a-axis ([11-20] axis) as the rotation axis.
  • ⁇ 2 ⁇ 5 to 5 °
  • the (11-22) plane of the substrate main surface portion 12a in the present application includes the miscut plane. That is, the sapphire substrate 11 may be a miscut substrate.
  • the off angle is an angle formed by the substrate main surface portion 12a and the crystal plane near the substrate main surface. That is, in the case of the r plane, it is an angle formed by the substrate main surface portion 12a and the (1-102) plane, and in the case of the (11-22) plane, the substrate main surface portion 12a and the (11-22) plane are formed. Is an angle.
  • the groove width of the concave groove 14 is not particularly limited, but is preferably 0.5 to 10 ⁇ m, and the groove depth is 0.75 to 10 ⁇ m. Only one groove 14 may be formed, or a plurality of grooves 14 may be formed in parallel. When a plurality of the concave grooves 14 are formed in parallel, the distance between the grooves, that is, the distance between the substrate main surface portions 12a between the adjacent concave grooves 14 is 1 to 100 ⁇ m.
  • the concave groove 14 is formed by patterning a photoresist on the substrate surface 12 of the sapphire substrate 11 so that only a portion where the concave groove is to be formed becomes an opening, and the sapphire substrate 11 is subjected to reactive ion etching (RIE) using the photoresist as an etching resist.
  • RIE reactive ion etching
  • Etc. can be formed by dry etching or wet etching.
  • One side surface of the groove 14 which is the crystal growth surface portion 12b is preferably a c-plane ⁇ (0001) plane>.
  • the substrate main surface portion 12a is an r-plane, it is formed with respect to the substrate main surface portion 12a.
  • the angle is preferably 57 ⁇ 20 °, for example. 57 ° is an angle formed between the r-plane and the c-plane, and an angle formed between the side surface and the c-plane is allowed up to ⁇ 20 °, but the range of this angle is not limited as long as crystal growth occurs. .
  • Examples of the crystal growth prevention layer 13 include oxide films and nitride films such as Si, Ti, Ta, and Zr, specifically, SiO 2 films, SiN x films, SiO x N y films, TiO 2 films, Examples thereof include a ZrO 2 film.
  • the crystal growth preventing layer 13 has a thickness of 0.01 to 3 ⁇ m.
  • the crystal growth blocking layer 13 can be formed on the sapphire substrate 11 by a method such as vacuum deposition, sputtering, or CVD (Chemical Vapor Deposition).
  • the crystal growth blocking layer 13 may be composed of a single layer or a plurality of layers.
  • metal organic chemical vapor deposition Metal-Organic-Vapor-Phase Epitaxy: MOVPE
  • molecular beam epitaxy MBE
  • hydride vapor phase growth Hydride-Vapor-Phase
  • MOVPE Metal-Organic-Vapor-Phase Epitaxy
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase growth
  • metal organic vapor phase epitaxy is the most common.
  • the MOVPE apparatus used for forming the semiconductor layer is mainly composed of a substrate transport system, a substrate heating system, a gas supply system, and a gas exhaust system, all of which are electronically controlled.
  • the substrate heating system is composed of a thermocouple and a resistance heater, and a carbon or SiC susceptor provided thereon, and a quartz tray on which a sapphire substrate 11 is set is conveyed on the susceptor, and a semiconductor The layer is epitaxially grown.
  • This substrate heating system is installed in a quartz double tube or a stainless steel reaction vessel equipped with a water cooling mechanism, and a carrier gas and various source gases are supplied into the double tube or reaction vessel.
  • a quartz flow channel is used to realize a laminar gas flow on the substrate.
  • Examples of the carrier gas include H 2 and N 2 .
  • An example of the group V element supply source is NH 3 .
  • Examples of the group III element supply source include trimethylgallium (TMG), trimethylindium (TMI), trimethylaluminum (TMA), and the like.
  • Examples of the n-type doping element supply source include SiH 4 (silane), Si 2 H 6 (disilane), and GeH 4 (germane).
  • Examples of the p-type doping element supply source include Cp 2 Mg (biscyclopentadienyl magnesium).
  • ⁇ Formation of u-GaN layer> First, after setting the sapphire substrate 11 on the quartz tray so that the substrate surface 12 faces upward, the sapphire substrate 11 is heated to 1050 to 1150 ° C. and the pressure in the reaction vessel is set to 10 to 100 kPa. The sapphire substrate 11 is thermally cleaned by circulating H 2 as a carrier gas in a flow channel installed inside and maintaining that state for several minutes.
  • the growth of the GaN layer proceeds in the normal direction of the substrate main surface portion 12a, and the main surface is semipolar ⁇ 11-22 ⁇ on the sapphire substrate 11 as shown in FIG.
  • a u-GaN layer (undoped GaN layer) 15 which is a surface is formed.
  • the substrate main surface portion 12a is the (11-22) plane, an appropriate miscut surface is used, and the growth conditions are selected so that the main surface is a semipolar (10-12) plane.
  • the semiconductor substrate S is obtained by forming the layer 15 or the u-GaN layer 15 having the (10-11) plane.
  • the thickness of the u-GaN layer 15 grown on the crystal growth blocking layer 13 is about 2 to 20 ⁇ m.
  • a low-temperature buffer layer having a thickness of about 20 to 30 nm on the crystal growth surface portion 12b.
  • Such a method of forming the u-GaN layer 15 whose main surface is a semipolar surface uses a sapphire substrate 11 as a starting material, and a crystal growth surface portion having a surface orientation different from that of the substrate main surface portion 12a of the substrate surface 12 Since GaN is grown on the c-plane starting from 12b, and a layer of semipolar plane GaN is grown in the normal direction of the substrate main surface portion 12a, the u-GaN layer 15 whose main surface is a semipolar plane can be easily formed.
  • the u-GaN layer 15 with few defects can be obtained by a single crystal growth by a selective lateral growth technique.
  • the u-GaN layer 15 that is a semipolar surface can be formed relatively inexpensively and in a large area.
  • the substrate main surface portion 12a or the like is covered with a thick crystal growth blocking layer 13 having a thickness of 0.2 ⁇ m or more, dislocations extending in the m-axis or a-axis direction generated in the initial stage of GaN growth are crystallized. It can be expected that the growth inhibition layer 13 stops.
  • the GaN has a substrate main surface portion 12a and a crystal growth surface. Crystal growth starts from each of the portions 12b. However, by selecting a condition in which the crystal growth rate from the crystal growth surface portion 12b is higher than the crystal growth rate from the substrate main surface portion 12a, the GaN crystal growth in the normal direction of the substrate main surface portion 12a is achieved. As a result, the main surface of the u-GaN layer 15 is semipolar ⁇ (11-22) ⁇ plane, semipolar (10-12) plane, or semipolar ( 10-11) plane.
  • each semiconductor layer is formed thereon as follows.
  • an InGaN layer 17a (well layer) is formed by epitaxial growth in the same plane orientation as the n-type GaN layer 16 and thus the same plane orientation as the u-GaN layer 15 in succession to the n-type GaN layer 16.
  • the thickness of the InGaN layer 17a grown on the n-type GaN layer 16 is 1 to 20 nm.
  • GaN is epitaxially grown continuously on the multiple quantum well layer 17 to form a p-type GaN layer 18.
  • the p-type GaN layer 18 grown on the multiple quantum well layer 17 has a thickness of about 100 nm.
  • the p-type GaN layer 18 may be composed of a plurality of layers having different doping element concentrations.
  • n-type GaN layer 16 is exposed by partially reactive ion etching a sapphire substrate 11 on which a semiconductor layer is formed, a method such as vacuum deposition, sputtering, CVD, etc.
  • a method such as vacuum deposition, sputtering, CVD, etc.
  • the n-type electrode 19n and the p-type electrode 19p are formed on the n-type GaN layer 16 and the p-type GaN layer 18, respectively.
  • each semiconductor light emitting element 10 is about 300 ⁇ m ⁇ 300 ⁇ m.
  • the semiconductor light emitting device 10 having the sapphire substrate 11 is used.
  • the present invention is not limited to this, and the crystal is formed in the normal direction of the substrate main surface portion 12a on the substrate surface 12 of the sapphire substrate 11.
  • the grown GaN layer may be separated from the sapphire substrate 11 to form a GaN substrate semiconductor substrate, and a semiconductor layer may be formed thereon.
  • the semiconductor substrate of the GaN substrate in which the GaN layer formed by crystal growth on the sapphire substrate 11 as described above is separated from the sapphire substrate 11 the following characteristics are obtained with respect to the conventional nonpolar or semipolar GaN substrate.
  • Example substrate (Sample substrate) ⁇ Sample substrate 1> A resist is patterned in a stripe pattern on a sapphire substrate having an a-plane as a main surface so as to extend in the m-axis direction, and then a SiO 2 layer having a thickness of about 200 nm is formed by sputtering. After a Ni layer having a thickness of about 500 nm is formed on the substrate by electron beam evaporation (EB method), the resist is dissolved (lift-off method), and an etching resist having a stacked structure of Ni (upper side) / SiO 2 (lower side) A pattern was formed.
  • EB method electron beam evaporation
  • This sample substrate 1 has a surface-exposed crystal growth surface in which the substrate surface is constituted by a substrate main surface portion whose surface is covered with a crystal growth inhibition layer constituted by a SiO 2 layer and a side surface of a concave groove which is a c-plane. And a portion.
  • Example 1 After setting the sample substrate 1 on the quartz tray so that the substrate surface faces upward in the MOVPE apparatus, the substrate is heated to 1150 ° C. and the pressure in the reaction vessel is set to 100 kPa. As a result, H 2 was circulated at a flow rate of 10 L / min, and this state was maintained for 10 minutes to thermally clean the substrate.
  • the temperature of the substrate is set to 1150 ° C.
  • the pressure in the reaction vessel is set to 100 kPa
  • the carrier gas to be circulated in the reaction vessel is set to H 2 while being circulated at a flow rate of 10 L / min.
  • a u-GaN layer was formed on the substrate so as to grow in the normal direction of the main surface portion of the substrate by allowing GaN (undoped GaN) to grow on the low-temperature buffer layer by flowing for 10 minutes.
  • Example 2 The sample substrate 2 was subjected to the same operation as in Example 1 to form a u-GaN layer on the substrate.
  • Example 4 The sample substrate 2 was subjected to the same operation as in Example 3 to form a u-GaN layer on the substrate.
  • Example 5 (U-GaN layer forming substrate) ⁇ Example 5>
  • the resist is patterned in a stripe pattern on the sapphire substrate with the r-plane as the main surface, and then dry-etched by reactive ion etching (RIE) to be parallel to the a-axis direction on the sapphire substrate.
  • RIE reactive ion etching
  • the concave grooves were formed so that the groove opening width was about 3 ⁇ m, the groove depth was about 1 ⁇ m, the groove bottom width was about 2 ⁇ m, and the distance between the substrate main surface portions to adjacent concave grooves was about 3 ⁇ m.
  • the resist was removed after dry etching.
  • the sapphire substrate is heated to 1150 ° C. and the pressure in the reaction vessel is set to 100 kPa.
  • the substrate was thermally cleaned by circulating H 2 as a gas at a flow rate of 10 L / min and maintaining this state for 10 minutes.
  • the temperature of the sapphire substrate is set to 460 ° C.
  • the pressure in the reaction vessel is set to 100 kPa
  • the carrier gas flowing through the reaction vessel is supplied at a flow rate of H 2 10 L / min, while supplying the group V element supply source there (NH 3 ) and a group III element supply source (TMG) were supplied at 5 L / min and 8 ⁇ mol / min, respectively, and a low-temperature buffer layer of about 30 nm was formed on the crystal growth surface portion on the side surface of the groove.
  • the temperature of the substrate is set to 1000 ° C.
  • the pressure in the reaction vessel is set to 100 kPa
  • the carrier gas to be circulated in the reaction vessel is set to H 2 while being circulated at a flow rate of 10 L / min.
  • a u-GaN layer was formed on the substrate so as to grow in the normal direction of the main surface portion of the substrate by allowing GaN (undoped GaN) to grow on the low-temperature buffer layer by flowing for 10 minutes.
  • Example 6> The u-GaN layer is formed on the sapphire substrate in the same manner as in Example 1 except that a miscut substrate of sapphire substrate in which the off angle ⁇ 2 in the c-axis direction is ⁇ 1 ° with the direction approaching the c-plane as a plus is used. Formed.
  • Example 7 A u-GaN layer was formed on the sapphire substrate in the same manner as in Example 1 except that a miscut substrate of a sapphire substrate having an off angle ⁇ 2 of ⁇ 0.5 ° was used.
  • Example 8> A u-GaN layer was formed on the sapphire substrate in the same manner as in Example 1 except that a sapphire substrate having an off angle ⁇ 2 of + 0.5 ° was used.
  • Example 9 A u-GaN layer was formed on the sapphire substrate in the same manner as in Example 1 except that a sapphire substrate having an off angle ⁇ 2 of + 1 ° was used.
  • the present invention is useful for a semiconductor substrate, a manufacturing method thereof, an electronic device using the semiconductor substrate, and a semiconductor light emitting element.

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Abstract

La présente invention concerne un substrat semi-conducteur qui est doté : d’un substrat en saphir (11), une surface de substrat (12) présentant une surface principale de substrat (12a) et une surface de croissance de cristaux (12b) où la direction du plan est différente de celle de la surface principale de substrat (12a) et où un cristal de GaN peut être mis à croître ; et d’une couche de GaN (15) mise à croître dans la direction de ligne normale de la surface principale du substrat (12a) par la croissance d’un cristal de GaN, la surface de croissance de cristaux (12b) de la surface du substrat (12) sur le substrat en saphir (11) formant le point de départ.
PCT/JP2009/003960 2008-08-25 2009-08-20 Substrat semi-conducteur et son procédé de fabrication WO2010023846A1 (fr)

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JP2019077601A (ja) * 2017-10-27 2019-05-23 古河機械金属株式会社 Ｉｉｉ族窒化物半導体基板、及び、ｉｉｉ族窒化物半導体基板の製造方法
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WO2020256028A1 (fr) * 2019-06-20 2020-12-24 株式会社小糸製作所 Substrat pour croissance de semi-conducteurs, élément semi-conducteur, élément électroluminescent semi-conducteur et procédé de production d'élément semi-conducteur
JP2021002574A (ja) * 2019-06-21 2021-01-07 古河機械金属株式会社 構造体、光デバイス、光デバイスの製造方法、および構造体の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003209062A (ja) * 2002-01-17 2003-07-25 Sony Corp 化合物半導体層の結晶成長方法及び半導体素子
JP2003347585A (ja) * 2002-03-19 2003-12-05 Nobuhiko Sawaki 半導体発光素子およびその製造方法
JP2006036561A (ja) * 2004-07-23 2006-02-09 Toyoda Gosei Co Ltd 半導体結晶の結晶成長方法、光半導体素子、及び結晶成長基板
JP2008288461A (ja) * 2007-05-18 2008-11-27 Sony Corp 半導体層の成長方法、半導体発光素子の製造方法、半導体発光素子および電子機器
JP2009184842A (ja) * 2008-02-01 2009-08-20 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物系化合物半導体の製造方法、ウエハ、ｉｉｉ族窒化物系化合物半導体素子

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003209062A (ja) * 2002-01-17 2003-07-25 Sony Corp 化合物半導体層の結晶成長方法及び半導体素子
JP2003347585A (ja) * 2002-03-19 2003-12-05 Nobuhiko Sawaki 半導体発光素子およびその製造方法
JP2006036561A (ja) * 2004-07-23 2006-02-09 Toyoda Gosei Co Ltd 半導体結晶の結晶成長方法、光半導体素子、及び結晶成長基板
JP2008288461A (ja) * 2007-05-18 2008-11-27 Sony Corp 半導体層の成長方法、半導体発光素子の製造方法、半導体発光素子および電子機器
JP2009184842A (ja) * 2008-02-01 2009-08-20 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物系化合物半導体の製造方法、ウエハ、ｉｉｉ族窒化物系化合物半導体素子

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010157716A (ja) * 2008-12-31 2010-07-15 Seoul Opto Devices Co Ltd 複数の非極性発光セルを有する発光素子及びその製造方法
JP2013522152A (ja) * 2010-03-18 2013-06-13 フライベルガー・コンパウンド・マテリアルズ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング 半極性の半導体結晶およびそれを製造するための方法
JP2012033893A (ja) * 2010-07-29 2012-02-16 Univ Qinghua Ｉｉｉ族窒化物発光ダイオード
WO2012042961A1 (fr) * 2010-09-27 2012-04-05 住友電気工業株式会社 Procédé de croissance d'un cristal de nitrure de gallium (gan) et substrat de cristal de gan
CN102479900A (zh) * 2010-11-25 2012-05-30 丰田合成株式会社 第iii族氮化物半导体发光器件
JP2012114277A (ja) * 2010-11-25 2012-06-14 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物半導体発光素子
CN102479900B (zh) * 2010-11-25 2015-03-11 丰田合成株式会社 第iii族氮化物半导体发光器件
WO2012121154A1 (fr) 2011-03-07 2012-09-13 株式会社トクヤマ Base, substrat comportant une couche cristalline de nitrure de gallium et procédé pour sa production
JP2012184144A (ja) * 2011-03-07 2012-09-27 Tokuyama Corp 窒化ガリウム結晶積層基板及びその製造方法
CN102184846A (zh) * 2011-04-22 2011-09-14 东莞市中镓半导体科技有限公司 一种图形化衬底的制备方法
JP2013173641A (ja) * 2012-02-24 2013-09-05 Tokuyama Corp 窒化ガリウム結晶積層基板及びその製造方法
JP2013175652A (ja) * 2012-02-27 2013-09-05 Tokuyama Corp 半導体装置の製造方法
JP2013193918A (ja) * 2012-03-19 2013-09-30 Tokuyama Corp 窒化ガリウム結晶自立基板及びその製造方法
WO2013141099A1 (fr) * 2012-03-19 2013-09-26 国立大学法人山口大学 Substrat autoporteur cristallin au nitrure de gallium, et procédé de fabrication de celui-ci
CN104838473A (zh) * 2012-11-30 2015-08-12 索芙特-艾匹株式会社 Ⅲ族氮化物半导体层积体
JP2015198196A (ja) * 2014-04-02 2015-11-09 ローム株式会社 半導体装置および半導体装置の製造方法
JP2017522721A (ja) * 2014-05-20 2017-08-10 サントル、ナショナール、ド、ラ、ルシェルシュ、シアンティフィク、（セーエヌエルエス） 半極性ｉｉｉ族窒化物層を含む半導体材料の製造方法
JPWO2016035696A1 (ja) * 2014-09-02 2017-10-19 株式会社Flosfia 積層構造体およびその製造方法、半導体装置ならびに結晶膜
JP2016199468A (ja) * 2016-07-12 2016-12-01 住友電気工業株式会社 ＧａＮ結晶基板
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JP2019054196A (ja) * 2017-09-19 2019-04-04 株式会社東芝 半導体装置及びその製造方法
JP2020174202A (ja) * 2017-09-19 2020-10-22 株式会社東芝 半導体装置及びその製造方法
JP2019077601A (ja) * 2017-10-27 2019-05-23 古河機械金属株式会社 Ｉｉｉ族窒化物半導体基板、及び、ｉｉｉ族窒化物半導体基板の製造方法
WO2020256028A1 (fr) * 2019-06-20 2020-12-24 株式会社小糸製作所 Substrat pour croissance de semi-conducteurs, élément semi-conducteur, élément électroluminescent semi-conducteur et procédé de production d'élément semi-conducteur
JP2021001089A (ja) * 2019-06-20 2021-01-07 株式会社小糸製作所 半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法
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