WO2010016564A1 - Dispositif à semiconducteurs - Google Patents

Dispositif à semiconducteurs Download PDF

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WO2010016564A1
WO2010016564A1 PCT/JP2009/064000 JP2009064000W WO2010016564A1 WO 2010016564 A1 WO2010016564 A1 WO 2010016564A1 JP 2009064000 W JP2009064000 W JP 2009064000W WO 2010016564 A1 WO2010016564 A1 WO 2010016564A1
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layer
dimensional electron
electron gas
low resistance
gan
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達峰 中山
広信 宮本
裕二 安藤
康宏 岡本
隆 井上
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日本電気株式会社
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention is based on the priority claim of Japanese Patent Application No. 2008-204602 (filed on Aug. 7, 2008), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a semiconductor device, and more particularly to a nitride semiconductor device.
  • Gate-recessed MISFET Metal Insulated Field Transducer Structure
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • HFET Hetero Junction Field Effect Transistor
  • Patent Document 1 Japanese Patent Laid-Open No. 2007-35905 discloses a structure using a Si 3 N 4 film as an insulating film on AlGaN / GaN.
  • FIG. 6 is a cross-sectional structure diagram of the field effect transistor disclosed in Patent Document 1 (FIG. 10 of Patent Document 1). As shown in FIG. 6, after the GaN channel layer 1, the AlGaN barrier layer 2, the GaN layers 3, 4, and the AlGaN layers 5, 6 are stacked, the gate electrodes of the GaN layers 3, 4 and the AlGaN layers 5, 6 are arranged. A recess is formed by removing the portion, a source electrode 8 and a drain electrode 9 are formed so as to be in ohmic contact with the AlGaN layers 5 and 6, a gate insulating film 15 is formed in the recess, and a gate electrode 10 is formed. It is produced by.
  • the AlGaN barrier layer 2 is sufficiently thin, so that a normally-off operation is possible.
  • a piezo electric field is generated, and a two-dimensional electron gas in a region other than the gate electrode ( 2 (Dimensional (Electron Gas)) can be increased, and the on-resistance can be reduced.
  • Patent Document 1 Note that the entire disclosure of Patent Document 1 is incorporated herein by reference. The following is an analysis of the related art according to the present invention.
  • a two-dimensional electron gas is also formed at the interface between the GaN layer 4 and the AlGaN layer 6 on the drain electrode 9 side. Since the two-dimensional electron gas is opposed to the gate electrode 10 via the insulating film 15, high voltage operation becomes difficult. That is, it is difficult to achieve both low source resistance and high voltage operation.
  • an object of the present invention is to provide a semiconductor device that performs a good enhancement operation, can operate at a high voltage, and has a low source resistance.
  • the invention disclosed in the present application is generally configured as follows in order to solve the above problems.
  • a field effect transistor comprising a group III-V nitride semiconductor and having an insulating film between the gate electrode and the semiconductor
  • two-dimensional electrons are present in the semiconductor layer between the drain electrode and the gate electrode.
  • a semiconductor device in which a gas is formed and a region is formed by forming a two-dimensional electron gas in at least a part of a semiconductor layer between the source electrode and the gate electrode.
  • a recess structure in which a part of the III-V nitride semiconductor layer is removed is provided, a part of the drain electrode is disposed in a part of the recess region, and the source electrode is disposed in the recess region.
  • a carrier supply layer (electron supply layer) and a carrier transit layer (electron transit layer) are provided between the drain electrode and the substrate, and two-dimensional electrons are provided between the source electrode and the carrier transit layer.
  • a gas release layer is provided.
  • a low resistance layer using electrons as carriers is further provided between the source electrode and the two-dimensional electron gas elimination layer.
  • part or all of the semiconductor layers facing each other across the gate electrode and the insulating film are the n-type low resistance layer.
  • a part of the semiconductor layer facing the gate electrode and the insulating film is an n-type low resistance layer, and a part is a two-dimensional electron gas elimination layer or a carrier supply layer.
  • a part of the semiconductor layer facing the gate electrode and the insulating film is an n-type low resistance layer, a part is a two-dimensional electron gas elimination layer, and a part is a carrier supply layer.
  • the carrier traveling layer is made of In x Ga 1-x N (0 ⁇ x ⁇ 1).
  • the carrier supply layer is made of unstrained or tensile strained In a Al b Ga 1-ab N (0 ⁇ a, 0 ⁇ b, a + b ⁇ 1).
  • the two-dimensional electron gas elimination layer is composed of unstrained or compressive strained GaN or compressive strained In ⁇ Al ⁇ Ga 1- ⁇ - ⁇ N (0 ⁇ , 0 ⁇ ⁇ , ⁇ + ⁇ ⁇ 1). .
  • unstrained or compressive strained n-type In y Ga 1-y N (0 ⁇ y ⁇ 1) or In m Al 1 Ga 1-ml N (0 ⁇ m, 0 ⁇ l, m + l ⁇ 1).
  • the gate insulating film is made of a substance (material) composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N.
  • low resistance and high breakdown voltage can be independently achieved, and both low source resistance and high voltage operation can be achieved.
  • Gate electrode 15 Gate insulating film 101 Substrate 102 Buffer layer 103 made of the first GaN-based semiconductor Carrier carrier layer 104 made of the second GaN-based semiconductor Third GaN-based semiconductor Carrier supply layer 105 made of a four-dimensional electron gas elimination layer 106 made of a fourth GaN-based semiconductor Low resistance layer made of a fifth GaN-based semiconductor 107 Source electrode 108 Drain electrode 109 Gate insulating film 110 Gate electrode 111 Protective film 201 Substrate 202 Buffer layer 203 made of the first GaN-based semiconductor Carrier carrier layer 204 made of the second GaN-based semiconductor Carrier supply layer 205 made of the third GaN-based semiconductor Two-dimensional electron gas elimination layer made of the fourth GaN-based semiconductor 206 Low resistance layer 207 made of
  • a two-dimensional electron gas is formed in the semiconductor layer between the drain electrode and the gate electrode, but in at least a part of the semiconductor layer between the source electrode and the gate electrode,
  • a two-dimensional electron gas is formed by the two-dimensional electron gas elimination layer that prevents the two-dimensional electron gas from accumulating in the carrier (electron) traveling layer.
  • the electrical conduction is performed through a low resistance layer on the two-dimensional electron gas elimination layer.
  • the two-dimensional electron gas elimination layer between the two-dimensional electron gas and the low resistance layer becomes a barrier, when the gate voltage is 0 V, a current flows between the two-dimensional electron gas and the low resistance layer. Does not flow and is in enhancement mode.
  • the source resistance is determined by a low-resistance layer that does not use a two-dimensional electron gas, and the low-resistance layer exists only between the source electrode and the gate electrode. Does not exist. For this reason, a reduction in resistance and an increase in breakdown voltage can be performed independently, and both a reduction in source resistance and a high voltage operation can be achieved.
  • FIG. 1 is a diagram schematically showing a cross-sectional structure of the first embodiment of the present invention.
  • the field effect transistor of the present embodiment is On the substrate 101, A buffer layer 102 made of a first GaN-based semiconductor (group III-V nitride semiconductor); A carrier traveling layer 103 made of a second GaN-based semiconductor, A carrier supply layer 104 made of a third GaN-based semiconductor, A two-dimensional electron gas elimination layer 105 made of a fourth GaN-based semiconductor, which works to prevent the two-dimensional electron gas from accumulating in the carrier traveling layer by raising the conduction band of the carrier supply layer to the vacuum level side; Low resistance layer 106 made of a fifth GaN-based semiconductor Are formed in this order.
  • group III-V nitride semiconductor group III-V nitride semiconductor
  • a carrier traveling layer 103 made of a second GaN-based semiconductor
  • a carrier supply layer 104 made of a third GaN-based semiconductor
  • a two-dimensional electron gas elimination layer 105 made of
  • the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 are removed by recess etching between the drain electrode and the gate electrode, and a region below the gate electrode and a part below the gate electrode.
  • the remaining side surfaces of the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 are formed so as to have a taper (taper angle) rather than perpendicular to the surface before the removal.
  • the source electrode 107 In contact with the low resistance layer 106, the source electrode 107, A drain electrode 108 is formed in contact with the carrier supply layer 104, Next, the gate insulating film 109 is formed, and the gate electrode 110 is formed.
  • a field effect transistor is manufactured by forming a protective film 111.
  • the substrate 101 for example, sapphire, silicon carbide, GaN, AlN or the like is used.
  • the first to fifth GaN-based semiconductors are indicated by reference numerals 102 to 106, respectively.
  • the first GaN-based semiconductor 102 for example, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, or the like is used.
  • a nucleation layer made of GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, or the like may be sandwiched between the substrate 101 and the buffer layer 102.
  • the first GaN-based semiconductor 102 As an n-type impurity, for example, Si, S, Se, etc. As the p-type impurity, for example, Be, C, Mg, or the like can be added.
  • n-type impurity for example, Si, S, Se, etc.
  • p-type impurity for example, Be, C, Mg, or the like can be added.
  • the second GaN-based semiconductor 103 for example, GaN, InN, AlN, and a mixture of the above three kinds of GaN-based semiconductors are used.
  • the impurity concentration in the second GaN-based semiconductor 103 is desirably 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the third GaN-based semiconductor 104 for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors are used. However, in this example, the material or composition has a smaller electron affinity than the second GaN-based semiconductor.
  • n-type impurity for example, Si, S, Se, etc.
  • p-type impurity for example, Be, C, Mg, or the like can be added.
  • Examples of the fourth GaN-based semiconductor 105 include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors.
  • the fourth GaN-based semiconductor 105 needs to work to eliminate the two-dimensional electron gas, a substance or composition capable of inducing a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer. It is.
  • the fourth GaN-based semiconductor 105 As an n-type impurity, for example, Si, S, Se, etc. As the p-type impurity, for example, Be, C, Mg, or the like can be added.
  • n-type impurity for example, Si, S, Se, etc.
  • p-type impurity for example, Be, C, Mg, or the like can be added.
  • the fifth GaN-based semiconductor 106 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors.
  • the n-type impurity Si, S, Se, or the like can be used as the n-type impurity.
  • the p-type impurity for example, Be, C, Mg, or the like can be added, but the conductivity type is n-type.
  • the gate insulating film 109 there is a substance composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N.
  • the protective film 111 there is a substance composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N, or an organic material.
  • the field effect transistor of this example is A silicon (Si) substrate as the substrate 101;
  • the first GaN-based semiconductor (buffer layer) 102 an AlGaN layer (Al composition ratio 0.2, film thickness 500 nm),
  • the second GaN-based semiconductor (carrier running layer) 103 a GaN carrier running layer (film thickness 1000 nm)
  • the third GaN-based semiconductor (carrier supply layer) 104 an AlGaN carrier supply layer (Al composition ratio 0.2, film thickness 15 nm)
  • As a fourth GaN-based semiconductor (two-dimensional electron gas elimination layer) 105 an InGaN two-dimensional electron gas elimination layer (In composition ratio 0.15, film thickness 10 nm, Mg-doped 1 ⁇ 10 18 cm ⁇ 3 )
  • the fifth GaN-based semiconductor (low resistance layer) 106 an epitaxial substrate made of a GaN low resistance layer (film thickness: 50 nm, Si-doped 1 ⁇ 10 19
  • a SiN film of 200 nm is formed, and using a photoresist as a mask, for example, ICP (Inductivity Coupled Plasma) dry etching using SF6 (Sulfur Hexafluoride) as a process gas is performed. Open the recess.
  • ICP Inductivity Coupled Plasma
  • recess etching is performed by ICP dry etching using, for example, a mixed gas of BCl3 (Boron Trichloride) and SF6 as a process gas to eliminate the two-dimensional electron gas
  • a mixed gas of BCl3 (Boron Trichloride) and SF6 as a process gas to eliminate the two-dimensional electron gas
  • the side surfaces of the SiN film are also etched at the same time, so that the side surfaces of the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 are tapered.
  • the etching stops when F is bonded to the surface of the AlGaN carrier supply layer the two-dimensional electron gas elimination layer 105 and the low resistance layer 106 can be selectively removed.
  • the SiN film is removed using HF (Hydrogen Fluoride) aqueous solution, Nb / Al / Nb / Au (film thickness 7 nm / 60 nm / 35 nm / 50 nm, heat treatment 850 ° C., 30 seconds) is formed as the source electrode 107 and the drain electrode 108.
  • HF Hydrofluoride
  • the gate insulating film 109 an Al 2 O 3 film (film thickness 20 nm), As the gate electrode 110, Ni / Au (Ni layer thickness 10nm, Au layer thickness 400nm), A SiON film (film thickness of 80 nm) is formed as the protective film 111, and a field effect transistor is manufactured.
  • the resistance of the GaN low-resistance layer doped with Si at a high density of 1 ⁇ 10 19 cm ⁇ 3 is extremely low, so that a low source resistance can be realized.
  • the operation voltage is 50 V or more while having a low source resistance. High voltage operation was possible.
  • the region works to alleviate electric field concentration, so that it is particularly suitable for high voltage operation. Is suitable.
  • Si is used as the substrate 101, but any other substrate such as SiC or sapphire can be used.
  • an AlGaN layer is used as the buffer layer 102.
  • GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used as the buffer layer 102.
  • a GaN layer is used as the carrier traveling layer 103.
  • the carrier traveling layer 103 GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used. .
  • an AlGaN layer is used as the carrier supply layer 104.
  • the carrier supply layer 104 GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors, such as an InAlN layer, are used. it can.
  • the electron affinity of the carrier supply layer 104 needs to be a material or composition smaller than the electron affinity of the carrier traveling layer 103.
  • the carrier supply layer 104 since the lattice constant of the carrier supply layer 104 is different from the lattice constant of the carrier traveling layer 103 which is the thickest layer, it is preferable that the carrier supply layer 104 be not more than the critical film thickness at which dislocation occurs.
  • an InGaN layer is used as the two-dimensional electron gas elimination layer 105, but the two-dimensional electron gas elimination layer 105 is an InAlN layer, such as GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. Etc. can be used.
  • the fourth GaN-based semiconductor needs to work to eliminate the two-dimensional electron gas
  • the fourth GaN-based semiconductor needs to be a substance or composition that can induce a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer.
  • the carrier running layer and the carrier supply layer for example, unstrained or compressive strained GaN, or compressive strained In ⁇ Al ⁇ Ga 1- ⁇ - ⁇ N (0 ⁇ , 0 ⁇ ⁇ , ⁇ + ⁇
  • a layer composed of ⁇ 1) or a layer to which a p-type impurity is added as in this embodiment is preferable.
  • the lattice constant of the two-dimensional electron gas elimination layer is different from the lattice constant of the carrier traveling layer, which is the thickest layer, it is preferable to set it to a critical film thickness or less where dislocation occurs.
  • the low resistance layer 106 is an unstrained or compressive strained n-type In y Ga 1-y N (0 ⁇ y ⁇ 1), or In m Al l Ga 1-ml N (0 ⁇ m, 0 ⁇ l, m + l ⁇ 1).
  • the thickness be equal to or less than the critical film thickness at which dislocation occurs.
  • the impurity concentration is desirably 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the impurity concentration of the two-dimensional electron gas elimination layer is desirably 1 ⁇ 10 18 cm ⁇ 3 or less.
  • Mg is added as a p-type impurity in the InGaN two-dimensional electron gas elimination layer 105.
  • the two-dimensional electron gas can be eliminated only by the piezo effect of InGaN itself, it is not necessary to add Mg.
  • the two-dimensional electron gas elimination layer 105 for example, Be, C, Mg, or the like can be added as an n-type impurity, for example, a p-type impurity such as Si, S, or Se.
  • the added impurity is preferably p-type.
  • Si is added as an n-type impurity in the GaN low-resistance layer 106, but as an n-type impurity, for example, Be, C, Mg, or the like is added as a p-type impurity such as Si, S, or Se. It is possible. However, in this embodiment, since it is conduction by electrons, it is desirable to add an n-type impurity in order to reduce the resistance.
  • Nb / Al / Nb / Au is used as the source electrode 107 and the drain electrode 108.
  • the source electrode and the drain electrode are in ohmic contact with the AlGaN serving as the carrier supply layer 104 and the low resistance layer 106.
  • metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used. Or it can also be set as the structure which laminated
  • Ni / Au is used as the gate electrode 110.
  • a desired metal can be used. However, it is desirable not to react with the gate insulating film.
  • an Al 2 O 3 film is used as the gate insulating film 109.
  • the gate insulating film 109 any one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr, and O and N are used. There exists a substance which consists of any one or more of these.
  • FIG. 2 is a diagram schematically showing a cross-sectional structure of the second embodiment of the present invention.
  • the field effect transistor of the present embodiment includes a buffer layer 202 made of a first GaN-based semiconductor, a carrier traveling layer 203 made of a second GaN-based semiconductor, and a third GaN-based material on a substrate 201.
  • a carrier supply layer 204 made of a semiconductor, a two-dimensional electron gas elimination layer 205 made of a fourth GaN-based semiconductor, and a low resistance layer 206 made of a fifth GaN-based semiconductor are formed.
  • the two-dimensional electron gas elimination layer 205 and the low resistance layer 206 are removed by recess etching between the drain electrode and the gate electrode and in a region below the gate electrode and a part below the gate electrode. At this time, the side surfaces of the remaining two-dimensional electron gas elimination layer 205 and low resistance layer 206 are formed so as to be substantially perpendicular to the surface before removal.
  • a source electrode 207 is in contact with the low resistance layer 206 and a drain electrode 208 is formed in contact with the carrier supply layer 204.
  • a gate insulating film 209 is formed, and a gate electrode 210 is formed.
  • a field effect transistor is manufactured by forming a protective film 211.
  • the substrate 201 for example, sapphire, silicon carbide, GaN, AlN or the like is used.
  • the first to fifth GaN-based semiconductors are also indicated by reference numerals 202 to 206, respectively.
  • Examples of the first GaN-based semiconductor 202 include GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, a nucleation layer made of GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, or the like may be sandwiched between the substrate 201 and the first semiconductor 202 in order to form the first semiconductor.
  • the first GaN-based semiconductor 202 As an n-type impurity, for example, Si, S, Se, etc. As the p-type impurity, for example, Be, C, Mg, or the like can be added.
  • n-type impurity for example, Si, S, Se, etc.
  • p-type impurity for example, Be, C, Mg, or the like can be added.
  • the second GaN-based semiconductor 203 for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors are used.
  • the impurity concentration in the second GaN-based semiconductor 203 is desirably 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the third GaN-based semiconductor 204 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. However, in the embodiment of the present invention, the material or composition has a smaller electron affinity than that of the second GaN-based semiconductor.
  • n-type impurity for example, Si, S, Se, etc.
  • p-type impurity for example, Be, C, Mg, or the like can be added.
  • the fourth GaN-based semiconductor 205 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors.
  • the fourth GaN-based semiconductor 205 needs to have a function of eliminating the two-dimensional electron gas, so that a substance capable of inducing a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer or Composition.
  • the fourth GaN-based semiconductor 205 As an n-type impurity, for example, Si, S, Se, etc. As the p-type impurity, for example, Be, C, Mg, or the like can be added.
  • n-type impurity for example, Si, S, Se, etc.
  • p-type impurity for example, Be, C, Mg, or the like can be added.
  • the fifth GaN-based semiconductor 206 includes, for example, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors.
  • the fifth GaN-based semiconductor 206 for example, Si, S, Se, etc. can be used as n-type impurities.
  • the p-type impurity for example, Be, C, Mg or the like can be added, but the conductivity type is n-type.
  • the gate insulating film 209 there is a substance including any one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and any one or more of O and N.
  • the protective film 211 there is a substance composed of one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and one or more of O and N, or an organic material.
  • FIG. 2 is a diagram schematically showing a cross-sectional configuration of the second embodiment of the present invention.
  • the field effect transistor of this example is As the substrate 201, a silicon carbide (SiC) substrate, As the first GaN-based semiconductor 202, an AlGaN layer (Al composition ratio 0.1, film thickness 1000 nm), As the second GaN-based semiconductor 203, a GaN carrier traveling layer (film thickness 40 nm), As the third GaN-based semiconductor 204, an AlGaN carrier supply layer (Al composition ratio 0.25, film thickness 15 nm), As the fourth GaN-based semiconductor 205, a GaN two-dimensional electron gas elimination layer (film thickness 10 nm, Mg-doped 1 ⁇ 10 18 cm ⁇ 3 ), As the fifth GaN-based semiconductor 206, an epitaxial substrate made of a GaN low resistance layer (film thickness: 30 nm, Si-doped 1 ⁇ 10 19 cm ⁇ 3 ) is used.
  • a 200 nm SiO 2 film is formed on the epitaxial substrate, and a recess portion of the SiN film is opened by ICP dry etching using, for example, SF 6 as a process gas using a photoresist as a mask.
  • recess etching is performed by using, for example, ICP dry etching using a mixed gas of BCl 3 and O 2 as a process gas, using the SiO 2 film as a mask, and the two-dimensional electron gas elimination layer 205, the low resistance layer 206 is removed.
  • the side surfaces of the SiO 2 film are hardly etched, so that the side surfaces of the two-dimensional electron gas elimination layer 205 and the low resistance layer 206 are almost vertical.
  • the etching stops when O is bonded to the surface of the AlGaN carrier supply layer the two-dimensional electron gas elimination layer 205 and the low resistance layer 206 can be selectively removed.
  • the SiO 2 film is removed using an HF aqueous solution, and Ti / Al / Nb / Au (film thickness 15 nm / 60 nm / 35 nm / 50 nm, heat treatment 850 ° C., 30 seconds) is used as the source electrode 207 and the drain electrode 208.
  • Ti / Al / Nb / Au film thickness 15 nm / 60 nm / 35 nm / 50 nm, heat treatment 850 ° C., 30 seconds
  • the two-dimensional electron gas elimination layer between the two-dimensional electron gas and the low resistance layer serves as a barrier, when the gate voltage is 0 V, a current flows between the two-dimensional electron gas and the low resistance layer.
  • a gate voltage of +3 V or higher was applied, the device was turned on and a good enhancement mode was realized.
  • the resistance of the GaN low-resistance layer doped with Si at a high density of 1 ⁇ 10 19 cm ⁇ 3 is very low, so that a low source resistance can be realized.
  • the low resistance layer 206 exists only between the source electrode 207 and the gate electrode 210 and does not exist on the side of the drain electrode to which a high voltage is applied during high voltage operation, a high voltage with an operating voltage of 50 V or more is achieved while having a low source resistance. I was able to work.
  • the region works to alleviate electric field concentration. Suitable for voltage operation.
  • SiC is used as the substrate, but any other substrate such as Si or sapphire can be used.
  • an AlGaN layer is used as the buffer layer 202, but a GaN layer such as GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used as the buffer layer.
  • a GaN layer is used as the carrier traveling layer 203, but as the carrier traveling layer, GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used.
  • the lattice constant of the carrier traveling layer 203 is different from the lattice constant of the AlGaN buffer layer 202 which is the thickest layer, it is preferable to set the critical film thickness to be less than the critical film thickness at which dislocation occurs.
  • an AlGaN layer is used as the carrier supply layer 204, but as the carrier supply layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like can be used.
  • the electron affinity of the carrier supply layer 204 needs to be a material or composition smaller than the electron affinity of the carrier traveling layer.
  • the carrier supply layer 204 since the lattice constant of the carrier supply layer 204 is different from the lattice constant of the AlGaN buffer layer, which is the thickest layer, it is preferable that the carrier supply layer 204 be less than the critical film thickness at which dislocation occurs.
  • the two-dimensional electron gas elimination layer 205 is used as the two-dimensional electron gas elimination layer 205.
  • the two-dimensional electron gas elimination layer is an InAlN layer, such as GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors. Can be used.
  • the fourth GaN-based semiconductor (two-dimensional electron gas elimination layer) 205 needs to work to eliminate the two-dimensional electron gas, a negative charge is induced at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer. It is necessary to be a material or a composition that can be used. Depending on the composition of the carrier running layer and the carrier supply layer, for example, unstrained or compressive strained GaN, or compressive strained In ⁇ Al ⁇ Ga 1- ⁇ - ⁇ N ( A layer composed of 0 ⁇ , 0 ⁇ ⁇ , ⁇ + ⁇ ⁇ 1) or a layer to which a p-type impurity is added as in this embodiment is preferable.
  • the lattice constant of the two-dimensional electron gas elimination layer is different from the lattice constant of the AlGaN buffer layer which is the thickest layer.
  • a GaN layer is used as the low resistance layer 206, but the low resistance layer is an unstrained or compressive strain n-type In y Ga 1-y N (0 ⁇ y ⁇ 1) or In m AllGa. 1-ml N (0 ⁇ m, 0 ⁇ l, m + l ⁇ 1).
  • the impurity concentration is desirably 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the impurity concentration of the two-dimensional electron gas elimination layer 205 is desirably 1 ⁇ 10 18 cm ⁇ 3 or less.
  • Mg was added as a p-type impurity in the GaN two-dimensional electron gas elimination layer 205.
  • the GaN layer in this example is subjected to compressive strain, and the electron supply capability of the AlGaN carrier supply layer is low. Therefore, it is possible to eliminate the two-dimensional electron gas without converting Mg.
  • the two-dimensional electron gas elimination layer 205 As an n-type impurity, for example, Si, S, Se, etc. As the p-type impurity, for example, Be, C, Mg or the like can be added. However, if the n-type impurity concentration in the carrier supply layer is increased, it is difficult to eliminate the two-dimensional electron gas between the source electrode and the gate electrode, so that the added impurity is preferably p-type.
  • n-type impurities and Si were added to the GaN low resistance layer 206.
  • an n-type impurity for example, Si, S, Se, etc.
  • the p-type impurity for example, Be, C, Mg or the like can be added.
  • it is conduction by electrons it is desirable to add an n-type impurity in order to reduce the resistance.
  • Ti / Al / Nb / Au is used as the source electrode 207 and the drain electrode 208.
  • the source electrode and the drain electrode are in ohmic contact with the AlGaN and the low resistance layer 206 which are the carrier supply layer 204 in this embodiment.
  • Any metal can be used as long as it is in contact with each other, and for example, metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the metals are stacked can be used.
  • Ni / Au is used as the gate electrode 210.
  • a desired metal can be used. However, it is desirable not to react with the gate insulating film.
  • a SiN film is used as the gate insulating film 209.
  • the gate insulating film 209 any one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and any of O and N are used. One or more substances may be used.
  • FIG. 4 is a diagram schematically showing a cross-sectional configuration of the third embodiment of the present invention.
  • the field effect transistor of this example is As the substrate 301, a silicon (Si) substrate, AlN layer (film thickness 150 nm) as the nucleation layer 312, As the first GaN-based semiconductor 302, a GaN layer (film thickness 1500 nm), As the second GaN-based semiconductor 303, an InGaN carrier traveling layer (In composition ratio 0.04, film thickness 25 nm), As the third GaN-based semiconductor 304, an InAlN carrier supply layer (Al composition ratio 0.83, film thickness 15 nm), As the fourth GaN-based semiconductor 305, an InGaN two-dimensional electron gas elimination layer (In composition ratio 0.15, film thickness 10 nm), As the fifth GaN-based semiconductor 306, an epitaxial substrate made of an AlGaN low resistance layer (Al composition ratio 0.05, film thickness 50 nm, Si-doped 1 ⁇ 10 19 cm ⁇
  • a 200 nm SiO 2 film is formed on the epitaxial substrate, and a recess portion of the SiN film is opened by ICP dry etching using, for example, SF 6 as a process gas using a photoresist as a mask. After removing the photoresist, recess etching is performed by using, for example, ICP dry etching using BCl 3 gas as a process gas with the SiO 2 film as a mask, and the low resistance layer 306 is removed.
  • a 200 nm SiO 2 film is formed, and the recess portion of the SiN film is opened by ICP dry etching using, for example, SF 6 as a process gas, using the photoresist as a mask.
  • recess etching is performed using, for example, ICP dry etching using a mixed gas of BCl 3 gas and O 2 as a process gas, using the SiO 2 film as a mask, and the two-dimensional electron gas elimination layer 305 is removed. To do.
  • the side surfaces of the SiO 2 film are hardly etched, so the side surfaces of the two-dimensional electron gas elimination layer 305 and the low resistance layer 306 are almost vertical.
  • the two-dimensional electron gas elimination layer 305 can be selectively removed.
  • the SiO 2 film is removed using an HF aqueous solution, and Ti / Al / Nb / Au (film thickness 15 nm / 60 nm / 35 nm / 50 nm, heat treatment 850 ° C., 30 seconds) is formed as the source electrode 307 and the drain electrode 308. .
  • the resistance of the AlGaN low-resistance layer doped with Si at a high density of 1 ⁇ 10 19 cm ⁇ 3 is very low, so that a low source resistance can be realized.
  • the low resistance layer exists only between the source electrode and the gate electrode and does not exist on the drain electrode side to which a high voltage is applied during high voltage operation, the high voltage operation with an operation voltage of 50 V or more is achieved while having a low source resistance. I was able to.
  • the two-dimensional electron gas elimination layer 305 When the two-dimensional electron gas elimination layer 305 is included in a part of the semiconductor layer opposed to each other with the gate electrode 310 and the insulating film 309 interposed therebetween as in the embodiment shown in FIG. 4, the two-dimensional electron gas is not formed in that region. Good pinch-off characteristics can be realized. However, depending on the position of the gate electrode and the two-dimensional electron gas elimination layer, it is difficult to flow electrons even in the on state, so care must be taken.
  • the semiconductor layers facing each other with the gate electrode 310 and the insulating film 309 interposed therebetween are the low resistance layer 306, the two-dimensional electron gas elimination layer 305, and the carrier supply layer 304.
  • the region facing the carrier supply layer 304 serves to alleviate electric field concentration
  • the region facing the two-dimensional electron gas supply layer 305 serves to achieve good pinch-off properties.
  • Si is used as the substrate, but any other substrate such as SiC or sapphire can be used.
  • a GaN layer is used as the buffer layer 302, but as the buffer layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like can be used.
  • an InGaN layer is used as the carrier traveling layer 303.
  • the carrier traveling layer GaN, InN, AlN, and a mixture of the above three types of GaN-based semiconductors can be used.
  • the lattice constant of the carrier traveling layer is different from the lattice constant of the GaN buffer layer, which is the thickest layer, in this embodiment, it is preferable to set it to a critical film thickness or less where dislocation occurs.
  • an InAlN layer is used as the carrier supply layer, but as the carrier supply layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like can be used.
  • the electron affinity of the carrier supply layer needs to be a material or composition smaller than the electron affinity of the carrier running layer.
  • the carrier supply layer since the lattice constant of the carrier supply layer is slightly different from the lattice constant of the GaN buffer layer, which is the thickest layer, it is preferable that the carrier supply layer be less than the critical film thickness at which dislocation occurs.
  • an InGaN layer was used as the two-dimensional electron gas elimination layer, but as the carrier supply layer, GaN, InN, AlN, a mixture of the above three types of GaN-based semiconductors, and the like were used. Can do.
  • the fourth GaN-based semiconductor 305 needs to work to eliminate the two-dimensional electron gas, the fourth GaN-based semiconductor 305 needs to be a substance or composition that can induce a negative charge at the interface between the two-dimensional electron gas elimination layer and the carrier supply layer.
  • the carrier running layer 303 and the carrier supply layer 304 for example, unstrained or compressive strained GaN, or compressive strained In ⁇ Al ⁇ Ga 1- ⁇ - ⁇ N (0 ⁇ , 0 ⁇
  • the lattice constant of the two-dimensional electron gas elimination layer is different from the lattice constant of the GaN buffer layer, which is the thickest layer.
  • an AlGaN layer is used as the low resistance layer.
  • the low resistance layer may be an unstrained or compressive strained n-type In y Ga 1-y N (0 ⁇ y ⁇ 1) or In m Al l Ga 1-ml N (0 ⁇ m, 0 ⁇ l, m + l ⁇ 1).
  • the impurity concentration is desirably 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the impurity concentration of the two-dimensional electron gas elimination layer is desirably 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the two-dimensional electron gas elimination layer has n-type impurities, for example, p-type impurities such as Si, S, Se, for example Be, C, etc. Mg or the like can be added.
  • the added impurity is preferably p-type.
  • Si was added as an n-type impurity in the AlGaN low resistance layer.
  • an n-type impurity for example, Si, S, Se, etc.
  • the p-type impurity for example, Be, C, Mg or the like can be added.
  • it is conduction by electrons it is desirable to add an n-type impurity in order to reduce the resistance.
  • Ti / Al / Nb / Au is used as the source electrode 307 and the drain electrode 308.
  • the source electrode and the drain electrode are in ohmic contact with InAlN and the low resistance layer 306 which are the carrier supply layers 304 in this embodiment.
  • Any metal can be used as long as it is in contact with each other, and for example, metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the metals are stacked can be used.
  • Ni / Au is used as the gate electrode 310.
  • a desired metal can be used. However, it is desirable not to react with the gate insulating film.
  • a SiN film is used as the gate insulating film 309.
  • the gate insulating film 309 one or more of Si, Mg, Hf, Al, Ti, Ta, and Zr and any of O and N are used. There are substances consisting of one or more.
  • Patent Document 1 above is incorporated herein by reference.
  • the embodiments and examples can be changed and adjusted based on the basic technical concept.
  • Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

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Abstract

L'invention concerne un dispositif à semiconducteurs présentant une faible résistance de source, capable d’effectuer une excellente action de renforcement pour une action à haute tension. Par-dessus un substrat (101), on forme une couche tampon (102) constituée d’un premier semiconducteur de la famille GaN, une couche (103) de transit des porteurs constituée d’un deuxième semiconducteur de la famille GaN, d’une couche (104) d’amenée de porteurs constituée d’un troisième semiconducteur de la famille GaN, d’une couche (105) de dissolution de gaz électronique bidimensionnel qui est constituée d’un quatrième semiconducteur de la famille GaN et élève la bande de conduction de la couche d’amenée de porteurs en la rapprochant de l’ordre du vide de telle sorte qu’un gaz électronique bidimensionnel ne puisse pas s’accumuler dans la couche de transit des porteurs, et une couche (106) à faible résistance constituée d’un cinquième semiconducteur de la famille GaN.  La couche (105) de dissolution du gaz électronique bidimensionnel et la couche (106) à faible résistance sont éliminées par attaque en creux au niveau des zones situées entre une électrode de drain et une électrode de grille et au niveau des zones situées au-dessous d’une partie inférieure de l’électrode de grille et une électrode (108) de drain. Ensuite, les faces latérales restantes de la couche (105) de dissolution du gaz électronique bidimensionnel et de la couche (106) à faible résistance sont formées de telle sorte qu’elles ne soient pas normales aux surfaces avant l’élimination, mais inclinées par rapport à celles-ci. Une électrode (107) de source est formée en contact avec la couche (106) à faible résistance, et l’électrode (108) de drain est formée en contact avec la couche d’amenée de porteurs (104).  Puis un film (109) d’isolation de grille est formé afin de former une électrode (110) de grille. Enfin, un film (111) de protection est formé afin de fabriquer un transistor à effet de champ.
PCT/JP2009/064000 2008-08-07 2009-08-07 Dispositif à semiconducteurs WO2010016564A1 (fr)

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CN113169228A (zh) * 2018-10-12 2021-07-23 创世舫科技有限公司 包括垂直栅极模块的横向iii族氮化物器件
KR20200094008A (ko) * 2019-01-29 2020-08-06 한국과학기술원 이종접합 구조의 수직형 트랜지스터 및 그 제조 방법
KR102198765B1 (ko) * 2019-01-29 2021-01-05 한국과학기술원 이종접합 구조의 수직형 트랜지스터 및 그 제조 방법

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