WO2010001505A1 - 電子部品 - Google Patents

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Publication number
WO2010001505A1
WO2010001505A1 PCT/JP2009/000670 JP2009000670W WO2010001505A1 WO 2010001505 A1 WO2010001505 A1 WO 2010001505A1 JP 2009000670 W JP2009000670 W JP 2009000670W WO 2010001505 A1 WO2010001505 A1 WO 2010001505A1
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WO
WIPO (PCT)
Prior art keywords
wire bonding
die bond
electronic component
terminal
semiconductor element
Prior art date
Application number
PCT/JP2009/000670
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
大野和幸
田中祥雄
中島清
鞍谷直人
前川智史
Original Assignee
オムロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Priority to EP09773083A priority Critical patent/EP2187437A1/en
Priority to US12/674,694 priority patent/US8274797B2/en
Priority to CN200980100230A priority patent/CN101785100A/zh
Publication of WO2010001505A1 publication Critical patent/WO2010001505A1/ja

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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive

Definitions

  • the present invention relates to an electronic component. Specifically, the present invention relates to an electronic component in which a semiconductor element such as a sensor chip or an electronic circuit is mounted on a substrate.
  • Patent Document 1 As an electronic component in which a semiconductor element is mounted on a package and covered with a cap, for example, there is one disclosed in Patent Document 1 (3-axis acceleration sensor).
  • the package 12 is configured by a cavity substrate having a recess 13 formed in the center of the upper surface, and a semiconductor element 14 is formed on the bottom surface in the recess 13. Is fixed with a die-bond resin.
  • a terminal pattern 15 for wire bonding is provided at a position higher than the surface to which the semiconductor element 14 is bonded, that is, around the recess 13.
  • the terminals of the semiconductor element 14 are connected to the terminal patterns 15 of the package 12 by bonding wires 16.
  • the cap 17 is overlapped and bonded to the package 12, and the semiconductor element 14 is confined within the package 12 and the cap 17.
  • the die bond resin bonding the semiconductor element 14 to the bottom surface of the recess 13 does not flow on the terminal pattern 15. Therefore, it is possible to prevent a film from being formed on the terminal pattern 15 by the die bond resin that has flowed out, and when bonding the bonding wire 16 to the terminal pattern 15, the film of the die bond resin prevents the wire pattern from being generated. Can be suppressed.
  • the die bonding resin is applied to the wire bonding terminal surface because the die bonding resin coating surface and the wire bonding terminal surface are the same surface. It may flow to the surface and contaminate the terminal surface, which may cause wire bonding failure. That is, even if the application amount of the die bond resin is accurately controlled or the pressing force of the semiconductor element 14 is controlled to be constant, the semiconductor depends on the time until the applied die bond resin is cured and the temperature of the external environment. The amount of die bond resin flowing out from the lower surface of the element 14 varies.
  • a flexible resin such as silicone is often used in order to mitigate the characteristic variation factor due to vibrations from the outside of the semiconductor element.
  • the resin When such a resin is used, the resin further flows. It becomes easy. As a result, the die bond resin that has flowed out adheres to the terminal surface for wire bonding and a film is formed on the terminal surface, which may be hindered by the film and cannot bond the bonding wire to the terminal surface.
  • the present invention has been made in view of such a technical problem, and an object of the present invention is to provide an electronic component that is unlikely to cause bonding wire connection failure even when an inexpensive printed board is used. There is.
  • a semiconductor element is bonded and fixed to a die bond portion of a printed board using a die bond resin, and a wire bonding terminal formed by a conductor pattern of the printed board is connected to the semiconductor element by a bonding wire.
  • a groove portion lower than the conductor pattern of the printed circuit board is formed in at least a region located on the die bond portion side in a region surrounding the wire bonding terminal.
  • a groove portion lower than the conductor pattern of the printed circuit board is formed at least in a region located on the die bond portion side in a region surrounding the wire bonding terminal, a semiconductor element is formed in the die bond portion. Even if the die bond resin flows out from the die bond part when mounting the die bond resin, the die bond resin that has flowed to the wire bonding terminal side can be captured by the groove, and the die bond resin is prevented from adhering to the surface of the wire bonding terminal. it can. Therefore, there is no fear that a film can be formed on the surface of the wire bonding terminal by the die bonding resin, and the wire bonding to the wire bonding terminal can be surely performed, and the wire bonding defect can be reduced.
  • the groove is formed on the entire circumference of the region surrounding the wire bonding terminal. According to this embodiment, since the groove portion is formed so as to surround the wire bonding terminal, the die bond resin that reaches the wire bonding terminal so as to go around from the die bonding portion can also be captured by the groove portion.
  • the groove is formed by removing a conductor pattern of the printed board. According to such an embodiment, since the groove portion can be formed by the portion from which the conductor pattern is removed, the groove portion can be formed easily and inexpensively.
  • the groove is formed by further removing a substrate core material of the printed board. According to this embodiment, since the groove portion is formed by removing the conductor pattern and the substrate core material, the groove portion can be deepened, and even when the amount of the die bond resin flowing out from the die bond portion is large, It is possible to prevent the die bond resin from adhering to the surface.
  • Still another embodiment of the electronic component according to the present invention is such that the surface of the wire bonding terminal is plated with Au. Since the die bond resin has poor wettability with respect to Au plating, the die bond resin is more difficult to adhere onto the wire bonding terminal by flipping the die bond resin that has flowed into the groove portion with the Au plating.
  • the means for solving the above-described problems in the present invention has a feature in which the above-described constituent elements are appropriately combined, and the present invention enables many variations by combining such constituent elements. .
  • FIG. 1 is a cross-sectional view illustrating an embodiment of an electronic component disclosed in Patent Document 1.
  • FIG. 2 is a cross-sectional view showing the structure of the electronic component according to Embodiment 1 of the present invention.
  • 3A is a plan view of a portion X in FIG. 2, and FIG. 3B is an enlarged cross-sectional view of the portion X in FIG.
  • FIG. 4 is a plan view of the electronic component with the conductive cap removed.
  • FIG. 5A is a plan view showing a part of an electronic component according to Embodiment 2 of the present invention, and FIG. 5B is an enlarged sectional view thereof.
  • FIG. 6A is a plan view showing a part of an electronic component according to Embodiment 3 of the present invention, and FIG. 6B is an enlarged sectional view thereof.
  • FIG. 7A is a plan view showing a part of an electronic component according to Embodiment 4 of the present invention, and FIG. 7B is an enlarged sectional view thereof.
  • FIG. 2 is a cross-sectional view showing the structure of the electronic component according to Embodiment 1 of the present invention
  • FIG. 3 (a) is a plan view of a portion X in FIG. 2
  • FIG. 3 (b) is an enlarged cross-sectional view of the portion X in FIG. is there.
  • FIG. 4 is a plan view of the electronic component with the conductive cap removed.
  • the electronic component 51 shown here is obtained by mounting a semiconductor element 53 on the upper surface of a substrate 52 and placing the semiconductor element 53 in a package (Faraday cage) made up of the substrate 52 and a conductive cap 54.
  • the substrate 52 is composed of a printed circuit board, and a conductive pattern obtained by patterning a metal thin film such as Cu is provided on the upper and lower surfaces of the insulating substrate core material 52a. As shown in FIG. 4, a die bond portion 55, a wire bonding terminal 56, a ground electrode 57, and a surface-side ground pattern 58 are formed on the upper surface of the substrate 52 by a conductor pattern.
  • the wire bonding terminal 56 is a terminal for supplying power to the semiconductor element 53 through the bonding wire 69 or inputting / outputting a signal.
  • a plurality of wire bonding terminals 56 are provided.
  • the periphery of the wire bonding terminal 56 is separated from the surface-side ground pattern 58 by a groove 60 (gap).
  • the groove portion 60 on the upper surface side means a region where at least a part of the conductor pattern is removed and becomes lower than the upper surface of the conductor pattern.
  • the groove portion 60 on the upper surface side is a region where the conductor patterns are separated and the substrate core material 52a is exposed on the bottom surface.
  • the groove part 60 is formed by etching a metal thin film, the width thereof is about 0.10 mm, and the groove depth is 0.02 to 0.03 mm.
  • the wire bonding terminal 56 is disposed in the vicinity of the die bond portion 55, and the surface thereof is covered with the Au plating 61.
  • the die bond portion 55, the ground electrode 57, and the surface side ground pattern 58 are continuous and connected to each other.
  • the ground electrode 57 is a region for joining the conductive cap 54.
  • the ground electrode 57 is formed on the outer peripheral portion of the substrate 52 and surrounds the die bond portion 55, the wire bonding terminal 56, and the surface side ground pattern 58.
  • the surface of the ground electrode 57 is covered with Au plating 61.
  • the die bond part 55 is an area for mounting the semiconductor element 53.
  • the surface-side ground pattern 58 is a region other than the die bond portion 55, the ground electrode 57, and the wire bonding terminal 56 in the conductor pattern on the upper surface.
  • the die bond portion 55 is defined in a region surrounded by the surface-side ground pattern 58, and the surfaces of the die bond portion 55 and the surface-side ground pattern 58 are covered with a solder resist 67.
  • the solder resist 67 is cured by heating after applying a uniform thickness to the surface of the substrate 52 by screen printing a molten solder resist. A silk screen can be used in place of the solder resist 67.
  • a plurality of extraction electrodes 62 and a back side ground pattern 63 are provided on the lower surface of the substrate 52 by a conductor pattern.
  • the back surface side ground pattern 63 covers almost the entire region where the extraction electrode 62 is not present, and the extraction electrode 62 and the back surface side ground pattern 63 are separated from each other by the groove 64.
  • the lead electrode 62 and the back surface side ground pattern 63 are patterns for solder mounting on a substrate (for example, a mother board for a mobile phone) on which the electronic component 51 is mounted, and the surface is plated with Au.
  • the substrate core material 52 a is provided with through holes 65 and 66 so as to penetrate the front and back surfaces, and each wire bonding terminal 56 is electrically connected to each lead electrode 62 through the through hole 65.
  • the die bond portion 55, the front surface side ground pattern 58, and the ground electrode 57 that are integrally continuous are connected to the back surface side ground pattern 63 by a through hole 66.
  • the semiconductor element 53 is an element such as a sensor chip for various sensing (for example, an acoustic sensor, an acceleration sensor, a pressure sensor, etc.), an LSI, or an ASIC.
  • the lower surface of the semiconductor element 53 is bonded and fixed on the die bond portion 55 with a die bond resin 68.
  • An adhesive resin such as silicone having flexibility is used as the die bond resin 68.
  • the semiconductor element 53 is formed thereon. Is pressed with an equal force, the die bond resin 68 is heated and cured, and the semiconductor element 53 is fixed.
  • the die bond resin 68 not only fixes the semiconductor element 53 but also functions to block extra force from the external environment due to its flexibility.
  • each terminal of the semiconductor element 53 is electrically connected to each extraction electrode 62 on the lower surface.
  • the conductor pattern can be freely designed as appropriate according to the form of the semiconductor element or electrical / electronic component to be mounted.
  • the conductive cap 54 is formed in a cap shape by a metal material having a small specific resistance, and a space for accommodating the semiconductor element 53 and the like is formed on the lower surface.
  • a flange 70 extending substantially horizontally is formed on the entire periphery of the lower end of the conductive cap 54.
  • the conductive cap 54 is placed on the substrate 52 so as to cover the semiconductor element 53 and the like, and the lower surface of the flange 70 is bonded and fixed to the ground electrode 57 by the conductive bonding member 71 and the conductive bonding member 71 conducts electricity. Depending on the nature, it is electrically connected to the ground electrode 57. Therefore, the conductive cap 54 has the same potential (ground potential) as the back surface side ground pattern 63 on the lower surface.
  • a material such as a conductive epoxy resin (for example, an epoxy resin containing a silver filler) or solder is used.
  • the semiconductor element 53 to be mounted is an acoustic sensor or the like
  • a hole (not shown) for allowing acoustic vibration to pass through the conductive cap 54 may be provided.
  • the package including the conductive cap 54 and the substrate 52 may have a sealed structure according to the type of the semiconductor element 53 to be accommodated. For example, when it is sufficient to block dust, light, etc. from the outside, it is only necessary to cover the semiconductor element 53 etc. with a package, and airtightness is not necessarily required, but moisture resistance and chemical resistance are required. For this reason, it is desirable that the package be airtight.
  • a Faraday cage is constituted by the conductive cap 54 connected to the ground and the substrate 52 having the back side ground pattern 63 and the front side ground pattern 58 connected to the ground.
  • the semiconductor element 53 can be blocked from external high-frequency noise, and the influence of the semiconductor element 53 due to external noise can be reduced.
  • the substrate 52 since the substrate 52 is almost entirely covered with the conductor pattern on both the upper surface and the lower surface, the substrate 52 can be prevented from warping due to a temperature change or the like.
  • the solder resist 67 is applied to the area where the Au plating 61 is not applied, so that the area where the conductor pattern need not be electrically joined is protected by an inexpensive material. Because. Furthermore, since the die bond resin 68 such as silicone has a higher adhesive strength to the solder resist than to the Au plating, the adhesive strength of the semiconductor element 53 by the die bond resin 68 is increased by covering the die bond portion 55 with the solder resist 67. Can be high.
  • the electronic component 51 it is possible to reduce wire bonding defects in the wire bonding terminal 56.
  • the die bond resin 68 flowing out from the die bond portion 55 forms a film on the wire bonding terminal 56 to cause a wire bonding failure.
  • a wire bonding failure is caused. The reason why it can be reduced will be described below.
  • the narrow groove portion 60 is provided so as to surround the wire bonding terminal 56 as described above. Therefore, even when the die bond resin 68 flows out from the die bond portion 55 toward the wire bonding terminal 56 at the time of die bonding, when the die bond resin 68 reaches the groove portion 60, it is sucked into the groove portion 60 by capillary action. Since the die bond resin 68 sucked into the groove portion 60 spreads along the groove portion 60, it is possible to prevent a film from being formed on the wire bonding terminal 56 beyond the groove portion 60.
  • the groove width is set to about 0.1 mm. However, the narrower groove width makes it easier to suck the die bond resin 68 due to the capillary phenomenon. It may be narrowed.
  • the wire bonding terminal 56 it is possible to prevent the wire bonding terminal 56 from becoming dirty with the die bond resin 68 and forming a coating film. Therefore, when bonding the bonding wire 69 to the wire bonding terminal 56 is not hindered by the coating film, the wire bonding failure is reduced. Can be made. Further, since it is not necessary to increase the distance between the die bond portion 55 and the wire bonding terminal 56, the length of the bonding wire 69 can be shortened, and the increase in cost can be suppressed.
  • the through hole 65 for connecting the wire bonding terminal 56 and the lead electrode 62 is provided at a position away from the portion where the bonding wire 69 is joined. This is to prevent the through hole 65 from being damaged by ultrasonic vibration during wire bonding.
  • FIG. 5A is a plan view showing a part of an electronic component according to Embodiment 2 of the present invention
  • FIG. 5B is an enlarged sectional view thereof.
  • a part of the groove portion 60 is filled with the solder resist 67 on the side far from the die bonding portion 55 and the wire bonding terminal 56.
  • a part is covered with a solder resist 67.
  • the region not used for wire bonding in the wire bonding terminal 56 is covered with the solder resist 67, the area of the Au plating region of the wire bonding terminal 56 can be reduced, and the cost of the substrate 52 can be reduced. Can be lowered.
  • the groove 60 is not covered with the solder resist 67 in the direction in which the die bond resin 68 flows, the die bond resin 68 can be sucked and a film is formed on the wire bonding terminal 56 with the die bond resin 68. Can be prevented.
  • FIG. 6A is a plan view showing a part of an electronic component according to Embodiment 3 of the present invention
  • FIG. 6B is an enlarged sectional view thereof.
  • This embodiment is a case of a wire bonding terminal 76 for ground.
  • the ground wire bonding terminal 76 is connected to the back surface side ground pattern 63 on the lower surface by a through hole 66.
  • a groove 60 is formed along the side close to the die bond portion 55 (the direction in which the die bond resin 68 flows) and both sides, and the die bond portion of the wire bonding terminal 76 is formed.
  • the side far from 55 is connected to the surface-side ground pattern 58 or the ground electrode 57.
  • Au plating 61 is applied to the surface of the wire bonding terminal 76 (region exposed from the solder resist 67).
  • the ground terminal of the semiconductor element 53 and the wire bonding terminal 76 are connected by a bonding wire 69.
  • the groove portion 60 is not closed in an annular shape, but the die bond portion 55 that has flowed is sucked by the groove portion 60 on the side close to the die bond portion 55, and the portion without the groove portion 60 is a place far from the die bond portion 55 Since the die bond resin 68 is difficult to reach and reach, the influence of the effect of preventing the die bond resin 68 from forming a film on the wire bonding terminal 76 is small.
  • FIG. 7A is a plan view showing a part of an electronic component according to Embodiment 4 of the present invention
  • FIG. 7B is an enlarged sectional view thereof.
  • the conductor pattern is removed to form the groove 60
  • the underlying substrate core material 52a is removed to deepen the groove 60.
  • the amount of resin stored in the groove 60 can be increased by increasing the depth of the groove 60.
  • the die bond resin 68 is sucked by capillary action as in the case of increasing the amount of resin to be stored by widening the groove width of the groove 60. There is no fear of power loss.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
PCT/JP2009/000670 2008-07-02 2009-02-18 電子部品 WO2010001505A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP09773083A EP2187437A1 (en) 2008-07-02 2009-02-18 Electronic component
US12/674,694 US8274797B2 (en) 2008-07-02 2009-02-18 Electronic component
CN200980100230A CN101785100A (zh) 2008-07-02 2009-02-18 电子零件

Applications Claiming Priority (2)

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JP2008173383A JP5458517B2 (ja) 2008-07-02 2008-07-02 電子部品
JP2008-173383 2008-07-02

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EP (1) EP2187437A1 (zh)
JP (1) JP5458517B2 (zh)
KR (1) KR20100031775A (zh)
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WO (1) WO2010001505A1 (zh)

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CN110930879A (zh) * 2019-11-25 2020-03-27 武汉华星光电半导体显示技术有限公司 一种显示装置

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