CN101785100A - 电子零件 - Google Patents
电子零件 Download PDFInfo
- Publication number
- CN101785100A CN101785100A CN200980100230A CN200980100230A CN101785100A CN 101785100 A CN101785100 A CN 101785100A CN 200980100230 A CN200980100230 A CN 200980100230A CN 200980100230 A CN200980100230 A CN 200980100230A CN 101785100 A CN101785100 A CN 101785100A
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- terminal
- wire
- bonded
- electronic component
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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Abstract
一种电子零件,在基板(52)(印刷基板)的上表面通过导体图案形成有装片部(55)和引线接合用端子(56)。在装片部(55)的上表面使用装片树脂(68)粘接固定有半导体元件(53)。半导体元件(53)的端子与引线接合用端子(56)之间通过接合线(69)连接。此外,在引线接合用端子(56)的周围以环绕引线接合用端子(56)的方式形成有槽部(64),该槽部(64)用于收集装片树脂(68)以防止其向引线接合用端子(56)侧流动。
Description
技术领域
本发明涉及一种电子零件。具体而言,涉及一种在基板上安装有传感器芯片及电子电路等半导体元件的电子零件。
背景技术
作为将半导体元件安装在封装上并用罩覆盖的电子零件,例如有专利文献1公开的电子零件(3轴加速度传感器)。如图1所示,在专利文献1所公开的电子零件11中,封装12由上表面中央部形成有凹部13的空腔基板构成,通过装片树脂将半导体元件14固定在凹部13内的底面。在封装12内,在比粘接半导体元件14的面高的位置即凹部13的周围设有引线接合用的端子图案15。半导体元件14的端子通过接合线16与封装12的端子图案15连接。而且,将半导体元件14安装在封装12内后,将罩17重合在封装12上并粘接,将半导体元件14封入封装12和罩17的内部。
根据这样结构的电子零件11,在对半导体元件14进行装片时,将半导体元件14粘接于凹部13底面的装片树脂不会流到端子图案15之上。因此,可防止因流出的装片树脂而在端子图案15上形成覆膜,可抑制将接合线16与端子图案15接合时、被装片树脂的覆膜阻碍而产生引线接合不良。
但是,由于内部形成有凹部13的空腔基板昂贵,因此,这样的电子零件11存在成本高的缺点。
另外,当为了降低成本而不使用空腔基板而使用平面状印刷基板时,由于涂敷装片树脂的面和引线接合用的端子面共面,故而装片树脂有可能流到引线接合用的端子面而污染该端子面,成为引线接合不良的原因。即,即使准确地管理装片树脂的涂敷量或使半导体元件14的推压力恒定而进行管理,因直至使涂敷的装片树脂固化的时间及外部环境的温度等而从半导体元件14的下表面流出的装片树脂的量发生变动。并且,作为装片树脂,为了缓和来自半导体元件的外部的振动等引起的特性变动要因,多使用硅酮等柔软的树脂。在使用这样的树脂的情况下树脂更容易流动。其结果是,有时流出的装片树脂附着在引线接合用的端子面而在该端子面形成覆膜,被覆膜阻碍而不能将接合线与端子面接合。
要想使用廉价的印刷基板并解决这样的问题,就必须使对半导体元件进行装片的区域与引线接合用的端子面的距离足够大。但是,当使该距离变大时,电子零件11的尺寸变大而妨碍小型化,且接合线(Au线)变长而导致高成本。
专利文献1:(日本)特开2006-98323号公报
发明内容
本发明是鉴于这样的技术课题而设立的,其目的在于提供一种电子零件,即使在使用廉价的印刷基板的情况下,也不易发生接合线的连接不良。
本发明的电子零件,使用装片树脂将半导体元件粘接固定在印刷基板的装片部,通过接合线将由印刷基板的导体图案形成的引线接合用端子和所述半导体元件连接,其特征在于,在围绕所述引线接合用端子的区域中至少位于所述装片部侧的区域形成有比所述印刷基板的导体图案低的槽部。
本发明的电子零件中,由于在围绕引线接合用端子的区域中至少位于装片部侧的区域形成有比印刷基板的导体图案低的槽部,因而在将半导体元件安装于装片部时即使装片树脂从装片部流出,也可以由槽部收集向引线接合用端子侧流动的装片树脂,可防止装片部附着在引线接合用端子的表面。因此,不必担心因装片树脂而在引线接合用端子的表面形成覆膜,能够可靠地进行向引线接合用端子的引线接合,可以减少引线接合不良。
本发明的电子零件的一方面,所述槽部在围绕所述引线接合用端子的区域的整个一周形成。根据该方面,由于以围绕引线接合用端子的方式形成槽部,故而可通过槽部收集从装片部绕入而到达引线接合用端子的装片树脂。
本发明的电子零件的另一方面,所述槽部通过将所述印刷基板的导体图案除去而形成。根据该方面,由于可利用将导体图案除去后的部分形成槽部,故而可简单且廉价地形成槽部。
本发明的电子零件的又一方面,所述槽部还通过将所述印刷基板的基板芯材除去而形成。根据该方面,由于将导体图案和基板芯材除去而形成槽部,故而可使槽部加深,即使在从装片部流出的装片树脂量多的情况下,也能够防止装片树脂附着在引线接合用端子上。
本发明的电子零件的其他方面,对所述引线接合用端子的表面实施镀金。由于装片树脂相对于镀金的濡湿性差,故而通过用镀金弹拨流入到槽部的装片树脂,使装片树脂更难以附着在引线接合用端子之上。
另外,用于解决本发明的所述课题的方式具有将以上说明的构成要素适当组合的特征,本发明可以通过将上述构成要素适当组合而进行多种变更。
附图说明
图1是表示专利文献1公开的电子零件的一实施方式的剖面图;
图2是表示本发明第一实施方式的电子零件的结构的剖面图;
图3(a)是图2的X部的平面图,图3(b)是图2的X部的放大剖面图;
图4是电子零件的除去导电性罩后的状态的平面图;
图5(a)是表示本发明第二实施方式的电子零件的一部分的平面图,图5(b)是其放大剖面图;
图6(a)是表示本发明第三实施方式的电子零件的一部分的平面图,图6(b)是其放大剖面图;
图7(a)是表示本发明第四实施方式的电子零件的一部分的平面图,图7(b)是其放大剖面图。
附图标记说明
51:电子零件
52:基板
52a:基板芯材
53:半导体元件
55:装片部
56:引线接合用端子
58:表面侧接地图案
60:槽部
61:镀金
62:引出电极
63:背面侧接地图案
64:槽部
65、66:通孔
67:抗焊料剂
68:装片树脂
69:接合线
70:凸缘
71:导电性接合部件
76:引线接合用端子
具体实施方式
以下,参照附图说明本发明的优选实施方式
(第一实施方式)
图2是表示本发明第一实施方式的电子零件的结构的剖面图。图3(a)是图2的X部的平面图,图3(b)是图2的X部的放大剖面图。另外,图4是电子零件去掉导电性罩后的状态的平面图。在此所示的电子零件51在基板52的上表面安装有半导体元件53,在由基板52和导电性罩54构成的封装(法拉第罩)内收纳有半导体元件53。
基板52由印刷基板构成,在绝缘性基板芯材52a的上表面及下表面设有对Cu等金属薄膜进行了构图的导体图案。如图4所示,在基板52的上表面通过导体图案形成有装片部55、引线接合用端子56、接地电极57、表面侧接地图案58。
引线接合用端子56是用于通过接合线69向半导体元件53供电或者进行信号输入输出的端子,在该实施方式中,设有多个引线接合用端子56。引线接合用端子56的周围通过槽部60(空隙)与表面侧接地图案58分开。上表面侧的槽部60是指将导体图案的至少一部分除去而比导体图案的上表面低的区域。特别是在第一实施方式中,上表面侧的槽部60是将导体图案彼此分开而在底面露出基板芯材52a的区域。槽部60通过对金属薄膜进行蚀刻而形成,其宽度为0.10mm左右,槽深为0.02~0.03mm。另外,引线接合用端子56配置在装片部55附近,其表面被镀金61覆盖。
装片部55、接地电极57及表面侧接地图案58连续地彼此连接。接地电极57为用于接合导电性罩54的区域。接地电极57形成在基板52的外周部,包围装片部55、引线接合用端子56以及表面侧接地图案58。另外,接地电极57的表面由镀金61覆盖。
装片部55为用于安装半导体元件53的区域。表面侧接地图案58为上表面的导体图案中除装片部55、接地电极57以及引线接合用端子56以外的区域。将装片部55设定在被表面侧接地图案58包围的区域,装片部55及表面侧接地图案58的表面由抗焊料剂67覆盖。抗焊料剂67通过对熔化状态的抗焊料剂进行网板印刷而在基板52的表面涂敷均匀的厚度,然后,通过进行加热使其固化。另外,也可替代抗焊料剂67而使用丝网。
在基板52的下表面通过导体图案设有多个引出电极62和背面侧接地图案63。背面侧接地图案63将无引出电极62的区域的大致整体覆盖,引出电极62和背面侧接地图案63通过槽部64而彼此分开。引出电极62及背面侧接地图案63为用于在用于安装电子零件51的基板(例如手机用的母板)上进行焊锡安装的图案,其表面实施了镀金。
在基板芯材52a上形成有贯通表面背面的通孔65、66,各引线接合用端子56通过通孔65与各引出电极62电连接。一体地连续的装片部55、表面侧接地图案58、接地电极57通过通孔66与背面侧接地图案63连接。
半导体元件53为各种传感检测用的传感器芯片(例如,音响传感器、加速度传感器、压力传感器等)、LSI、ASIC等元件。半导体元件53的下表面通过装片树脂68粘接固定在装片部55之上。作为装片树脂68可使用具有柔软性的硅酮等粘接树脂,将涂覆于转印针(压模)的装片树脂68转印到装片部55之上后,将半导体元件53装载于其上并以均等的力进行按压,将装片树脂68加热使其固化而将半导体元件53固定。装片树脂68除了固定半导体元件53之外,还具有通过其柔软性遮断来自外部环境的多余力的作用。
在半导体元件53的端子和引线接合用端子56上分别超声波焊接有由Au线构成的接合线69的一端,半导体元件53和引线接合用端子56通过接合线69连接。因此,半导体元件53的各端子与下表面的各引出电极62导通。
另外,在基板52的上表面可以安装多个半导体元件,也可以安装其它的电子零件。因此,导体图案可根据所安装的半导体元件及电子零件等的形式而适当自由地设计。
导电性盖54由电阻率小的金属材料形成为罩状,在下表面形成有用于收纳半导体元件53等的空间。在导电性罩54的下端部整个一周形成有大致水平延伸的凸缘70。
导电性罩54以覆盖半导体元件53等的方式载置于基板52上,凸缘70下表面通过导电性接合部件71被粘接固定在接地电极57,并且通过导电性接合部件71的导电性与接地电极57电连接。因此,导电性罩54与下表面的背面侧接地图案63为同电位(地电位)。作为导电性接合部件71使用导电性环氧树脂(例如,含有银填充剂的环氧树脂)及焊料等材料。
另外,在所安装的半导体元件53为音响传感器等的情况下,可以在导电性罩54上开设用于使音响振动通过的孔(未图示)。另外,由导电性罩54和基板52构成的封装可以根据所收纳的半导体元件53的种类而成为密闭结构。例如,在只要遮断来自外部的灰尘、光等即可的情况下,只要用封装覆盖半导体元件53等即可,不是一定要求气密性,而在需要有耐化学药品性的情况下,封装具有气密性为好。
根据该电子零件51,由于法拉第罩由接地的导电性盖54和具有接地连接的背面侧接地图案63及表面侧接地图案58的基板52构成,因而可将半导体元件53与外部的高频干扰隔断,可降低外部噪声对半导体元件53的影响。
另外,由于基板52的上表面和下表面均几乎整个面都被导体图案覆盖,因而可防止由温度变化等造成的基板52的翘曲。
另外,基板52上表面的导体图案上之所以在未实施镀金61的区域涂敷抗焊料剂67,是为了利用廉价的材料保护导体图案的无需电连接的区域。此外,由于硅酮等装片树脂68与对镀金的粘接强度相比较,对抗焊料剂的粘接强度高,因而通过用抗焊料剂67覆盖装片部55,可提高装片树脂68对半导体元件53的粘接强度。
另外,根据该电子零件51,可降低引线接合用端子56的引线接合不良。在背景技术中,对由于从装片部55流出的装片树脂68在引线接合用端子56形成覆膜而产生引线接合不良的情况进行了说明,但以下将对在该实施方式中可降低这样的引线接合不良的理由进行说明。
在该实施方式中,如上所述,以围绕引线接合用端子56的方式设有宽度小的槽部60。因此,即使进行装片时装片树脂69从装片部55向引线接合用端子56流出,当该装片树脂68到达槽部60时,通过毛细管现象被吸收到槽部60内。而且,由于被吸引到槽部60的装片树脂68沿着槽部60扩展,故而可防止超出槽部60而在引线接合用端子56形成覆膜。在该实施方式中,虽然将槽宽形成为0.1mm左右,但是槽宽窄的一方容易由于毛细管现象而吸引装片树脂68,因此,在考虑了绝缘性的基础上,槽部60的槽宽也可以更窄。
这样,由于可防止引线接合用端子56被装片树脂68污染而形成覆膜,故而在将接合线69与引线接合用端子56进行接合时不会受到覆膜的妨碍,可降低引线接合不良。另外,由于没有无需增大装片部55与引线接合用端子56的距离,可缩短接合线69的线长,可抑制成本的上升。
另外,用于连接引线接合用端子56和引出电极62的通孔65设置在自接合接合线69的部位偏离的位置。这是为了防止通孔65因引线接合时的超声波振动而破损。
(第二实施方式)
图5(a)是表示本发明第二实施方式的电子零件的一部分的平面图,图5(b)是其放大剖面图。在该实施方式中,以围绕引线接合用端子56的方式在整个一周形成有槽部60,然后,在远离装片部55的一侧用抗焊料剂67掩埋槽部60的一部分,并且由抗焊料剂67覆盖引线接合用端子56的一部分。而且,将引线接合用端子56中从抗焊料剂67露出的区域,即接近装片部55一侧的区域被镀金61覆盖,将由镀金61覆盖的区域作为接合线69的接合部位。
根据该实施方式,由于引线接合用端子56中未用作引线接合的区域被抗焊料剂67覆盖,因而可缩小引线接合用端子56的镀金区域的面积,可降低基板52的成本。另一方面,由于在装片树脂68的流动方向上,槽部60被抗焊料剂67覆盖,故而可吸引装片树脂68,可防止由装片树脂68在引线接合用端子56上形成覆膜。
(第三实施方式)
图6(a)是表示本发明第三实施方式的电子零件的一部分的平面图,图6(b)是其放大剖面图。该实施方式是接地用的引线接合用端子76的情况。接地用的引线接合用端子76通过通孔66与下表面的背面侧接地图案63连接。另外,在引线接合用端子76的周围,沿靠近装片部55的一边(装片树脂68的流动方向)和两侧边形成有槽部60,引线接合用端子76的远离装片部55一侧的边与表面侧接地图案58或接地电极57连接。
在引线接合用端子76的表面(从抗焊料剂67露出的区域)实施镀金61。而且,半导体元件53的接地端子和引线接合用端子76通过接合线69连接。
在这样的实施方式中,虽然槽部60没有闭合成环状,但由于流出的装片部55被接近装片部55一侧的槽部60吸引,而没有槽部60的部分为远离装片部55的部位,是装片树脂68不易绕入而到达的部分,因此,对于防止由装片树脂68在引线接合用端子76上形成覆膜的效果的影响小。
(第四实施方式)
图7(a)是表示本发明第四实施方式的电子零件的一部分的平面图,图7(b)是其放大剖面图。在该实施方式中,将导体图案除去而形成槽部60,并且将其下表面的基板芯材52a除去而使槽部60加深。根据这样的结构,可以通过加深槽部60的深度来增加滞留在槽部60内的树脂量。另外,由于使槽部60的深度加深而增加滞留的树脂量,故而如扩大槽部60的槽宽以增加滞留的树脂量的情况,不会使由毛细管现象吸引装片树脂68的能力降低。
Claims (5)
1.一种电子零件,使用装片树脂将半导体元件粘接固定在印刷基板的装片部,通过接合线将由印刷基板的导体图案形成的引线接合用端子和所述半导体元件连接,其特征在于,
在围绕所述引线接合用端子的区域中至少在位于所述装片部侧的区域形成有比所述印刷基板的导体图案低的槽部。
2.如权利要求1所述的电子零件,其特征在于,所述槽部在围绕所述引线接合用端子的区域的整个一周形成。
3.如权利要求1所述的电子零件,其特征在于,所述槽部通过将所述印刷基板的导体图案除去而形成。
4.如权利要求3所述的电子零件,其特征在于,所述槽部还通过将所述印刷基板的基板芯材除去而形成。
5.如权利要求1所述的电子零件,其特征在于,对所述引线接合用端子的表面实施镀金。
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JP2008173383A JP5458517B2 (ja) | 2008-07-02 | 2008-07-02 | 電子部品 |
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PCT/JP2009/000670 WO2010001505A1 (ja) | 2008-07-02 | 2009-02-18 | 電子部品 |
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EP (1) | EP2187437A1 (zh) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105555018A (zh) * | 2016-02-16 | 2016-05-04 | 广东欧珀移动通信有限公司 | 一种印刷电路板及电子终端 |
CN111328210A (zh) * | 2018-12-13 | 2020-06-23 | 意法半导体(格勒诺布尔2)公司 | 用于安装部件的方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011003195B4 (de) * | 2011-01-26 | 2019-01-10 | Robert Bosch Gmbh | Bauteil und Verfahren zum Herstellen eines Bauteils |
JP6678506B2 (ja) * | 2016-04-28 | 2020-04-08 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージ及び半導体パッケージの製造方法 |
US10544040B2 (en) * | 2017-05-05 | 2020-01-28 | Dunan Microstaq, Inc. | Method and structure for preventing solder flow into a MEMS pressure port during MEMS die attachment |
KR102471275B1 (ko) * | 2019-01-24 | 2022-11-28 | 삼성전자주식회사 | 칩 온 필름(cof) 및 이의 제조방법 |
CN110930879B (zh) * | 2019-11-25 | 2020-11-10 | 武汉华星光电半导体显示技术有限公司 | 一种显示装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5508556A (en) * | 1994-09-02 | 1996-04-16 | Motorola, Inc. | Leaded semiconductor device having accessible power supply pad terminals |
JPH08181166A (ja) * | 1994-12-22 | 1996-07-12 | Ibiden Co Ltd | プリント配線板 |
US6034427A (en) * | 1998-01-28 | 2000-03-07 | Prolinx Labs Corporation | Ball grid array structure and method for packaging an integrated circuit chip |
JP2000223613A (ja) * | 1999-01-28 | 2000-08-11 | Citizen Watch Co Ltd | 半導体装置 |
JP2001267452A (ja) * | 2000-03-16 | 2001-09-28 | Hitachi Ltd | 半導体装置 |
US6426565B1 (en) * | 2000-03-22 | 2002-07-30 | International Business Machines Corporation | Electronic package and method of making same |
US6867493B2 (en) * | 2000-11-15 | 2005-03-15 | Skyworks Solutions, Inc. | Structure and method for fabrication of a leadless multi-die carrier |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4963148B2 (ja) | 2001-09-18 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7164192B2 (en) * | 2003-02-10 | 2007-01-16 | Skyworks Solutions, Inc. | Semiconductor die package with reduced inductance and reduced die attach flow out |
US7144517B1 (en) * | 2003-11-07 | 2006-12-05 | Amkor Technology, Inc. | Manufacturing method for leadframe and for semiconductor package using the leadframe |
JP2006098323A (ja) | 2004-09-30 | 2006-04-13 | Hitachi Metals Ltd | 半導体型3軸加速度センサ |
KR100688857B1 (ko) * | 2004-12-17 | 2007-03-02 | 삼성전기주식회사 | 윈도우를 구비한 볼 그리드 어레이 기판 및 그 제조방법 |
JP4736451B2 (ja) * | 2005-02-03 | 2011-07-27 | パナソニック株式会社 | 多層配線基板とその製造方法、および多層配線基板を用いた半導体パッケージと電子機器 |
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- 2009-02-18 WO PCT/JP2009/000670 patent/WO2010001505A1/ja active Application Filing
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- 2009-02-18 KR KR1020107003090A patent/KR20100031775A/ko not_active Application Discontinuation
- 2009-02-18 CN CN200980100230A patent/CN101785100A/zh active Pending
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Cited By (2)
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---|---|---|---|---|
CN105555018A (zh) * | 2016-02-16 | 2016-05-04 | 广东欧珀移动通信有限公司 | 一种印刷电路板及电子终端 |
CN111328210A (zh) * | 2018-12-13 | 2020-06-23 | 意法半导体(格勒诺布尔2)公司 | 用于安装部件的方法 |
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JP2010016096A (ja) | 2010-01-21 |
EP2187437A1 (en) | 2010-05-19 |
KR20100031775A (ko) | 2010-03-24 |
US8274797B2 (en) | 2012-09-25 |
WO2010001505A1 (ja) | 2010-01-07 |
JP5458517B2 (ja) | 2014-04-02 |
US20110044017A1 (en) | 2011-02-24 |
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