WO2009147723A1 - 試験システムおよび試験用基板ユニット - Google Patents
試験システムおよび試験用基板ユニット Download PDFInfo
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- WO2009147723A1 WO2009147723A1 PCT/JP2008/060175 JP2008060175W WO2009147723A1 WO 2009147723 A1 WO2009147723 A1 WO 2009147723A1 JP 2008060175 W JP2008060175 W JP 2008060175W WO 2009147723 A1 WO2009147723 A1 WO 2009147723A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- the present invention relates to a test system for testing a semiconductor chip and a test substrate unit.
- the present invention relates to a test system and a test substrate unit that test a plurality of semiconductor chips formed on a semiconductor wafer.
- a probe card is formed using a printed circuit board or the like (for example, see Patent Document 2).
- a plurality of probe pins By forming a plurality of probe pins on the printed circuit board, a plurality of semiconductor chips can be electrically connected together.
- the test of the semiconductor chip includes a DC test that determines whether the DC power consumed by the semiconductor chip satisfies the specifications, a function test that determines whether the semiconductor chip outputs a predetermined output signal with respect to the input signal, etc.
- a DC test that determines whether the DC power consumed by the semiconductor chip satisfies the specifications
- a function test that determines whether the semiconductor chip outputs a predetermined output signal with respect to the input signal
- There are various tests such as an analog test for determining whether the characteristics of the signal output from the semiconductor chip satisfy the specifications.
- an object of the present invention is to provide a test system and a test substrate unit that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- a test system for testing a plurality of chips to be tested formed on a wafer to be tested each of which has a plurality of test circuits formed in multiple layers.
- a plurality of test substrates arranged in layers, a connection part for transmitting a signal generated by a test circuit provided on any of the test substrates to each chip under test, and a control for controlling each test circuit A test system comprising the apparatus.
- a test substrate unit for testing a plurality of chips to be tested formed on a wafer to be tested, each of which has a plurality of test circuits and is arranged in multiple layers.
- a test substrate unit comprising: a test substrate; and a connection portion for transmitting a signal generated by a test circuit provided on any of the test substrates to each chip under test.
- a test system for testing a plurality of chips to be tested formed on a wafer to be tested, each of which has a plurality of test circuits and is arranged in multiple layers.
- a test system is provided in which a test circuit having a function predetermined for each board is formed on each test board.
- a test substrate unit for testing a plurality of chips to be tested formed on a wafer to be tested, each of which has a plurality of test circuits and is arranged in multiple layers.
- a test substrate unit in which a test circuit having a function predetermined for each substrate is formed on each test substrate.
- FIG. 2 is a diagram for explaining an outline of a test in a test system 200.
- FIG. 2 is a diagram illustrating an example of a test circuit 110 provided on each test substrate 100.
- FIG. 2 is an example of a sectional view of a test substrate unit 400 and a wafer under test 300.
- FIG. 4A is a diagram illustrating a configuration example of the connection unit 710.
- FIG. 4B is a diagram illustrating another configuration example of the connection unit 710.
- FIG. 10 is a diagram showing another configuration example of the test substrate unit 400. It is a figure explaining the outline
- FIG. 1 is a diagram for explaining an outline of a test in the test system 200.
- the test system 200 uses the test substrate unit 400 to test each chip under test 310 of the wafer under test 300.
- the test system 200 includes a control device 10 and a test board unit 400.
- the test substrate unit 400 is connected to a plurality of chips to be tested 310 formed on the wafer to be tested 300 so as to be able to exchange signals collectively, and tests each chip to be tested 310 in parallel.
- the test substrate unit 400 may include a plurality of test circuits 110 provided corresponding to the plurality of chips to be tested 310. Each test circuit 110 may test a corresponding chip under test 310.
- the test circuit 110 may be provided corresponding to a plurality of pins to be tested in the corresponding chip under test 310, or may be provided for each pin to be tested in the chip under test 310.
- the control device 10 controls the test substrate unit 400 to test each chip under test 310.
- the control device 10 may supply a trigger signal or the like for starting the test to each test circuit 110.
- the test substrate unit 400 includes a plurality of test substrates 100 and a connection unit 700.
- a test substrate unit 400 having two test substrates 100 is shown as an example.
- Each of the test substrate 100 and the connection unit 700 may be formed of the same semiconductor material as the wafer under test 300.
- these substrates may be silicon wafers.
- each of the test substrate 100 and the connection unit 700 may have substantially the same diameter as the wafer under test 300.
- the test system 200 of this example uses a semiconductor wafer having a diameter substantially the same as that of the wafer under test 300 as the connection unit 700 and is electrically connected to a plurality of chips under test 310 in a lump.
- each test substrate 100 a plurality of test circuits 110 having a function predetermined for each wafer are formed for each substrate corresponding to the plurality of chips to be tested 310.
- test circuits 110 having different functions may be formed on different test substrates 100. More specifically, a test circuit 110-1 for performing a DC test of the chip under test 310 is formed on the first test substrate 100-1 in a one-to-one correspondence with each chip under test 310. Good. Further, on the second test substrate 100-2, test circuits 110-2 for performing an analog test of the chip under test 310 may be formed in one-to-one correspondence with each chip under test 310. In FIG. 1, in each test substrate 100, the test circuit 110 corresponding to one chip under test 310 is shown, and the display of the other test circuits 110 is omitted.
- each test substrate 100 is arranged in multiple layers.
- the back surface of the first test substrate 100-1 and the front surface of the second test substrate 100-2 may be attached via an anisotropic conductive sheet or the like.
- connection unit 700 is provided between the test substrate 100 closest to the wafer under test 300 and the wafer under test 300.
- the connection unit 700 of this example is provided between the second test substrate 100-2 and the wafer under test 300, the pad provided on the second test substrate 100-2, and the wafer under test.
- the signal transmission path between the pads provided at 300 is connected.
- connection unit 700 has a plurality of connection portions 710 corresponding to the plurality of chips to be tested 310.
- the connection unit 700 may have a plurality of connection portions 710 in one-to-one correspondence with the plurality of chips to be tested 310.
- FIG. 1 the connection portion 710 corresponding to one chip to be tested 310 is shown, and the display of the other connection portions 710 is omitted.
- Each connection unit 710 supplies a signal generated by the test circuit 110 provided on one of the test substrates 100 to each chip under test 310.
- each connection unit 710 may connect a signal transmission path from one of the test circuits 110 to each chip under test 310.
- the signal transmission path may include an electrical signal transmission path, an optical signal transmission path, or the like. Further, a part of the signal transmission path may include a non-contact transmission path such as electrostatic coupling or inductive coupling.
- an electric signal transmission path is used as the signal transmission path will be described.
- Each connection portion 710 may be provided so as to be able to switch which test circuit 110 of the test substrate 100 is connected to the corresponding chip under test 310.
- each connection unit 710 may connect the test circuit 110 of the predetermined test substrate 100 to the corresponding chip under test 310.
- each connection portion 710 determines which function of the test circuit 110 is connected to the corresponding chip under test 310.
- the signal used for the test is transmitted via a short needle, a cable, etc.
- the transmission path length between the test circuit 110 and the chip under test 310 is shortened. Therefore, the chip under test 310 can be tested with higher accuracy. Since the substrate materials of the wafer under test 300 and the connection unit 700 are the same, the thermal expansion coefficients of these wafers can be made substantially the same, and the electrical connection between the wafer under test 300 and the connection unit 700 Connection reliability can be improved.
- connection portion 710 may be electrically connected to the test circuit 110 provided on each test substrate 100.
- each test substrate 100 bypasses the test circuit 110 provided on the test substrate 100 far from the connection unit 700 to the test substrate 100 closer to the connection unit 700.
- a via hole to be connected is formed.
- the test circuit 110 provided on the first test substrate 100-1 is electrically connected to the connection portion 710 via a via hole provided on the second test substrate 100-2.
- connection unit 710 may be electrically connected to a plurality of corresponding test circuits 110 through a plurality of via holes.
- the connection unit 710 may electrically connect the corresponding chip under test 310 to any one test circuit 110 via any via hole.
- FIG. 2 is a diagram illustrating an example of a test circuit 110 provided on each test substrate 100.
- one test circuit 110 provided on each test substrate 100 is shown.
- each test substrate 100 is provided with a test circuit 110 having a function predetermined for each wafer.
- the first test substrate 100-1 may be provided with a test circuit 110-1 for performing a DC test of the chip under test 310.
- the direct current test may be, for example, a test for determining whether or not the power supply voltage or power supply current supplied to the chip under test 310 is within a predetermined range.
- the second test substrate 100-2 may be provided with a test circuit 110-2 for performing an analog test of the chip under test 310.
- the analog test may be a test for determining whether an analog waveform of a signal output from the chip under test 310 satisfies a predetermined specification, for example.
- the third test substrate 100-3 may be provided with a test circuit 110-3 for performing a function test of the chip under test 310.
- the function test is a test for determining whether or not the logic pattern of the response signal output from the chip under test 310 matches a predetermined expected value pattern when a predetermined logic pattern is input to the chip under test 310, for example. It may be.
- test executed by the test system 200 is not limited to the above test.
- a test circuit 110 corresponding to various tests such as a scan test of the chip under test 310 and a jitter tolerance test may be provided on the test substrate 100.
- the test circuit 110 provided on the test substrate 100 closer to the wafer under test 300 may generate a signal having a higher frequency to test the chip under test 310.
- the test circuit 110 that performs the DC test may be provided on the test substrate 100 that is farther from the wafer under test 300 than the test circuit 110 that performs the high-frequency analog test. That is, by disposing the test circuit 110 for testing the chip under test 310 using a high frequency signal close to the chip under test 310, the transmission distance of the high frequency signal can be shortened, and the chip under test 310 can be made more accurately. Can be tested.
- connection unit 710 connects the test circuit 110 provided on one of the test substrates 100 to the corresponding chip under test 310.
- the connection unit 710 may include a multiplexer that selects one of the test circuits 110.
- the connection unit 700 may be provided with a setting register 711 for each connection unit 710.
- the setting register 711 causes the connection unit 710 to select the test circuit 110 corresponding to the setting information written in advance.
- the control device 10 may write the setting information in the setting register 711.
- the control device 10 may write the same setting information in each setting register 711 or may write different setting information. In this way, by using a plurality of types of test circuits 110 provided in the vicinity of the chip under test 310, various tests can be performed on the chip under test 310 with high accuracy.
- FIG. 3 is an example of a cross-sectional view of the test substrate unit 400 and the wafer under test 300. As described above, each test circuit 110 is electrically connected to the connection portion 710 through a via hole formed in each test substrate 100.
- the uppermost first test substrate 100-1 includes a plurality of test circuits 110-1, a plurality of signal via holes 116-1, a plurality of front surface pads 112-1, a plurality of back surface pads 114-1, A plurality of wirings 124, control wirings 126, control pads 118, and control via holes 122-1 are formed. These structures may be formed by a semiconductor process such as optical exposure.
- the test circuit 110-1 may be formed on the surface of the first test substrate 100-1. Each test circuit 110-1 is electrically connected to the surface pad 112-1 via a wiring 124 formed on the surface of the first test substrate 100-1. The front surface pad 112-1 is electrically connected to the back surface pad 114-1 provided on the back surface of the first test substrate 100-1 through the signal via hole 116-1.
- control pad 118-1 may be electrically connected to the control device 10.
- the control pad 118-1 may supply a control signal given from the control device 10 to each test circuit 110-1.
- the control pad 118-1 is electrically connected to the control pad 118-2 of the second test substrate 100-2 through the control via hole 122-1. Thereby, the control signal from the control device 10 is supplied to all the test circuits 110.
- the pads provided on the back surface of the first test substrate 100-1 are the pads provided on the surface of the second test substrate 100-2 via the anisotropic conductive sheet 150. May be electrically connected.
- the second test substrate 100-2 connected to the first test substrate 100-1 includes a plurality of bypass surface pads 128-2 in addition to the configuration of the first test substrate 100-1.
- a plurality of bypass via holes 130-2 and a plurality of bypass backside pads 132-2 are further formed.
- the plurality of bypass front surface pads 128-2 are provided in one-to-one correspondence with the plurality of back surface pads of the test substrate 100, which is the upper layer of the test substrate 100. Each bypass front surface pad 128-2 is electrically connected to a corresponding back surface pad.
- the plurality of bypass back surface pads 132-2 are provided on the back surface of the test substrate 100 in one-to-one correspondence with the plurality of bypass surface pads 128-2.
- the plurality of bypass via holes 130-2 are provided in one-to-one correspondence with the plurality of bypass surface pads 128-2.
- Each bypass via hole 130-2 electrically connects the corresponding front surface pad 128-2 and back surface pad 132-2.
- connection unit 700 includes a plurality of connection portions 710, a plurality of test circuit surface pads 712, a plurality of wirings 714, a plurality of connection surface pads 718, a plurality of connection back surface pads 720, and a plurality of connections.
- a via hole 722 is formed.
- the plurality of test circuit front surface pads 712 are provided in one-to-one correspondence with the back surface pads of the test substrate 100 provided to face the connection unit 700 and are electrically connected.
- the connection unit 700 may be provided with a control pad 730 that receives a control signal.
- connection portion 710 is electrically connected to the corresponding plurality of test circuit surface pads 712. Thereby, the connection part 710 is electrically connected to the test circuit 110 of each layer.
- the connection unit 710 electrically connects any one of the test circuit surface pads 712 to the connection surface pad 718. Thereby, each connection part 710 electrically connects the test circuit 110 of any layer to the corresponding connection surface pad 718.
- connection surface pad 718 is electrically connected to the connection back surface pad 720 through the connection via hole 722.
- connection back surface pad 720 is electrically connected to the pad of the wafer under test 300 via the anisotropic conductive sheet 150 and the bumped membrane 160.
- the test circuit 110 of the upper test substrate 100 is added to the lower test wafer 100.
- the connection unit 710 can connect any one of the test circuits 110 to the chip under test 310.
- FIG. 4A is a diagram illustrating a configuration example of the connection unit 710.
- the connection unit 710 of this example includes a multiplexer 716.
- the multiplexer 716 is electrically connected to the plurality of test circuit surface pads 712, selects any one of the test circuit surface pads 712, and is electrically connected to the connection surface pad 718.
- the multiplexer 716 may receive a selection signal indicating which test circuit surface pad 712 should be selected from the control device 10.
- the control device 10 may supply a selection signal to the multiplexer 716 through the control via hole 122. With such a configuration, various test circuits 110 can be connected to the chip under test 310.
- the multiplexer 716 may receive a selection signal from the chip under test 310. That is, each chip under test 310 may select the test circuit 110 connected to itself. The chip under test 310 may select the test circuit 110 to be connected next according to its own test result, and data indicating the order of the test circuits 110 to be sequentially selected is received by the user or the like. It may be stored in the test chip 310 in advance.
- FIG. 4B is a diagram illustrating another configuration example of the connection unit 710.
- the connection portion 710 in this example includes a selection wiring 715.
- the selection wiring 715 electrically connects one of the test circuit surface pads 712 to the corresponding connection surface pad 718.
- the test system 200 preferably holds the connection unit 700 in a replaceable manner.
- Various test circuits 110 can be connected to the chip under test 310 by using a plurality of types of connection units 700 having different connection relationships of the selection wiring 715 in the connection portion 710.
- portions other than the selection wiring 715 in the connection unit 700 may be formed by a process such as optical exposure using a mask.
- the selection wiring 715 may be formed by electron beam exposure. In the electron beam exposure, exposure is performed by controlling the irradiation direction of the electron beam and the like, so that exposure can be performed without using a mask. Therefore, a plurality of types of connection units 700 can be manufactured using a common mask. Further, since portions other than the selection wiring 715 can be formed by optical exposure, the connection unit 700 can be manufactured efficiently.
- FIG. 5 is a diagram showing a connection example of the test circuit 110 and the surface pad 112 in each test substrate 100.
- each test substrate 100 has a different configuration, but the test substrate 100 of this example may have the same configuration. .
- the number of surface pads 112 corresponding to the number of test substrates 100 in the test substrate unit 400 may be formed on each test substrate 100 corresponding to one test circuit 110.
- Each front surface pad 112 is electrically connected to the underlying wafer through a via hole and a back surface pad. That is, each surface pad 112 is electrically connected to the connection portion 710 of the connection unit 700 through the via hole formed in the test substrate 100 of each layer.
- a multiplexer 170 may be formed for each test circuit 110 on each test substrate 100. Each multiplexer 170 selects which surface pad 112 the corresponding test circuit 110 is connected to. The multiplexer 170 may be supplied with a control signal indicating which surface pad 112 is selected from the control device 10.
- each test circuit 110 can be connected to the connection portion 710. Further, even when any one of the test substrates 100 is replaced with another test substrate 100, each test circuit 110 can be connected to the connection portion 710.
- the test system 200 may include a holding unit that holds each test substrate 100 in a replaceable manner.
- FIG. 6 is a diagram showing another configuration example of the test board unit 400.
- the test substrate unit 400 of this example is different from the configuration of the test substrate unit 400 described with reference to FIG. 2 in that the connection unit 700 is not provided.
- the connecting portion 710 may be provided on the test substrate 100 closest to the wafer under test 300 among the plurality of test substrates 100.
- the connection unit 710 is electrically connected to the test circuit 110 of the upper-layer test substrate 100 through a via hole in the same manner as the connection unit 710 described with reference to FIG. 2, and the connection unit 710 is provided.
- the test circuit 110 in the test substrate 100 is also electrically connected. Then, one of the test circuits 110 is electrically connected to the corresponding chip under test 310.
- test circuits 110 can be connected to the chip under test 310. Therefore, various tests can be performed on the chip under test 310.
- the connection portion 710 is provided on the lowermost test substrate 100, the lowermost test substrate 100 does not have to be held interchangeably.
- a test circuit 110 that is commonly used in a plurality of types of tests may be formed on the test substrate 100 at the lowermost layer.
- the test circuit 110 of the lowermost test substrate 100 may be a power supply circuit that supplies power to the chip under test 310.
- connection unit 700 may be a probe card.
- the probe card may be a unit that is electrically connected to a plurality of chips to be tested 310 by providing probe pins on a printed circuit board or the like, for example.
- connection unit 700 may use an anisotropic conductive sheet. The anisotropic conductive sheet is pressed by the pads of the test circuit 110 and the pads of the chip under test 310 to electrically connect these pads.
- the connection portion 710 may include a selection wiring 715 as illustrated in FIG.
- connection units 700 may be provided.
- the test system 200 may include a connection unit 700 disposed between the test substrates 100 in addition to the connection unit 700 disposed between the test substrate 100 and the wafer under test 300.
- the connection unit 700 disposed between the test substrates 100 may switch which pad on the lower test substrate 100 is connected to each pad on the upper test substrate 100.
- FIG. 7 is a diagram illustrating an outline of a test system 200 in another example.
- the test system 200 in this example tests a plurality of chips to be tested 310 using a plurality of test substrates 100 without having the connection portion 710. In this case, the test system 200 may not have the connection unit 700. Also in this example, each test substrate 100 may be provided with a test circuit 110 classified for each function for each test substrate 100.
- the test circuit 110 formed on each of the test substrates 100 passes signals to and from the chip under test 310 via any of the input / output pads 312 of the chip under test 310.
- the test circuit 110 selected by the connection unit 710 is connected to the chip under test 310.
- all the test circuits 110 are connected to any of the chips under test 310.
- the input / output pad 312 may be connected.
- Each test substrate 100 may be provided corresponding to at least one input / output pad 312.
- each test circuit 110 in each test substrate 100 may be connected to the input / output pad 312 corresponding to the test substrate 100 in the corresponding chip under test 310.
- the test circuit 110 connected to the input / output pad 312 corresponding to the test substrate 100 can be connected to a plurality of test substrates.
- the test chip 310 can be changed collectively.
- a test circuit 110 for digital pattern input a test circuit 110 for control input, a test circuit 110 for digital pattern measurement, a test circuit 110 for power supply, and the like are provided on each test substrate 100 for each function. It may be formed by classification. With such a configuration, a digital test of the chip under test 310 may be performed.
- a predetermined test substrate 100 may be replaced with another test substrate 100.
- the analog test of the chip under test 310 may be performed by replacing the test substrate 100 for digital pattern input with the test substrate 100 for analog signal input.
- the test substrate 100 corresponds to a plurality of input / output pads 312, a plurality of types of test circuits 110 corresponding to the plurality of input / output pads 312 are mixedly formed on the test substrate 100. It's okay.
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Abstract
Description
Claims (12)
- 被試験ウエハに形成された複数の被試験チップを試験する試験システムであって、
それぞれ複数の試験回路が形成され、多層に重ねて配置される複数の試験用基板と、
それぞれの前記被試験チップに、いずれかの前記試験用基板に設けられた前記試験回路が生成した信号を伝送する接続部と、
それぞれの前記試験回路を制御する制御装置と
を備える試験システム。 - それぞれの前記試験用基板には、基板毎に予め定められた機能を有する前記試験回路が形成される
請求項1に記載の試験システム。 - 前記試験システムは、前記被試験ウエハに対して最も近い側の前記試験用基板と、前記被試験ウエハとの間に設けられる接続用ユニットを更に備え、
前記接続部は、前記接続用ユニットにおいて、前記複数の被試験チップに対応して設けられ、対応する前記被試験チップを、いずれか一つの前記試験回路からの信号伝送路に接続する
請求項2に記載の試験システム。 - それぞれの前記試験用基板には、前記被試験ウエハに対して遠い側の前記試験用基板に設けられる前記試験回路を、被試験ウエハに対して近い側の前記試験用基板にバイパスして接続するビアホールが形成される
請求項3に記載の試験システム。 - それぞれの前記接続部は、前記ビアホールを介して、前記試験用基板毎に一つずつの前記試験回路と電気的に接続される
請求項4に記載の試験システム。 - それぞれの前記接続部は、いずれの前記試験回路を、対応する前記被試験チップに電気的に接続するかを切り替える
請求項5に記載の試験システム。 - それぞれの前記接続部は、対応する前記被試験チップに電気的に接続される接続パッドを、対応する複数の前記ビアホールのうち、いずれか一つに電気的に接続する選択配線を有する
請求項4に記載の試験システム。 - 前記被試験ウエハに近い側の前記試験用基板に設けられる前記試験回路ほど、より高周波の信号を生成する
請求項1に記載の試験システム。 - 前記接続部は、複数の前記試験用基板のうち前記被試験ウエハに対して最も近い側の前記試験用基板に設けられる
請求項1に記載の試験システム。 - 被試験ウエハに形成された複数の被試験チップを試験する試験用基板ユニットであって、
それぞれ複数の試験回路が形成され、多層に重ねて配置される複数の試験用基板と、
それぞれの前記被試験チップに、いずれかの前記試験用基板に設けられた前記試験回路が生成した信号を伝送する接続部と
を備える試験用基板ユニット。 - 被試験ウエハに形成された複数の被試験チップを試験する試験システムであって、
それぞれ複数の試験回路が形成され、多層に重ねて配置される複数の試験用基板と、
それぞれの前記試験回路を制御する制御装置と
を備え、
それぞれの前記試験用基板には、基板毎に予め定められた機能を有する前記試験回路が形成される試験システム。 - 被試験ウエハに形成された複数の被試験チップを試験する試験用基板ユニットであって、
それぞれ複数の試験回路が形成され、多層に重ねて配置される複数の試験用基板を備え、
それぞれの前記試験用基板には、基板毎に予め定められた機能を有する前記試験回路が形成される試験用基板ユニット。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP2008/060175 WO2009147723A1 (ja) | 2008-06-02 | 2008-06-02 | 試験システムおよび試験用基板ユニット |
KR1020107025263A KR101147677B1 (ko) | 2008-06-02 | 2008-06-02 | 시험 시스템 및 시험용 기판 유닛 |
JP2010515693A JP5269897B2 (ja) | 2008-06-02 | 2008-06-02 | 試験システムおよび試験用基板ユニット |
TW098118195A TWI387762B (zh) | 2008-06-02 | 2009-06-02 | 測試系統以及測試用基板單元 |
US12/953,352 US8466702B2 (en) | 2008-06-02 | 2010-11-23 | Test system and substrate unit for testing |
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PCT/JP2008/060175 WO2009147723A1 (ja) | 2008-06-02 | 2008-06-02 | 試験システムおよび試験用基板ユニット |
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US12/953,352 Continuation US8466702B2 (en) | 2008-06-02 | 2010-11-23 | Test system and substrate unit for testing |
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JP (1) | JP5269897B2 (ja) |
KR (1) | KR101147677B1 (ja) |
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JP2011163807A (ja) * | 2010-02-05 | 2011-08-25 | Advantest Corp | 電子部品試験装置 |
TWI678748B (zh) * | 2018-10-18 | 2019-12-01 | 大陸商蘇州工業園區雨竹半導體有限公司 | 將測試樣品自晶圓基材分離方法 |
JP2021028993A (ja) * | 2020-11-25 | 2021-02-25 | 東京エレクトロン株式会社 | 検査システム |
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TW201245732A (en) * | 2011-05-05 | 2012-11-16 | Novatek Microelectronics Corp | Test chip and test system for integrated circuit chip using the same |
KR200458004Y1 (ko) * | 2011-06-21 | 2012-01-16 | 이화랑 | 방열수단이 구비된 엘이디 형광등 |
CN102520340B (zh) * | 2012-01-06 | 2016-08-03 | 日月光半导体制造股份有限公司 | 具有测试结构的半导体封装元件及其测试方法 |
US10295588B2 (en) * | 2016-12-22 | 2019-05-21 | Xcelsis Corporation | Wafer testing without direct probing |
KR102066801B1 (ko) * | 2018-12-20 | 2020-01-15 | 재단법인 한국기계전기전자시험연구원 | 전류 및 전압 수집 장치 |
CN109841535B (zh) * | 2019-01-31 | 2022-04-15 | 合肥鑫晟光电科技有限公司 | 阵列基板及其制备方法、显示面板、显示装置 |
US11378618B2 (en) * | 2020-04-29 | 2022-07-05 | Innolux Corporation | Method for manufacturing electronic device having a seed layer on a substrate |
CN115050727B (zh) * | 2022-08-15 | 2022-11-15 | 之江实验室 | 晶圆处理器及用于其的电路自测试和供电管理装置 |
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Also Published As
Publication number | Publication date |
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JP5269897B2 (ja) | 2013-08-21 |
KR20110005713A (ko) | 2011-01-18 |
JPWO2009147723A1 (ja) | 2011-10-20 |
KR101147677B1 (ko) | 2012-05-21 |
TW201005305A (en) | 2010-02-01 |
US20110128031A1 (en) | 2011-06-02 |
US8466702B2 (en) | 2013-06-18 |
TWI387762B (zh) | 2013-03-01 |
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