WO2009142265A1 - Élément électroluminescent à semi-conducteur au nitrure du groupe iii et son procédé de fabrication, et lampe - Google Patents

Élément électroluminescent à semi-conducteur au nitrure du groupe iii et son procédé de fabrication, et lampe Download PDF

Info

Publication number
WO2009142265A1
WO2009142265A1 PCT/JP2009/059357 JP2009059357W WO2009142265A1 WO 2009142265 A1 WO2009142265 A1 WO 2009142265A1 JP 2009059357 W JP2009059357 W JP 2009059357W WO 2009142265 A1 WO2009142265 A1 WO 2009142265A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
iii nitride
group iii
nitride semiconductor
substrate
Prior art date
Application number
PCT/JP2009/059357
Other languages
English (en)
Japanese (ja)
Inventor
裕直 篠原
Original Assignee
昭和電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昭和電工株式会社 filed Critical 昭和電工株式会社
Publication of WO2009142265A1 publication Critical patent/WO2009142265A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the present invention relates to a group III nitride semiconductor light-emitting device having a light-emitting diode (LED) structure and an emission wavelength of 490 to 570 nm, a method for manufacturing the same, and a lamp.
  • LED light-emitting diode
  • Group III nitride semiconductors have attracted attention as semiconductor materials for light-emitting elements that emit light of short wavelengths.
  • MOCVD method metal organic chemical vapor deposition method
  • MBE method molecular beam epitaxy method
  • an n-type semiconductor layer, a light emitting layer, and a p type semiconductor layer made of a group III nitride semiconductor are arranged in this order on a sapphire single crystal substrate.
  • stacked is mentioned.
  • the sapphire substrate is an insulator. Therefore, the element structure using the sapphire substrate generally has a structure in which the positive electrode formed on the p-type semiconductor layer and the negative electrode formed on the n-type semiconductor layer are present on the same plane in the lateral direction. .
  • a face-up method in which a transparent electrode is used as a positive electrode and light is extracted from the p-type semiconductor side, and a highly reflective film such as Ag is used as a positive electrode from the sapphire substrate side.
  • a flip chip type that extracts light.
  • External quantum efficiency is used as an index of the output of such a light emitting element. If the external quantum efficiency is high, it can be said that the light-emitting element has a high output.
  • the external quantum efficiency is a value obtained by multiplying the internal quantum efficiency and the light extraction efficiency.
  • the internal quantum efficiency is a rate at which the energy of current injected into the device is converted into light in the light emitting layer.
  • the light extraction efficiency is a ratio of light that can be extracted outside the light emitting element among light generated in the light emitting layer. Therefore, in order to improve the external quantum efficiency, it is necessary to improve the light extraction efficiency.
  • an element that emits green light having an emission wavelength of 490 to 570 nm is used in various fields that require such an emission color.
  • the emission wavelength is a long wavelength of 490 nm or longer, the emission color is green.
  • the emission wavelength is around 505 nm, a blue-green color used for a traffic light or the like is exhibited.
  • the emission wavelength is in the vicinity of 525 nm, a pure green color that is used as a light source for three primary colors such as a display can be obtained.
  • the emission wavelength when the emission wavelength is near 560 nm, a yellowish green color used for, for example, a pilot lamp is obtained, and when the emission wavelength is 570 nm, the emission color becomes a color tone close to yellow.
  • the emission wavelength needs to be 490 nm or more.
  • indium (In) contained in a well layer (active layer) included in the light emitting layer is used. It is necessary to increase the concentration. However, when the indium concentration is increased, the lattice constant increases, and the difference in lattice constant between the lower layer (substrate side) layer and the barrier layer located below the light emitting layer increases. For this reason, there is a problem that distortion occurs in the light emitting layer, leading to a decrease in internal quantum efficiency. Moreover, indium is easy to evaporate. For this reason, in the temperature rising process for forming the barrier layer, indium evaporates from the well layer, and as a result, the crystallinity is lowered and distortion occurs in the light emitting layer, leading to a decrease in internal quantum efficiency. appear.
  • the present invention has been made in view of the above problems, and provides a group III nitride semiconductor light-emitting device excellent in light extraction efficiency and a manufacturing method thereof without reducing the internal quantum efficiency of an LED structure that emits green light.
  • an object of the present invention is to provide a lamp that uses the above-mentioned group III nitride semiconductor light emitting device and has excellent light emission characteristics.
  • a group III nitride semiconductor light emitting device in which an LED structure is formed on a single crystal group III nitride semiconductor layer formed on a substrate,
  • the substrate has a main surface composed of a flat portion made of a (0001) C plane and a plurality of convex portions, and a back surface, and the base width of the convex portion is 0.05 to 1.5 ⁇ m
  • the group III nitride semiconductor layer is formed so as to cover the planar portion and the convex portion on the main surface of the substrate by epitaxial growth of the group III nitride semiconductor.
  • the group III nitride semiconductor light-emitting device characterized in that the light emission wavelength of the LED structure is in the range of 490 to 570 nm.
  • the group III nitride semiconductor light-emitting device according to the above [1], wherein the convex portion is configured by a surface non-parallel to the C-plane.
  • the convex portion has a base width of 0.05 to 1 ⁇ m, a height in the range of 0.05 to 1 ⁇ m, and 1 ⁇ 4 or more of the base width, and between adjacent convex portions.
  • the LED structure includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, each of which is made of a group III nitride semiconductor, in this order on the main surface of the substrate.
  • the group III nitride semiconductor light-emitting device according to any one of [8].
  • a buffer layer made of polycrystalline Al x Ga 1-x N (0 ⁇ x ⁇ 1) and having a thickness of 0.01 to 0.5 ⁇ m is stacked on the main surface of the substrate by sputtering.
  • a buffer layer made of single-crystal Al x Ga 1-x N (0 ⁇ x ⁇ 1) and having a thickness of 0.01 to 0.5 ⁇ m is stacked on the main surface of the substrate by sputtering.
  • the group III nitride semiconductor light-emitting device according to any one of the above [1] to [10], wherein the group III nitride semiconductor layer is stacked on the buffer layer.
  • the n-type semiconductor layer includes an n-type cladding layer
  • the p-type semiconductor layer includes a p-type cladding layer
  • at least one of the n-type cladding layer and the p-type cladding layer has a superlattice structure.
  • the group III nitride semiconductor light-emitting device according to any one of the above [8] to [12], comprising: [14] Any one of [1] to [13] above, wherein a half width of an X-ray rocking curve (XRC) in the (10-10) plane of the group III nitride semiconductor layer is 150 arcsec or more.
  • XRC X-ray rocking curve
  • a substrate processing step for forming a main surface comprising: An epitaxial step of forming a single crystal group III nitride semiconductor layer covering the planar portion and the convex portion by epitaxially growing a group III nitride semiconductor on the main surface of the substrate;
  • a method of manufacturing a group III nitride semiconductor light emitting device comprising: an LED stacking step of forming an LED structure having an emission wavelength in the range of 490 to 570 nm on the group III nitride semiconductor layer.
  • the group III nitride semiconductor light-emitting device according to [15], wherein in the substrate processing step, the surface of the convex portion is formed by a surface non-parallel to the C-plane Manufacturing method.
  • the base width is in the range of 0.05 to 1 ⁇ m
  • the height is in the range of 0.05 to 1 ⁇ m
  • a mask pattern is formed on the (0001) C surface of the substrate using one of a stepper exposure method, a nanoimprint method, an electron beam (EB) exposure method, and a laser exposure method.
  • the LED structure is formed by stacking an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer made of a group III nitride semiconductor in this order on the main surface of the substrate.
  • the method for producing a group III nitride semiconductor light-emitting device according to any one of the above [15] to [23], wherein [25] The method for producing a group III nitride semiconductor light-emitting element according to the above [24], wherein, in the LED stacking step, an In concentration of a light-emitting layer provided in the LED structure is 7% by mass or more.
  • a thickness of 0.1% of the polycrystalline Al x Ga 1-x N (0 ⁇ x ⁇ 1) is formed on the main surface of the substrate.
  • the group III nitride semiconductor light-emitting device according to any one of [15] to [25], wherein a buffer layer forming step of laminating a buffer layer of 01 to 0.5 ⁇ m by a sputtering method is included. Production method.
  • the n-type semiconductor layer includes an n-type cladding layer
  • the p-type semiconductor layer includes a p-type cladding layer
  • the n-type cladding layer and the p-type cladding layer are the n-type cladding layer and the p-type cladding layer.
  • XRC line rocking curve
  • the substrate has a flat surface composed of a (0001) C plane, a main surface composed of a plurality of convex portions, and a back surface.
  • the base width is 0.05 to 1.5 ⁇ m.
  • the group III nitride semiconductor layer is formed by epitaxially growing a group III nitride semiconductor on the main surface of the substrate so as to cover the planar portion and the convex portion.
  • the emission wavelength in the LED structure is in the range of 490 to 570 nm.
  • the present invention can appropriately control the crystallinity of the group III nitride semiconductor layer and suppress the occurrence of lattice mismatch with the LED structure further stacked on this layer. can do. Moreover, the said effect becomes more remarkable and the exceptional effect is acquired because the convex part of a board
  • substrate is comprised by the surface non-parallel to C surface. With these characteristics, there is no distortion in the LED structure that emits green light, and it is possible to suppress the decrease in internal quantum efficiency and the occurrence of leakage current, so that the electrical characteristics are excellent and the light emission output is high. A group nitride semiconductor light emitting device is obtained.
  • the light emitting device of the present invention includes an n-type cladding layer and / or a p-type cladding layer, and when the n-type cladding layer and / or the p-type cladding layer has a superlattice structure, the output is remarkably high. Thus, a light-emitting element having excellent electrical characteristics can be obtained.
  • a plurality of convex portions having a base width of 0.05 to 1.5 ⁇ m are formed on the plane composed of the (0001) C plane of the substrate. Is done.
  • a substrate processing step for forming a main surface composed of a flat portion and a convex portion on a substrate, and a group III nitride semiconductor is epitaxially grown on the main surface of the substrate to cover the flat surface and the convex portion.
  • an epitaxial process for forming the group III nitride semiconductor layer and an LED stacking process for forming the LED structure with an emission wavelength in the LED structure in the range of 490 to 570 nm are included.
  • a group III nitride semiconductor layer with properly controlled crystallinity can be formed, and it is possible to suppress the occurrence of lattice mismatch with the LED structure formed on this layer, distortion, etc. It is possible to form an LED structure without causing the above.
  • the said effect becomes more remarkable by using the method of forming the convex part comprised by the surface which is non-parallel with respect to C surface in a board
  • the lamp according to the present invention has excellent light emission characteristics.
  • FIG. 1 It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and is sectional drawing which shows the light-emitting device in which the LED structure was formed on the laminated structure shown in FIG. It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and is an expanded sectional view which shows the principal part of FIG. It is the schematic explaining typically an example of the lamp
  • FIG. 1 is a diagram for explaining a part of a light emitting device 1 according to the present invention.
  • FIG. 1 is a cross-sectional view showing a laminated structure in which a buffer layer and a single crystal underlayer (group III nitride semiconductor layer) 103 are formed on a main surface 10 of a substrate 101.
  • FIG. FIG. 2 is a perspective view for explaining the substrate 101 shown in FIG.
  • FIG. 3 is a cross-sectional view showing the light-emitting element 1 in which the LED structure 20 is formed on the base layer (group III nitride semiconductor layer) 103 having the stacked structure shown in FIG.
  • reference numeral 107 denotes a positive electrode bonding pad
  • reference numeral 108 denotes a negative electrode bonding pad.
  • 4 is a partial cross-sectional view showing cross sections of the n-type semiconductor layer 104, the light-emitting layer 105, and the p-type semiconductor layer 106 in the light-emitting element 1 shown in FIG.
  • a light-emitting element 1 according to the present invention is schematically configured as in the example shown in FIGS. 1 to 4, and is formed on a single crystal underlayer (group III nitride semiconductor layer) 103 formed on a substrate 101.
  • An LED structure 20 is formed.
  • the substrate 101 has a main surface 10 composed of a back surface, a flat portion 11 made of a (0001) C plane, and a plurality of convex portions 12 made of a surface 12c non-parallel to the C surface.
  • the base width of the convex portion 12 is 0.05 to 3 ⁇ m.
  • the underlayer 103 is formed by epitaxially growing a group III nitride semiconductor on the main surface 10 of the substrate 101 so as to cover the flat portion 11 and the convex portion 12.
  • the emission wavelength in the LED structure 20 is in the range of 490 to 570 nm.
  • a buffer layer 102 is provided on the substrate 101, and a base layer 103 is further formed on the buffer layer 102.
  • the light-emitting element 1 which is an example of the present invention described in the present embodiment is a single electrode type as shown in FIG.
  • a buffer layer 102 and an LED structure (Group III nitride semiconductor layer) 20 made of a Group III nitride semiconductor containing Ga as a Group III element are formed on the substrate 101 as described above.
  • the LED structure 20 provided in the light-emitting element 1 includes an n-type semiconductor layer 104, a light-emitting layer 105, and a p-type semiconductor layer 106 stacked in this order.
  • the group III nitride semiconductor light-emitting device of the present invention has a light emission wavelength of 490 nm by controlling the indium (In) content of the well layer constituting the light-emitting layer to be high concentration in the LED structure described in detail later. It exhibits green light emission as described above, and more preferably exhibits an emission wavelength in the range of 490 to 570 nm.
  • the element of the present invention can emit good green light.
  • the laminated structure of the light emitting element 1 will be described in detail.
  • the material that can be used for the substrate 101 is not particularly limited as long as it is a substrate material on which a group III nitride semiconductor crystal is epitaxially grown, and various materials can be selected and used. it can.
  • sapphire SiC, silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide Lanthanum strontium oxide aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten, molybdenum and the like.
  • sapphire is particularly preferable. It is desirable that an intermediate layer (buffer layer) 102 be formed on the c-plane of the sapphire substrate.
  • the buffer layer 102 is preferably used.
  • the buffer layer 102 in the case where an underlayer 103 described later is formed by a method using ammonia after forming the buffer layer 102 without using ammonia, the buffer layer 102 also functions as a coat layer. It is effective in preventing chemical alteration. It is also preferable to form the buffer layer 102 by sputtering. In the case where the buffer layer 102 is formed by a sputtering method, the temperature of the substrate 101 can be kept low. Therefore, even when the substrate 101 made of a material that decomposes at a high temperature is used, the formation of each layer on the substrate without damaging the substrate 101 by forming the buffer layer 102 by sputtering. A membrane is possible.
  • a plurality of convex portions 12 are formed on the main surface 10 of the substrate 101 used in this embodiment, as in the example shown in FIG.
  • a portion of the main surface 10 of the substrate 101 where the convex portion 12 is not formed is constituted by a flat portion 11 made of a (0001) C plane. Therefore, as in the example shown in FIGS. 2 and 3, the main surface 10 of the substrate 101 is composed of a flat surface portion 11 made of a C surface and a plurality of convex portions 12.
  • the surface of the convex portion 12 is a surface 12 c that is non-parallel to the C plane.
  • the C surface does not appear on the surface 12c.
  • the convex portions 12 shown in FIGS. 1 and 2 have an obstructed bowl-like (hemispherical) shape. That is, the planar shape of the base 12a (the shape of the bottom surface of the convex portion 12) is substantially circular, and the convex portion 12 has a shape in which the outer shape (cross-sectional area) gradually decreases toward the top.
  • the side surface 12b of the convex portion 12 is curved outward.
  • the planar arrangement of the protrusions 12 is arranged in a grid pattern at regular intervals.
  • the base width d 1 is 0.05 to 1.5 ⁇ m
  • the height h is 0.05 to 1 ⁇ m
  • the distance d 2 between the adjacent convex portions 12 is 0.5 to 5 times the base width d 1 .
  • the base width d 1 of the convex portion 12 refers to the maximum width at the bottom surface (base portion 12 a) of the convex portion 12.
  • the distance d 2 between the adjacent convex portions 12 refers to the shortest distance between the edge of the base portion 12 a of the convex portion 12 and the edge of the base portion 12 a of the convex portion 12 closest to the convex portion 12.
  • the distance d 2 between the convex portions 12 adjacent to each other is preferably 0.5 to 5 times the base width d 1 . If the interval d 2 between the convex portions 12 adjacent is less than 0.5 times the base width d 1 from each other, when epitaxially growing a base layer 103 of n-type semiconductor layer 104 (semiconductor layer 30) is formed thereon. In addition, it is difficult to promote crystal growth from the C-plane flat portion 11, and it becomes difficult to completely fill the convex portion 12 with the underlayer 103, and the flatness of the surface 103 a of the underlayer 103 is sufficiently high. It may not be obtained.
  • the base width d 1 is preferably 0.05 to 1.5 ⁇ m.
  • the base width d 1 is less than 0.05 ⁇ m, when a group III nitride semiconductor light emitting device is formed using the substrate 101, the effect of irregularly reflecting light may not be obtained sufficiently.
  • the base width d 1 exceeds 1.5 ⁇ m, it may be difficult to completely fill the convex portion 12 and epitaxially grow the base layer 103. Further, even if an underlayer with good flatness and crystallinity can be formed, the distortion between the underlayer and the light-emitting layer may increase, leading to a decrease in internal quantum efficiency.
  • the base width d 1 is within the above range, the light emission output of the light emitting element can be further improved as the configuration is made smaller.
  • the base width d 1 is more preferably 0.05 to 1 ⁇ m.
  • the height h of the convex portion 12 is preferably 0.05 to 1 ⁇ m.
  • the height h of the convex portion 12 is less than 0.05 ⁇ m, when a group III nitride semiconductor light emitting device is formed using the substrate 101, the effect of irregularly reflecting light may not be sufficiently obtained.
  • the height h of the convex portion 12 exceeds 1 ⁇ m, it may be difficult to epitaxially grow the base layer 103 by filling the convex portion 12, and the flatness of the surface 14a of the base layer 103 may not be sufficiently obtained. is there.
  • the height h of the convex portion 12 is preferably 1/4 or more base portion width d 1. More preferably, it is 1 ⁇ 2 or more and 1/1 or less. When the height h of the convex portion 12 is less than 1 ⁇ 4 of the base width d 1 , the effect of irregularly reflecting light when the substrate 101 is used to form a group III nitride semiconductor light-emitting device and the light extraction efficiency are improved. The effect of improving may not be obtained sufficiently.
  • the shape of the convex part 12 is not limited to the example shown in FIG.1 and FIG.2, and what kind of shape may be sufficient if it is comprised from the surface non-parallel to C surface.
  • the planar shape of the base may be substantially polygonal, and the outer shape may gradually decrease toward the top, or the side surface 12 may be curved outward.
  • the shape of the convex part 12 may be a substantially conical shape or a substantially polygonal pyramid whose side width gradually decreases toward the top.
  • the side surface may protrude outward.
  • the side surface inclination angle may be a shape that changes in multiple stages, for example, in two stages.
  • planar arrangement of the protrusions 12 is not limited to the example shown in FIGS. 1 and 2 (a grid pattern), and may be arranged at equal intervals or may be arranged at non-equal intervals. . Further, the planar arrangement of the convex portions 12 may be a quadrangular shape, a triangular shape, or a random shape.
  • the convex portion 12 provided on the substrate 101 can be formed by etching the substrate 101 by a manufacturing method described in detail later.
  • the manufacturing method is not limited to this.
  • the convex portion may be formed by depositing another material forming the convex portion on the C surface of the substrate 101 on the substrate.
  • a method for depositing another material for forming a convex portion on the substrate for example, a sputtering method, a vapor deposition method, a CVD method, or the like can be used.
  • the material forming the convex portion it is preferable to use a material having a refractive index substantially equal to the material of the substrate, such as an oxide or a nitride.
  • the substrate is a sapphire substrate, for example, SiO 2 , Al 2 O 3 , SiN, ZnO, or the like can be used.
  • the substrate 101 since the substrate 101 has the above-described configuration including the main surface 10 including the flat portion 11 and the convex portion 12, the interface between the substrate 101 and the underlayer 103, which will be described in detail later, is a buffer layer. Concavities and convexities are formed through 102. For this reason, confinement of light inside the light emitting element due to irregular reflection of light due to the unevenness is reduced, and the light emitting element 1 having excellent light extraction efficiency can be realized. Further, since the substrate 101 has the above-described structure, the crystallinity of the base layer 103 can be appropriately controlled, so that a lattice is formed between the light emitting layer 105 (well layer 105b) provided in the LED structure 20 described later and the base layer 103.
  • Inconsistencies are prevented from occurring. Thereby, even when the In concentration of the well layer 105b provided in the light emitting layer 105 is set to a high concentration to constitute the light emitting element 1 that emits green light, the occurrence of distortion or the like in the well layer 105b is suppressed. Accordingly, it is possible to realize the light emitting device 1 that has excellent internal quantum efficiency, has a high light emission output, and is excellent in electrical characteristics by suppressing generation of leakage current.
  • buffer layer In the present invention, it is preferable to form the buffer layer 102 on the main surface 10 of the substrate 101 and form an underlayer 103 described later on the buffer layer 102.
  • the buffer layer 102 is stacked on the substrate 101 with a composition of Al X Ga 1-X N (0 ⁇ x ⁇ 1).
  • the buffer layer can be formed by a reactive sputtering method in which a gas containing a group V element and a metal material are activated and reacted with plasma.
  • a film formed by a method using a plasma metal raw material as in this embodiment has an effect that alignment is easily obtained.
  • the buffer layer 102 has a function of alleviating the difference in lattice constant between the substrate 101 and the base layer 103 and, as a result, easily forming a C-axis oriented single crystal layer on the C plane of the substrate 101. Therefore, when a single-crystal group III nitride semiconductor layer (underlayer 103) is stacked on the buffer layer 102 formed on the substrate, the underlayer has better crystallinity than the case without the buffer layer. 103 can be formed. In the present embodiment, it is most preferable to form the buffer layer 102 between the substrate 101 and the base layer 103, but a configuration in which the buffer layer is omitted may be employed.
  • the buffer layer 102 preferably has a composition of Al X Ga 1-X N (0 ⁇ x ⁇ 1), and more preferably AlN.
  • the buffer layer laminated on the substrate preferably has a composition containing Al, and may be a group III nitride compound represented by the general formula Al X Ga 1-X N (0 ⁇ x ⁇ 1). Any material can be used. Furthermore, it can also be set as the composition containing As and P as V group.
  • the Al composition is more preferably 50% or more.
  • a material constituting the buffer layer 102 a material having the same crystal structure as that of the group III nitride semiconductor can be used, but the length of the lattice is close to that of the group III nitride semiconductor constituting the underlayer described later. And nitrides of group IIIa elements of the periodic table are particularly preferred.
  • the group III nitride crystal forming the buffer layer has a hexagonal crystal structure, and can be formed into a single crystal film by controlling the film formation conditions. Further, the group III nitride crystal can be formed into a columnar crystal (polycrystal) having a texture based on a hexagonal column by controlling the film forming conditions. Note that the columnar crystal described here is a crystal which is separated by forming a crystal grain boundary between adjacent crystal grains, and is itself a columnar shape as a longitudinal sectional shape.
  • the buffer layer 102 preferably has a single crystal structure from the viewpoint of the buffer function.
  • the group III nitride crystal has a hexagonal crystal and forms a structure based on a hexagonal column.
  • the buffer layer 102 having the single crystal structure as described above is formed over the substrate 101, the buffer function of the buffer layer 102 effectively operates. Therefore, the group III nitride semiconductor layer formed thereon is a crystal film having good orientation and crystallinity.
  • the thickness of the buffer layer 102 is preferably in the range of 0.01 to 0.5 ⁇ m. By setting the thickness of the buffer layer 102 in the above range, it has good orientation and functions effectively as a coating layer when each layer made of a group III nitride semiconductor is formed on the buffer layer 102. The buffer layer 102 is obtained. When the film thickness of the buffer layer 102 is less than 0.01 ⁇ m, a sufficient function as the above-described coat layer cannot be obtained, and the buffer function that alleviates the difference in lattice constant between the substrate 101 and the base layer 103. May not be sufficiently obtained.
  • the buffer layer 102 when the buffer layer 102 is formed with a film thickness exceeding 0.5 ⁇ m, the film formation processing time is prolonged and the productivity is lowered although there is no change in the buffer function and the function as the coat layer. There is.
  • the thickness of the buffer layer 102 is more preferably in the range of 0.02 to 0.1 ⁇ m.
  • the underlayer (group III nitride semiconductor layer) 103 provided in the light emitting device 1 of the present invention is made of a group III nitride semiconductor as described above, and is laminated on the buffer layer 102 by a conventionally known MOCVD method. can do.
  • the base layer 103 described in this example is formed of a group III nitride semiconductor on the main surface 10 of the substrate 101 via the buffer layer 102 so as to cover the planar portion 11 and the convex portion 12. It is formed by epitaxial growth.
  • the use of an Al y Ga 1-y N layer (0 ⁇ y ⁇ 1, preferably 0 ⁇ y ⁇ 0.5, more preferably 0 ⁇ y ⁇ 0.1) as the base layer 103 provides good crystallinity. It is more preferable in that the underlayer 103 can be formed.
  • a material different from that of the buffer layer 102 may be used as the material of the base layer 103, but the same material as that of the buffer layer 102 may be used.
  • the underlayer 103 may have a configuration in which n-type impurities are doped in the range of 1 ⁇ 10 17 to 1 ⁇ 10 19 atoms / cm 3 as necessary, but may be undoped ( ⁇ 1 ⁇ 10 17 atoms / cm 3). 3 ). Undoped is preferable in that good crystallinity can be maintained.
  • the base layer 103 is doped with a dopant so that the substrate 101 is conductive, whereby electrodes can be provided above and below the light emitting element.
  • a chip structure in which the positive electrode and the negative electrode are provided on the same surface of the light-emitting element is employed.
  • the base layer 103 be an undoped crystal because crystallinity is improved.
  • the n-type impurity doped in the base layer 103 is not particularly limited, and examples thereof include Si, Ge, and Sn, and preferably Si and Ge.
  • the thickness of the underlayer 103 is preferably in the range of 1 to 8 ⁇ m, from the viewpoint of obtaining an underlayer with good crystallinity, and in the range of 2 to 5 ⁇ m shortens the process time required for film formation. This is more preferable in terms of productivity.
  • the maximum thickness H of the base layer 103 illustrated in FIG. 1 is not less than twice the height h of the convex portion 12 of the substrate 101 because a flat base layer 103 having a surface 103a can be obtained.
  • the maximum thickness H of the base layer 103 is smaller than twice the height h of the convex portion 12, the flatness of the surface 103a of the base layer 103 grown so as to cover the convex portion 12 becomes insufficient. There is a possibility that the crystallinity of each layer which is laminated on the underlayer 103 and constitutes the LED structure 20 is lowered.
  • the X-ray rocking curve (XRC) half width of the (10-10) plane of the underlayer 103 is 150 arcsec or more. If the XRC half width of the underlayer 103 is 150 arcsec or more, the crystallinity of the underlayer 103 does not become too high and is controlled within an appropriate range. Therefore, the LED structure 20, particularly the light emitting layer 105, laminated on the surface 103 a is prepared. The well layer 105b is free from distortion and becomes a good crystal layer.
  • the XRC half-width of the (10-10) plane of the underlayer is an index of crystallinity, and the smaller this value, the higher the crystallinity of the underlayer.
  • the half-value width affects the crystallinity of the LED structure formed thereon, a method of increasing the crystallinity of the entire light-emitting element by setting the value as small as possible has been employed.
  • a light emitting element that emits green light with an emission wavelength of 490 to 570 nm as in the present invention, it is necessary to increase the In concentration of the well layer provided in the light emitting element. Lattice constant increases.
  • the crystallinity of the underlayer 103 is set within an appropriate range.
  • Well controlled In order to obtain green light emission, even when the In concentration of the well layer 105b of the light emitting layer 105 provided in the LED structure 20 is increased, there is a large lattice mismatch between the base layer 103 and the well layer 105b. It is suppressed from occurring. Accordingly, the occurrence of defects such as strain in the well layer 105b is suppressed, and the internal quantum efficiency is not lowered, so that the light emitting element 1 having a high light emission output can be realized.
  • XRC X-ray rocking curve
  • the XRC half width of the underlayer 103 can be appropriately controlled by the base width d 1 of the convex portion 12 formed on the substrate 101 described above.
  • the base width d 1 of the convex portion 12 of the substrate 101 is 1 ⁇ m
  • the XRC half width of the base layer 103 is about 150 to 200 arcsec. If the base width d 1 is kept within the preferred range of the present invention, the half width tends to be 150 arcsec or more.
  • the XRC half-value width of the underlayer is about 100 arcsec or more and less than 150 arcsec, and the crystallinity of the underlayer is greatly enhanced.
  • the XRC half-value width of the (10-10) plane of the underlayer 103 is 150 arcsec or more from the viewpoint of controlling the crystallinity of the underlayer 103 appropriately.
  • crystallinity will fall too much when the XRC half value width of a base layer exceeds 250 arcsec, it is preferable to control so that it may become 250 arcsec or less.
  • the XRC half-value width of the (10-10) plane on the side of the mold semiconductor layer 106 has the same tendency as that of the base layer 103. Therefore, in the present invention, the XRC half width of the (10-10) plane of the underlayer is used as an index representing crystallinity.
  • the LED structure 20 includes an n-type semiconductor layer 104, a light-emitting layer 105, and a p-type semiconductor layer 106 each made of a group III nitride semiconductor. By forming each layer of such an LED structure 20 by MOCVD, a layer with higher crystallinity can be obtained.
  • the n-type semiconductor layer 104 is generally composed of an n-type contact layer 104a and an n-type cladding layer 104b.
  • the n-type contact layer 104a can also serve as the n-type cladding layer 104b.
  • the n-type contact layer 104a is a layer for providing a negative electrode.
  • the n-type contact layer 104a is preferably composed of an Al x Ga 1-x N layer (0 ⁇ x ⁇ 1, preferably 0 ⁇ x ⁇ 0.5, more preferably 0 ⁇ x ⁇ 0.1).
  • the n-type contact layer 104a is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 ⁇ 10 17 to 1 ⁇ 10 20 / cm 3 , preferably 1 ⁇ 10 18 to 1 ⁇ 10 19 /. Containing at a concentration of cm 3 is preferable in terms of maintaining good ohmic contact with the negative electrode.
  • an n-type impurity For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.
  • the film thickness of the n-type contact layer 104a is preferably 0.5 to 5 ⁇ m, and more preferably set to a range of 1 to 3 ⁇ m. When the film thickness of the n-type contact layer 104a is in the above range, the crystallinity of the semiconductor is maintained well.
  • the n-type cladding layer 104b is a layer that injects carriers into the light emitting layer 105 and confines carriers.
  • the n-type cladding layer 104b can be formed of AlGaN, GaN, GaInN, or the like. Further, a structure in which these are heterojunctioned or a superlattice structure in which a plurality of layers are laminated may be used.
  • the n-type cladding layer 104b is formed of GaInN, it is desirable to make the band gap of the n-type cladding layer 104b larger than the band gap of GaInN of the light emitting layer 105.
  • the film thickness of the n-type cladding layer 104b is not particularly limited, but is preferably 0.005 to 0.5 ⁇ m, and more preferably 0.005 to 0.1 ⁇ m.
  • the n-type doping concentration of the n-type cladding layer 104b is preferably 1 ⁇ 10 17 to 1 ⁇ 10 20 / cm 3 , more preferably 1 ⁇ 10 18 to 1 ⁇ 10 19 / cm 3 . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.
  • n-type cladding layer 104b is a layer including a superlattice structure, a detailed illustration is omitted, but an n-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less.
  • the n-type cladding layer 104b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. Preferably, either the n-side first layer or the n-side second layer is in contact with the active layer (light-emitting layer 105).
  • compositions of the n-side first layer and the n-side second layer as described above include, for example, AlGaN-based Al (sometimes simply referred to as AlGaN) and GaInN-based (including simply InGa). Or a composition of GaN.
  • the n-side first layer and the n-side second layer have a GaInN / GaN alternating structure, an AlGaN / GaN alternating structure, a GaInN / AlGaN alternating structure, and a GaInN / GaInN alternating structure having a different composition (the present invention).
  • the n-side first layer and the n-side second layer are preferably GaInN / GaInN having different GaInN / GaN structures or different compositions.
  • the n-side first layer and the n-side second layer which are superlattice layers, are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Most preferably it is. If the thickness of each of the n-side first layer and the n-side second layer forming the superlattice layer exceeds 100 angstroms, crystal defects are likely to occur, which is not preferable.
  • the n-side first layer and the n-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure.
  • the impurity to be doped conventionally known impurities can be applied to the material composition without any limitation.
  • an n-type cladding layer is formed of an alternate structure of GaInN / GaN or a combination of an n-side first layer and an n-side second layer having an alternate structure of GaInN / GaInN having different compositions, Si as an impurity. Is preferred.
  • the n-side superlattice multilayer film as described above may be formed in a multilayer structure using the same composition typified by GaInN, AlGaN, and GaN while appropriately turning ON / OFF doping.
  • the n-type cladding layer 104b has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting element 1 having excellent electric characteristics can be obtained.
  • Examples of the light emitting layer 105 stacked on the n-type semiconductor layer 104 include a light emitting layer 105 having a single quantum well structure or a multiple quantum well structure.
  • a well layer having a quantum well structure as shown in FIG. 4 for example, in the case of a structure exhibiting blue light emission, a composition having a composition of Ga 1-y In y N (0 ⁇ y ⁇ 0.04) is usually used.
  • a group III nitride semiconductor is used, in the case of the well layer 105b exhibiting green light emission as in the present invention, the composition of indium such as Ga 1-y In y N (0.07 ⁇ y ⁇ 0.20) is used. The one with increased is used.
  • the Ga 1-y In y N is used as the well layer 105b, and Al x Ga 1-x N (0 ⁇ z ⁇ 0.3) is preferably the barrier layer 105a.
  • the well layer 105b and the barrier layer 105a may or may not be doped with impurities depending on the design.
  • the film thickness of the well layer 105b can be, for example, a film thickness at which a quantum effect can be obtained, that is, 1 to 10 nm, and more preferably 2 to 6 nm from the viewpoint of light emission output.
  • the emission wavelength In order for the group III nitride semiconductor light emitting device to emit green light, the emission wavelength needs to be 490 nm or more. In order to obtain good green light emission, the emission wavelength is more preferably in the range of 490 to 570 nm. For this reason, in the light emitting element 1 of the present invention, the In composition ratio of the well layer 105b forming the light emitting layer 105 is preferably 7% or more. If the In concentration of the well layer 105b is within this range, good green light emission with an emission wavelength of 490 to 570 nm can be obtained.
  • the light emitting element 1 emits green light when the In concentration of the well layer 105b is as high as described above and the emission wavelength is in the above range.
  • the well layer 105b included in the light emitting layer 105 is configured with a high In concentration
  • the crystallinity of the underlying layer 103 which is the lower layer
  • the internal quantum efficiency is reduced due to crystal defects in the well layer, and thus the emission intensity is low. End up.
  • the substrate 101 has the main surface 10 composed of the flat portion 11 and the convex portion 12 and the back surface thereof, and the base width of the convex portion 12 is 0.05 to 1.5 ⁇ m.
  • a base layer 103 formed by epitaxially growing a single crystal group III nitride semiconductor is provided on the main surface 10 of the substrate 101 so as to cover the flat portion 11 and the convex portion 12.
  • a crystal does not grow from the parallel surface 12c, and a crystal oriented in the C-axis direction grows epitaxially only from the flat portion 11 made of the (0001) C plane. Therefore, the underlying layer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown so as to cover the convex portion 12 on the main surface 10 and does not cause crystal defects such as dislocations in the crystal. It becomes a controlled layer.
  • each layer constituting the LED structure 20 on the base layer 103 whose crystallinity is well controlled in an appropriate range as described above, the well layer 105b exhibiting green light emission with a high In concentration. Even when the layer is formed, the occurrence of lattice mismatch between the base layer 103 and the well layer 105b is suppressed. Thereby, crystal defects such as strain do not occur in the well layer 105b, it is possible to suppress a decrease in internal quantum efficiency and a leak current, and the light emitting device 1 having excellent electrical characteristics and high light emission output. It becomes possible to do.
  • the p-type semiconductor layer 106 is generally composed of a p-type cladding layer 106a and a p-type contact layer 106b.
  • the p-type contact layer 106b can also serve as the p-type cladding layer 106a.
  • the p-type cladding layer 106 a is a layer that performs confinement of carriers and injection of carriers in the light emitting layer 105.
  • the composition of the p-type cladding layer 106 a is not particularly limited as long as the composition is larger than the band gap energy of the light emitting layer 105 and can confine carriers in the light emitting layer 105.
  • a preferable composition is Al x Ga 1-x N (0 ⁇ x ⁇ 0.4).
  • the p-type cladding layer 106a is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer.
  • the film thickness of the p-type cladding layer 106a is not particularly limited, but is preferably 1 to 400 nm, and more preferably 5 to 100 nm.
  • the p-type doping concentration of the p-type cladding layer 106a is preferably 1 ⁇ 10 18 to 1 ⁇ 10 21 / cm 3 , more preferably 1 ⁇ 10 19 to 1 ⁇ 10 20 / cm 3 .
  • the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
  • the p-type cladding layer 106a may have a superlattice structure in which a plurality of layers are stacked.
  • the p-type cladding layer 106a is a layer including a superlattice structure, a detailed illustration is omitted, but a p-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less.
  • the p-type cladding layer 106a may include a structure in which p-side first layers and p-side second layers are alternately and repeatedly stacked.
  • composition of the p-side first layer and the p-side second layer as described above may be different compositions, for example, any composition of AlGaN, GaInN, or GaN.
  • the p-side first layer and the p-side second layer may have a GaInN / GaN alternating structure, an AlGaN / GaN alternating structure, or a GaInN / AlGaN alternating structure.
  • the p-side first layer and the p-side second layer preferably have an AlGaN / AlGaN or AlGaN / GaN alternating structure.
  • the superlattice layers of the p-side first layer and the p-side second layer are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Is most preferred. If the thickness of each of the p-side first layer and the p-side second layer forming the superlattice layer exceeds 100 angstroms, it becomes a layer containing many crystal defects and the like, which is not preferable.
  • the p-side first layer and the p-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure.
  • the impurity to be doped conventionally known impurities can be applied to the material composition without any limitation.
  • Mg is suitable as the impurity.
  • the p-side superlattice multilayer film as described above has the same composition as GaInN, AlGaN, or GaN, a multilayer structure can be produced by appropriately turning ON / OFF doping.
  • the p-type cladding layer 105a has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting device 1 having excellent electric characteristics can be obtained.
  • the p-type contact layer 106b is a layer for providing a positive electrode.
  • the p-type contact layer 106b preferably has a composition of Al x Ga 1-x N (0 ⁇ x ⁇ 0.4). When the Al composition is in the above range, it is preferable in that good crystallinity is maintained and good ohmic contact with the p ohmic electrode is possible.
  • the p-type contact layer 106b contains a p-type impurity (dopant) at a concentration of 1 ⁇ 10 18 to 1 ⁇ 10 21 / cm 3 , preferably 5 ⁇ 10 19 to 5 ⁇ 10 20 / cm 3 .
  • the thickness of the p-type contact layer 106b is not particularly limited, but is preferably 0.01 to 0.5 ⁇ m, and more preferably 0.05 to 0.2 ⁇ m. When the film thickness of the p-type contact layer 106b is within this range, it is preferable in terms of light emission output.
  • a translucent positive electrode 109 made of a translucent conductive oxide film layer is provided in contact with the p-type semiconductor layer 106.
  • the positive electrode bonding pad 107 is provided on a part of the translucent positive electrode 109.
  • the translucent positive electrode 109 is selected from ITO (In 2 O 3 —SnO 2 ), AZnO (ZnO—Al 2 O 3 ), ISnO (In 2 O 3 —ZnO), and GZO (ZnO—Ga 2 O 3 ).
  • ITO In 2 O 3 —SnO 2
  • AZnO ZnO—Al 2 O 3
  • ISnO In 2 O 3 —ZnO
  • GZO ZnO—Ga 2 O 3
  • the structure of the translucent positive electrode 109 can be used without any limitation, including a conventionally known structure.
  • the translucent positive electrode 109 may be formed so as to cover almost the entire surface of the p-type semiconductor layer 106, or may be formed in a lattice shape or a tree shape with a gap. After forming the translucent positive electrode 109, thermal annealing may be performed for the purpose of alloying or transparency, but it may not be performed.
  • the positive electrode bonding pad 107 is provided for electrical connection with a circuit board, a lead frame or the like.
  • various structures using Au, Al, Ni, Cu and the like are well known, and these known materials and structures can be used without any limitation.
  • the thickness of the positive electrode bonding pad 107 is preferably in the range of 100 to 1500 nm. Further, in view of the characteristics of the bonding pad, the larger the thickness, the higher the bondability. Therefore, the thickness of the positive electrode bonding pad 107 is more preferably 300 nm or more.
  • the negative electrode bonding pad 108 is formed in contact with the n-type semiconductor layer 104 of the LED structure 20. For this reason, when forming the negative electrode bonding pad 108, the light emitting layer 105 and the p-type semiconductor layer 106 are partially removed to expose the n-type contact layer of the n-type semiconductor layer 104, and the negative electrode bonding pad is formed thereon. 108 is installed.
  • compositions and structures are well known, and these well known compositions and structures can be used without any limitation, and can be provided by conventional means well known in this technical field.
  • the substrate 101 has the principal surface 10 composed of the planar portion 11 composed of the (0001) C plane and the plurality of convex portions 12.
  • the base width d 1 of the convex portion 12 is 0.05 to 1.5 ⁇ m
  • the base layer (group III nitride semiconductor layer) 103 covers the planar portion 11 and the convex portion 12 on the main surface 10 of the substrate 101.
  • the group III nitride semiconductor is formed by epitaxial growth.
  • the LED structure 20 has a configuration in which the emission wavelength is in the range of 490 to 570 nm.
  • the crystallinity of the underlayer 103 is appropriately controlled, so that it is possible to suppress the occurrence of lattice mismatch with the LED structure 20 stacked thereon.
  • the LED structure 20 that emits green light in particular, the well layer 105b included in the light emitting layer 105 is not distorted, and it is possible to suppress a decrease in internal quantum efficiency and a leakage current.
  • the light emitting device 1 having excellent optical characteristics and high light emission output can be obtained.
  • the interface between the substrate 101 and the base layer 103 is uneven through the buffer layer 102, light confinement inside the light-emitting element is reduced due to irregular reflection of light, so that light extraction efficiency is excellent.
  • the light emitting device 1 can be realized.
  • the n-type cladding layer 104b and / or the p-type cladding layer 105a has a layer structure including a superlattice structure, whereby the output is remarkably improved and the light emitting device 1 having excellent electrical characteristics is provided. can do.
  • a single crystal underlayer (group III nitride semiconductor layer) 103 is formed on a substrate 101, and an LED structure 20 is formed on the underlayer 103.
  • a plurality of convex portions 12 having a base width of 0.05 to 3 ⁇ m are formed on the flat portion 11 made of the (0001) C surface of the substrate 101, thereby forming the flat portion 11 on the substrate 101.
  • each process with which the manufacturing method of this invention is equipped is demonstrated in detail.
  • FIG. 2 is a diagram for explaining an example of a process for manufacturing the laminated structure shown in the schematic diagram of FIG. 1. Specifically, it is a perspective view showing a substrate 101 prepared in the manufacturing method of the present embodiment.
  • the substrate 101 has a main surface 10 composed of a flat surface portion 11 composed of a C surface and a plurality of convex portions 12 formed on the C surface.
  • a method for processing the substrate 101 as shown in FIG. 2 will be described.
  • the substrate processing step for example, by forming a plurality of convex portions 12 having a surface non-parallel to the C plane on the (0001) C plane of the sapphire substrate, the plane portion 11 and the convex portion 12 having the C plane are formed.
  • a substrate 101 having a main surface 10 made of is manufactured.
  • Such a substrate processing step includes, for example, a patterning step for forming a mask on the substrate 101 so as to have a planar arrangement of the convex portions 12 on the substrate 101, and a substrate 101 using the mask formed by the patterning step. And a method including an etching step of forming the convex portion 12 by etching.
  • a sapphire single crystal wafer having a (0001) C plane as a surface is used as a substrate material for forming the plurality of convex portions 12.
  • the substrate having the (0001) C plane as the surface includes a substrate in which an off angle is given in the range of ⁇ 3 ° from the (0001) direction in the plane direction of the substrate.
  • the surface that is not parallel to the C plane means a surface that is not within a range of ⁇ 3 ° from the (0001) C plane.
  • the patterning process can be performed by a general photolithography method.
  • the base width d 1 of the base portion 12a is preferably at 1.5 ⁇ m or less. Therefore, in order to uniformly pattern the entire surface of the substrate 101, it is preferable to use a stepper exposure method among photolithography methods.
  • an expensive stepper device is required, resulting in high cost.
  • a laser exposure method, a nanoimprint method, an electron beam (EB) exposure method, or the like used in the field of optical discs is used. Is preferred.
  • Examples of the method for etching the substrate in the etching process include a dry etching method and a wet etching method.
  • a dry etching method since the crystal plane of the substrate 101 is exposed, it is difficult to form the convex portion 12 formed of the surface 12c that is non-parallel to the C plane. For this reason, it is preferable to use a dry etching method in an etching process.
  • the convex part 12 constituted by the surface 12c non-parallel to the C plane can be formed, for example, by dry etching the substrate 101 until the mask formed in the patterning process described above disappears. More specifically, for example, a resist is formed on the substrate 101 and then patterned into a predetermined shape. Thereafter, the side surface of the resist having a predetermined shape is tapered by post-baking in which heat treatment is performed at 110 ° C. for 30 minutes using an oven or the like. Next, the convex portion 12 can be formed by performing dry etching under predetermined conditions that promote lateral etching until the resist disappears.
  • the convex portion 12 constituted by the surface 12c non-parallel to the C-plane may be formed by using a method in which the substrate is dry-etched using a mask and then the mask is removed again and the substrate 101 is dry-etched. I can do it. More specifically, for example, a resist is formed on the substrate 101 and patterned into a predetermined shape. Thereafter, the side surface of the resist having a predetermined shape is tapered by post-baking in which heat treatment is performed at 110 ° C. for 30 minutes using an oven or the like. Next, dry etching is performed under a predetermined condition that promotes lateral etching, and the dry etching is interrupted before the resist disappears.
  • the convex part 12 formed by such a method is excellent in in-plane uniformity of the height dimension.
  • the convex portion 12 constituted by the surface 12c non-parallel to the C plane can be formed by combining with the dry etching method.
  • the wet etching can be performed by using a mixed acid of phosphoric acid and sulfuric acid at a high temperature of 250 ° C. or higher.
  • the convex portion 12 is formed by performing a predetermined amount of wet etching using a high-temperature acid. can do.
  • the convex portion 12 By forming the convex portion 12 using such a method, the crystal plane is exposed on the slope constituting the side surface of the convex portion 12, and the angle of the slope constituting the side surface of the convex portion 12 is formed with good reproducibility. Can do. Further, a good crystal plane can be exposed to the main surface 10 with good reproducibility.
  • a mask made of a material resistant to an acid such as SiO 2 is formed and wet etching is performed, and then the mask is peeled off.
  • the convex portion 12 can also be formed by a method of performing dry etching under a predetermined condition for promoting lateral etching.
  • the convex part 12 formed by such a method is excellent in in-plane uniformity of the height dimension. Moreover, even when the convex part 12 is formed using such a method, the angle of the slope which comprises the side surface of the convex part 12 can be formed with sufficient reproducibility.
  • the convex part is formed of oxide or nitride, after depositing a material on the substrate, a mask patterned by a method such as nanoimprinting is formed, and the convex part is formed by dry etching or wet etching. It can be a method to do.
  • this invention is not limited to the said method.
  • a buffer layer 102 as shown in FIGS. 1 and 3 is laminated on the main surface 10 of the substrate 101 prepared by the above method.
  • the buffer layer 102 as shown in FIG. 1 is stacked on the main surface 10 of the substrate 101 by performing a buffer layer forming step after the substrate processing step and before the epitaxial step.
  • the buffer layer may be omitted. In this case, the buffer layer forming step may not be performed.
  • Pretreatment of substrate In this embodiment, after introducing the substrate 101 into the chamber of the sputtering apparatus and before forming the buffer layer 102, it is desirable to perform pretreatment using a method such as reverse sputtering by plasma treatment.
  • the surface can be prepared by exposing the substrate 101 to Ar or N 2 plasma.
  • organic matter and oxide attached to the surface of the substrate 101 can be removed by reverse sputtering in which plasma such as Ar gas or N 2 gas is applied to the surface of the substrate 101.
  • plasma such as Ar gas or N 2 gas
  • the buffer layer 102 can be formed over the entire surface of the substrate 101 in the subsequent steps, and a film made of a group III nitride semiconductor formed thereon It becomes possible to increase the crystallinity. Further, it is more preferable that the substrate 101 is subjected to a wet pretreatment before the pretreatment by reverse sputtering as described above.
  • the pretreatment for the substrate 101 plasma is performed in an atmosphere in which ion components such as N + and (N 2 ) + and radical components having no charge such as N radicals and N 2 radicals are mixed. It is preferable to carry out by processing.
  • the pretreatment on the substrate 101 is a method using plasma treatment performed in an atmosphere in which an ionic component and a radical component are mixed as described above.
  • Deposition of buffer layer After performing the pretreatment to the substrate 101 on the substrate 101 by a reactive sputtering method, forming an Al X Ga 1-X N ( 0 ⁇ X ⁇ 1) buffer layer 102 of the composition it is.
  • the ratio of the flow rate of the nitrogen source to the total flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is in the range of 50 to 100%. It is preferable to control so that it is about 75%.
  • the ratio of the flow rate of the nitrogen source to the total flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is 1 to 50%. It is preferable to control to be within the range, and more preferably about 25%.
  • the buffer layer 102 is not limited to the reactive sputtering method described above, and can be formed using, for example, the MOCVD method. However, since the convex portion 12 is formed on the main surface 10 of the substrate 101, the flow of the source gas may be disturbed on the main surface 10 when the buffer layer is formed by the MOCVD method. In contrast to the MOCVD method, the reactive sputtering method has a high degree of straightness of the raw material particles, so that the uniform buffer layer 102 can be stacked without being affected by the shape of the main surface 10. Therefore, the buffer layer 102 is preferably formed using a reactive sputtering method.
  • the buffer layer forming step As shown in FIGS. 1 and 3, a single crystal group III nitride semiconductor is epitaxially grown on the buffer layer 102 formed on the main surface 10 of the substrate 101. An epitaxial process is performed to form a base layer (group III nitride semiconductor layer) 103 so as to cover 10.
  • the LED stacking process includes the n-type semiconductor layer 104, the light emitting layer 105, and the p-type semiconductor layer 106 on the base layer 103.
  • An LED structure 20 is formed.
  • the description of the configuration common to both processes may be partially omitted for the epitaxial process and the LED stacking process in which each layer is formed using a group III nitride semiconductor.
  • the growth method of the gallium nitride compound semiconductor (group III nitride semiconductor) when forming the base layer 103, the n-type semiconductor layer 104, the light emitting layer 105, and the p-type semiconductor layer 106 is not particularly limited. All methods known to grow nitride semiconductors such as reactive sputtering, MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy), etc. Applicable.
  • the MOCVD method for example, hydrogen (H 2 ) or nitrogen (N 2 ) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source as a group III source, and as an Al source Trimethylaluminum (TMA) or triethylaluminum (TEA), trimethylindium (TMI) or triethylindium (TEI) as the In source, ammonia (NH 3 ), hydrazine (N 2 H 4 ), etc. as the N source that is a group V source Can be used.
  • monosilane (SiH 4 ) or disilane (Si 2 H 6 ) can be used as a Si raw material for the n-type, and germane gas (GeH 4 ) or tetramethyl germanium ((CH 3 ) as a Ge raw material.
  • germane gas GeH 4
  • tetramethyl germanium (CH 3 )
  • Organic germanium compounds such as 4 Ge) and tetraethyl germanium ((C 2 H 5 ) 4 Ge) can be used.
  • elemental germanium can also be used as a doping source.
  • the p-type for example, biscyclopentadienyl magnesium (Cp 2 Mg) or bisethylcyclopentadienyl magnesium (EtCp 2 Mg) can be used as the Mg raw material.
  • the gallium nitride compound semiconductor as described above can contain other group III elements in addition to Al, Ga, and In, and can contain Ge, Si, Mg, Ca, Zn, and Be as necessary.
  • a dopant element can be contained.
  • it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.
  • the MOCVD method is preferably used from the viewpoint of obtaining a film having good crystallinity.
  • an example using the MOCVD method in the epitaxial process and the LED stacking process will be described. To do.
  • a base layer 103 is formed on a buffer layer 102 formed on a substrate 101 by using a conventionally known MOCVD method, and a planar portion 11 that forms the main surface 10 of the substrate 101. And it forms so that the convex part 12 may be covered.
  • the underlayer 103 is formed using the MOCVD method.
  • the method for stacking the base layer 103 is not particularly limited, and any crystal growth method that can cause dislocation looping can be used without any limitation.
  • the MOCVD method, the MBE method, the VPE method, and the like are preferable in that a film with favorable crystallinity can be formed because migration can occur.
  • the MOCVD method can be used more suitably in that a film having particularly good crystallinity can be obtained.
  • a single crystal group III nitride semiconductor layer is grown on the main surface of a sapphire substrate using MOCVD, a single crystal layer is epitaxially grown from the C surface, but a single crystal is formed on the main surface other than the C surface.
  • the layer does not grow epitaxially. That is, in the example described in this embodiment, when the base layer 103 made of a single crystal group III nitride semiconductor is epitaxially grown on the main surface 10 of the substrate 101 on which the buffer layer 102 is formed, it is non-parallel to the C plane.
  • a crystal does not grow from the surface 12c of the first layer, and a crystal oriented in the C-axis direction grows epitaxially only from the flat portion 11 made of the (0001) C plane.
  • the base layer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown so as to cover the convex portion 12 on the main surface 10, so that crystal defects such as dislocations do not occur in the crystal, so that the crystallinity is improved.
  • a properly controlled layer is used to control the base layer 103 formed on the main surface 10 of the substrate 101 so as to cover the convex portion 12 on the main surface 10, so that crystal defects such as dislocations do not occur in the crystal, so that the crystallinity is improved.
  • the substrate 101 on which the protrusions 12 are formed has a better flatness when the underlayer 103 is epitaxially grown on the main surface 10 by the MOCVD method than the substrate on which the protrusions 12 are not formed. It is difficult to stack.
  • the base layer 103 laminated on the main surface 10 of the substrate 101 on which the convex portions 12 are formed is liable to cause a tilt in the C-axis direction that deteriorates the crystallinity, a twist in the C-axis, or the like.
  • the base layer 103 is epitaxially grown by the MOCVD method on the main surface 10 of the substrate 101 on which the convex portions 12 are formed, the following growth conditions are used in order to obtain sufficient surface flatness and good crystallinity. It is desirable.
  • the growth pressure and the growth temperature are set as described below. Generally, when the growth pressure is lowered and the growth temperature is raised, lateral crystal growth is promoted. On the other hand, when the growth pressure is raised and the growth temperature is lowered, the facet growth mode ( ⁇ shape) is entered. Further, when the growth pressure at the initial stage of growth is increased, the half-value width (XRC-FWHM) of the X-ray rocking curve is decreased, and the crystallinity tends to be improved.
  • the base layer 103 is epitaxially grown by the MOCVD method on the main surface 10 of the substrate 101 on which the convex portions 12 are formed, it is preferable to change the growth pressure in two stages. That is, it is preferable to change the growth pressure until the film thickness of the underlayer 103 is about 2 ⁇ m or more (first half film formation) and after the underlayer 103 is laminated about 2 ⁇ m or more (second half film formation).
  • the growth pressure is preferably 40 kPa or more, and more preferably about 60 kPa.
  • the growth pressure When the growth pressure is set to 40 kPa or more, a facet growth mode ( ⁇ shape) is set, dislocations bend in the lateral direction, and do not penetrate the epitaxial surface. For this reason, it is presumed that by increasing the growth pressure, the dislocation is lowered and the crystallinity is improved. If the growth pressure is less than 40 kPa, the crystallinity is deteriorated and the half width (XRC-FWHM) of the X-ray rocking curve is increased, which is not preferable.
  • XRC-FWHM half width
  • the growth pressure is 40 kPa or more in the first half film formation, pits are likely to be generated on the surface of the epitaxially grown base layer 103, and sufficient surface flatness may not be obtained.
  • the growth temperature is preferably 1140 ° C. or less, and more preferably about 1120 ° C. By setting the growth temperature to 1140 ° C. or lower, the generation of pits can be sufficiently suppressed even when the growth pressure is 40 kPa or more, preferably about 60 kPa.
  • the growth pressure is preferably 40 kPa or less, more preferably about 20 kPa.
  • the base layer 103 can be formed by being doped with impurities as necessary, but undoped is preferable from the viewpoint of improving crystallinity. It is also possible to form the base layer 103 made of a group III nitride semiconductor by using a reactive sputtering method. When the sputtering method is used, the apparatus can have a simple configuration as compared with the MOCVD method, the MBE method, or the like.
  • the stacked structure shown in FIG. 1 is obtained.
  • the base layer 103 is grown on the main surface 10 so as to cover the planar portion 11 and the convex portion 12. Since the epitaxial process is provided, crystal defects such as dislocations are not easily generated in the crystal of the base layer 103, and the base layer 103 in which the crystallinity is well controlled within an appropriate range can be formed.
  • the crystal defect which arose here is the semiconductor layer which comprises LED structure. If the light-emitting element is formed by the crystal, the internal quantum efficiency may be reduced and the leakage current may be increased.
  • the convex portion 12 made of the surface 12c that is non-parallel to the C plane is formed on the substrate 101, so that the flat portion 11 made of the C plane and the convex portion 12 are formed.
  • the main surface 10 is formed.
  • the base layer 103 is epitaxially grown on the main surface 10 of the substrate 101, crystals grow only from the planar portion 11. Therefore, the underlayer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown on the main surface 10 so as to cover the convex portions 12, and crystal defects such as dislocations do not occur in the crystal.
  • the interface between the substrate 101 and the base layer 103 is uneven via the buffer layer 102, light confinement inside the light-emitting element is reduced due to irregular reflection of light. The extraction efficiency can be further improved.
  • (X-ray rocking curve half width) In the present invention, as described above, (10) of the base layer 103 in a state where the base layer 103 made of a group III nitride semiconductor is formed on the main surface 10 of the substrate 101 provided with the protrusions 12 by the epitaxial process. It is preferable that the X-ray rocking curve (XRC) half-width in the ⁇ 10) plane is 150 arcsec or more. If the X-ray rocking curve (XRC) half-value width in the (10-10) plane of the underlayer 103 is such a numerical value, the crystallinity of the underlayer 103 is well controlled within an appropriate range, and is formed thereon.
  • the LED structure 20 composed of the n-type semiconductor layer 104, the light-emitting layer 105, and the p-type semiconductor layer 106 on the base layer 103.
  • MOCVD method Metal Organic Chemical Vapor Deposition
  • n-type semiconductor layer 104 is formed by sequentially laminating an n-type contact layer 104a and an n-type clad layer 104b on the base layer 103 formed by the epitaxial process using a conventionally known MOCVD method.
  • MOCVD apparatus used for forming the base layer 103 and the light-emitting layer 105 described later may be used by appropriately changing various conditions. Is possible.
  • the n-type contact layer 104a and the n-type cladding layer 104b can be formed by a reactive sputtering method.
  • the light emitting layer 105 is formed on the n-type cladding layer 104b (n-type semiconductor layer 104) by a conventionally known MOCVD method.
  • the light emitting layer 105 formed in the present embodiment has a stacked structure starting with a GaN barrier layer and ending with the GaN barrier layer. That is, seven barrier layers 105a made of GaN and six well layers 105b made of non-doped Ga 0.8 In 0.2 N are alternately stacked.
  • the light emitting layer 105 can be formed using the same film forming apparatus (MOCVD apparatus) used for forming the n-type semiconductor layer 104 described above.
  • a light emitting element that emits green light with an emission wavelength in the range of 490 to 570 nm can be configured.
  • the concentration of In contained in the well layer 105b is high, the growth temperature of the well layer 105b needs to be about 700 to 800 ° C., for example.
  • the lowering is achieved by controlling the half width.
  • the p-type semiconductor layer 106 composed of the p-type cladding layer 106a and the p-type contact layer 106b is formed on the light-emitting layer 105, that is, on the barrier layer 105a that is the uppermost layer of the light-emitting layer 105 by a conventionally known MOCVD method.
  • MOCVD method a conventionally known MOCVD method.
  • the same apparatus as the MOCVD apparatus used for forming the n-type semiconductor layer 104 and the light-emitting layer 105 can be used by appropriately changing various conditions.
  • the p-type cladding layer 106a and the p-type contact layer 106b constituting the p-type semiconductor layer 106 can be formed using a reactive sputtering method.
  • a p-type cladding layer 106a made of Al 0.1 Ga 0.9 N doped with Mg is formed on the light emitting layer 105 (the uppermost barrier layer 105a), and further, Mg A p-type contact layer 106b made of Al 0.02 Ga 0.98 N doped with is formed.
  • the same MOCVD apparatus can be used for stacking the p-type cladding layer 106a and the p-type contact layer 106b.
  • not only Mg but also zinc (Zn), for example, can be used as the p-type impurity.
  • electrodes are installed on the wafer on which the LED structure 20 is formed in the LED stacking step. Specifically, after forming a translucent positive electrode 109 at a predetermined position on the p-type semiconductor layer 106, a positive electrode bonding pad 107 is formed on each of the translucent positive electrodes 109. Also, the n-type semiconductor layer 104 is exposed by etching away a predetermined position of the LED structure 20 to form an exposed region 104c, and a negative electrode bonding pad 108 is formed in the exposed region 104c.
  • the translucent positive electrode 109 made of ITO is formed on the p-type contact layer 106b of the laminated semiconductor 10 in which each layer is formed by the above method.
  • a method for forming the translucent positive electrode 109 is not particularly limited, and the translucent positive electrode 109 can be provided by a common means well known in this technical field. Further, any structure including a conventionally known structure can be used without any limitation.
  • the material of the translucent positive electrode 109 is not limited to ITO, and can be formed using materials such as AZO, IZO, and GZO. Further, after forming the translucent positive electrode 109, thermal annealing may be performed for the purpose of alloying or transparency, but it may not be performed.
  • a positive electrode bonding pad 107 is further formed on the translucent positive electrode 109 formed on the laminated semiconductor 10.
  • the positive electrode bonding pad 107 can be formed, for example, by laminating Ti, Al, and Au materials in order from the surface side of the translucent positive electrode 109 by a conventionally known method.
  • the negative electrode bonding pad 108 when forming the negative electrode bonding pad 108, first, a part of the p-type semiconductor layer 106, the light emitting layer 105, and the n-type semiconductor layer 104 formed on the substrate 101 is removed by a method such as dry etching. The exposed region 104c of the n-type contact layer 104a is formed. Then, on this exposed region 104c, for example, each material of Ni, Al, Ti, and Au is sequentially laminated from the surface side of the exposed region 104c by a conventionally known method, thereby omitting detailed illustration.
  • the negative electrode bonding pad 108 can be formed.
  • the base width is 0.05 to 1.5 ⁇ m on the planar portion 11 made of the (0001) C plane of the substrate 101.
  • a substrate processing step of forming a plurality of convex portions 12 to form main surface 10 composed of flat portion 11 and convex portions 12 on substrate 101, and a group III nitride on main surface 10 of substrate 101 By epitaxially growing a semiconductor, an epitaxial process for forming a base layer so as to cover the planar portion 11 and the convex portion 12 and an LED structure 20 having the emission wavelength in the range of 490 to 570 nm are formed. LED lamination process.
  • the method for manufacturing a group III nitride semiconductor light emitting device it is possible to form the underlayer 103 with properly controlled crystallinity, and the LED structure 20 formed on this layer, particularly light emission.
  • the occurrence of lattice mismatch with the well layer 105b provided in the layer 105 is suppressed, and the well layer 105b (light-emitting layer 105) can be formed without causing distortion or the like.
  • the LED structure 20 exhibiting green light emission is formed, a group III nitride semiconductor light emitting device having excellent internal quantum efficiency and light extraction efficiency and having high light emission characteristics can be manufactured.
  • the group III nitride semiconductor light-emitting device of the present invention is used for the lamp of the present invention.
  • Examples of the lamp of the present invention include a combination of the group III nitride semiconductor light emitting device of the present invention and a phosphor.
  • a lamp in which a group III nitride semiconductor light emitting device and a phosphor are combined may be manufactured by means well known to those skilled in the art and may have a structure well known to those skilled in the art.
  • Conventionally, a technique for changing the emission color by combining a group III nitride semiconductor light-emitting element and a phosphor is known, and such a technique should be adopted in the lamp of the present invention without any limitation. Is possible.
  • FIG. 5 is a schematic view schematically showing an example of a lamp configured using the group III nitride semiconductor light emitting device according to the present invention.
  • the lamp 3 shown in FIG. 5 is a cannonball type, and the group III nitride semiconductor light emitting device 1 shown in FIG. 3 is used.
  • the group III nitride semiconductor light emitting device 1 is mounted. That is, the positive electrode bonding pad 107 of the group III nitride semiconductor light emitting device 1 is bonded to one of the two frames 31 and 32 (the frame 31 in FIG. 5) by the wire 33, and the negative electrode bonding pad of the light emitting device 1. 108 is bonded to the other frame 32 by a wire 34. Further, the periphery of the group III nitride semiconductor light emitting device 1 is sealed with a mold 35 made of a transparent resin.
  • the lamp of the present invention has excellent light emission characteristics.
  • the lamp of the present invention is not limited in shape and use, and can be used for any use such as a general-use bullet type, a side view type for a portable backlight, and a top view type used for a display.
  • Examples 1 and 2 A sapphire substrate having a plurality of (0001) C faces is prepared. On the (0001) C face of the sapphire substrate, “base width”, “height”, “base width / 4”, “ By forming a plurality of convex portions that satisfy the conditions of “interval between adjacent convex portions” and “presence / absence of convex surface C”, the substrates of Examples 1 and 2 and Comparative Example 1 are formed. Formed (substrate processing step). The convex portions were formed by forming a mask on a C-plane sapphire substrate having a diameter of 2 inches by a known photolithography method and etching the sapphire substrate by a dry etching method. As an exposure method, a stepper exposure method using ultraviolet light was used. In addition, a mixed gas of BCl 3 and Cl 2 was used for dry etching.
  • the convex portions of the substrates of Examples 1 and 2 and Comparative Example 1 obtained in this way have a shape in which the planar shape of the base of the convex portion is circular and the outer shape (cross-sectional area) gradually decreases toward the top. Yes, it had a bowl-like (hemispherical) shape with side surfaces curved outward.
  • a sapphire substrate having a principal surface made of a (0001) C surface without a convex portion without carrying out the substrate processing step as described above was prepared and used as a substrate of Comparative Example 2.
  • the thickness made of AlN having a single crystal structure using RF sputtering is used.
  • a 50 nm buffer layer was formed (buffer layer forming step).
  • the sputtering film forming apparatus an apparatus having a high-frequency power source and having a mechanism capable of moving the position of the magnet in the target was used.
  • a 50 nm thick buffer layer made of AlN having a single crystal structure was also formed on the main surface of the substrate of Comparative Example 2 having no protrusions using the same procedure described below.
  • a substrate having a plurality of convex portions was introduced into a chamber of a sputter deposition apparatus and heated to 500 ° C., and only nitrogen gas was introduced into the chamber at a flow rate of 15 sccm. Thereafter, the pressure in the chamber was maintained at 1 Pa, a high frequency bias of 500 W was applied to the substrate side, and the substrate was exposed to nitrogen plasma, thereby cleaning the surface of the substrate (pretreatment).
  • argon and nitrogen gas were introduced into the chamber, the pressure in the chamber was maintained at 0.5 Pa, and Ar gas was circulated at 5 sccm and nitrogen gas was circulated at 15 sccm. Under the conditions (the ratio of nitrogen to the whole gas is 75%), a high frequency bias of 2000 W is applied to the metal Al target side to start the formation of a buffer layer made of AlN on the substrate on which a plurality of convex portions are formed. It was. The growth rate was 0.08 nm / s. Note that the magnet in the target was swung both when the substrate was cleaned and when the buffer layer was formed.
  • film formation is performed for a prescribed time according to a film formation rate measured in advance, and after the buffer layer made of a 50 nm AlN layer is deposited on the substrate on which the plurality of convex portions are formed, the plasma is stopped from being generated. The substrate temperature was lowered.
  • an underlying layer made of a group III nitride semiconductor was epitaxially grown on the buffer layer thus obtained by using the low pressure MOCVD method described below (epitaxial process).
  • the substrate on which the buffer layer was formed was taken out from the sputter deposition apparatus. This substrate is introduced into a stainless steel vapor phase growth reactor used for the growth of a group III nitride semiconductor layer by MOCVD, and heated to a film formation temperature by a high frequency (RF) induction heating heater. The substrate was placed on a susceptor made of high-purity graphite for semiconductor in a reaction furnace. Thereafter, nitrogen gas was circulated in the reaction furnace to purge the reaction furnace.
  • RF high frequency
  • nitrogen gas was distribute
  • the induction heater was activated to raise the temperature of the sapphire substrate from room temperature to 500 ° C. in about 10 minutes.
  • the temperature of the substrate was kept at 500 ° C., and NH 3 gas and nitrogen gas were circulated in the reaction furnace.
  • the pressure in the vapor growth reactor was 95 kPa.
  • the temperature of the substrate was raised to 1000 ° C. over about 10 minutes, and the substrate surface was left under this temperature and pressure for 10 minutes to thermally clean the surface of the substrate. Even after the thermal cleaning was completed, the supply of nitrogen gas into the vapor phase growth reactor was continued.
  • the temperature of the substrate was raised to 1120 ° C. in a hydrogen atmosphere while continuing the flow of NH 3 gas, and the pressure in the reactor was 60 kPa. Then, after confirming that the temperature of the substrate was stabilized at 1120 ° C., supply of trimethylgallium (TMG) into the vapor phase growth reactor was started, and an undoped GaN layer having a thickness of 3 ⁇ m was formed on the AlN buffer layer. Until epitaxial growth. At this time, the amount of ammonia was adjusted so that the V group (N) / III group (Ga) ratio was 600. Then, after the growth of a base layer made of 3 ⁇ m of GaN (Group III nitride semiconductor), the supply of the raw material to the reaction furnace was stopped, and the temperature of the substrate was lowered.
  • TMG trimethylgallium
  • the substrate on which the buffer layer and the underlayer were formed was taken out from the reaction furnace, and the X-ray rocking curve (XRC) half widths of the (10-10) plane and the (0002) plane of the underlayer were measured. Indicated.
  • the X-ray rocking curve (XRC) on the (0002) plane represents the flatness of the crystal.
  • the sample of Comparative Example 1 in which the base layer was formed via the buffer layer on the main surface of the substrate having the base width of the protrusions of 2 nm is the XRC half of the (10-10) plane. It can be seen that the value width is 121 arcsec, the XRC half-value width of the (0002) plane is 38 arcsec, and the crystallinity of the underlayer is greatly enhanced. Further, in the sample of Comparative Example 2 in which the base layer is formed on the main surface of the substrate on which the convex portion is not formed via the buffer layer, the XRC half-value width of the (10-10) plane is 220 arcsec and the (0002) plane. The XRC half-value width is 36 arcsec, indicating that the crystallinity of the underlayer is inferior.
  • Example 1 in which the base layer was formed on the main surface of the substrate with the base width of the convex portion being 1 ⁇ m so as to cover the convex portion through the buffer layer is the (10-10) plane
  • the XRC half width was 171 arcsec
  • the XRC half width of the (0002) plane was 40 arcsec.
  • the sample of Example 1 has a smaller XRC half-value width, that is, improved crystallinity, as compared with Comparative Example 2 in which the base layer is formed on the substrate on which no convex portion is formed.
  • the sample of Example 1 has a larger XRC half-value width, that is, lower crystallinity than Comparative Example 1 in which the base layer is formed on the substrate on which the base width is as large as 2 ⁇ m. It is apparent that the crystallinity of the underlayer is controlled by controlling the dimensions of the convex portions formed on the substrate.
  • an n-type semiconductor layer constituting an LED structure is formed on the base layer made of a group III nitride semiconductor produced by the same method as in Examples 1 and 2 and Comparative Examples 1 and 2 by the following method.
  • the light emitting layer and the p-type semiconductor layer were laminated in this order to produce a light emitting element as shown in FIG. 3 (see also FIG. 4).
  • a lamp (light emitting diode: LED) using the light emitting element as shown in FIG. 5 was manufactured using the light emitting element.
  • n-type contact layer 104a made of GaN was formed on the underlayer 103 by the same MOCVD apparatus. At this time, the n-type contact layer 104a was doped with Si. Crystal growth was performed under the same conditions as the underlayer except that SiH 4 was circulated as a Si dopant material.
  • An n-type contact layer was formed by the process as described above. That is, an AlN buffer layer 102 having a single crystal structure is formed on a substrate 101 made of sapphire whose surface is reverse-sputtered, and an undoped GaN layer (underlayer 103) having a thickness of 8 ⁇ m is formed thereon. A 2 ⁇ m Si-doped GaN layer (n-type contact layer 104a) having a carrier concentration of 5 ⁇ 10 18 cm ⁇ 3 was formed. The substrate taken out from the apparatus after film formation was colorless and transparent, and the surface of the GaN layer (here, the initial layer forming the n-type contact layer 104a) was a mirror surface.
  • n-type cladding layer 104b was stacked on the n-type contact layer 104a produced by the above procedure by MOCVD.
  • the substrate on which the n-type contact layer 104a was grown by the above procedure was introduced into an MOCVD apparatus, and then the substrate temperature was lowered to 760 ° C. with nitrogen as the carrier gas while circulating the NH 3 gas. While waiting for the temperature change in the furnace, the NH 3 gas was continuously supplied into the furnace at the same flow rate. At this time, the supply amount of SiH 4 was set while waiting for the temperature change in the furnace. That is, the amount of SiH 4 to be distributed was calculated in advance, and the amount of SiH 4 was adjusted so that the electron concentration of the Si-doped layer was 4 ⁇ 10 18 cm ⁇ 3 .
  • a calculated amount of SiH 4 gas and TMI and TEG vapor generated by bubbling are circulated into the furnace, and a layer composed of Ga 0.99 In 0.01 N is formed.
  • a layer composed of Ga 0.99 In 0.01 N was formed with a thickness of 1.7 nm and a layer made of GaN with a thickness of 1.7 nm.
  • a layer made of Ga 0.99 In 0.01 N was grown at 1.7 nm.
  • the SiH 4 flow was continued during this process.
  • an n-type cladding layer 104b having a superlattice structure of Si-doped Ga 0.99 In 0.01 N and GaN was formed.
  • the light emitting layer 105 was laminated
  • the light emitting layer 105 has a multiple quantum well structure including a barrier layer 105a made of GaN and a well layer 105b made of Ga 0.85 In 0.15 N.
  • a barrier layer 105a is first formed on an n-type cladding layer 104c having a superlattice structure of Si-doped GaInN and GaN, and Ga 0.85 In is formed on the barrier layer 105a.
  • a well layer 105b made of 0.15 N was formed.
  • a seventh barrier layer 105a is formed on the sixth stacked well layer 105b, on both sides (upper and lower) of the light emitting layer 105 having a multiple quantum well structure.
  • the barrier layer 105a is provided.
  • the light emitting layer 105 was formed by the following method.
  • the barrier layer 105a of the light emitting layer 105 was formed as follows. With the substrate temperature kept at 760 ° C., supply of TEG and SiH 4 into the furnace was started, and an initial barrier layer made of GaN doped with Si for a predetermined time was formed to 0.8 nm, and then TEG and SiH 4 Supply was stopped. Thereafter, the temperature of the susceptor was raised to 920 ° C. Then, the supply of TEG and SiH 4 into the furnace was restarted, and the 1.7 nm intermediate barrier layer was grown while the substrate temperature remained at 920 ° C., and then the supply of TEG and SiH 4 into the furnace was stopped. did.
  • the susceptor temperature is lowered to 760 ° C.
  • the supply of TEG and SiH 4 is started
  • the final barrier layer of 3.5 nm is grown
  • the supply of TEG and SiH 4 is stopped again, and the GaN Finished the growth of the barrier layer.
  • an Si-doped GaN barrier layer (barrier layer 105a) having a total film thickness of 6 nm, which is composed of an initial barrier layer, an intermediate barrier layer, and a final barrier layer, is formed. did.
  • the amount of SiH 4 was adjusted so that the Si concentration was 1 ⁇ 10 17 cm ⁇ 3 .
  • the well layer 105b of the light emitting layer 105 was formed as follows. After the growth of the GaN barrier layer (barrier layer 105a) is completed, TEG and TMI are supplied into the furnace to form a well layer, and a Ga 0.85 In 0.15 N layer having a thickness of 3 nm is formed. (Well layer 105b) was formed on barrier layer 105a. During the deposition process of the well layer 105b, the In concentration of the well layer 105b was 8%, and the substrate temperature during growth was 750 ° C. Then, after the growth of the well layer 105b made of Ga 0.85 In 0.15 N, the setting of the TEGa supply amount was changed. Subsequently, the supply of TEGa and SiH 4 was restarted, and the second barrier layer 105a was formed.
  • barrier layers 105a made of Si-doped GaN and six layers of well layers 105b made of Ga 0.85 In 0.15 N are formed alternately. did.
  • a seventh barrier layer was formed.
  • the supply of SiH 4 was stopped, and an initial barrier layer made of undoped GaN was formed.
  • the substrate temperature is raised to 920 ° C. while the supply of the TEG into the furnace is continued, and the intermediate barrier layer is grown at the substrate temperature of 920 ° C. for a specified time.
  • the supply to was stopped.
  • the substrate temperature was lowered to 760 ° C., the supply of TEG was started, and the final barrier layer was grown. Thereafter, the supply of TEG was stopped again, and the growth of the GaN barrier layer was completed.
  • a seventh barrier layer made of undoped GaN having an initial barrier layer, an intermediate barrier layer, and a final barrier layer and having a total thickness of 4 nm was formed (in the light emitting layer 105 in FIG. 4).
  • top barrier layer 105a which uses the same reference number 105a but is not doped unlike the other barrier layers.
  • a well layer having a non-uniform thickness (the first to fifth well layers 105b from the n-type semiconductor layer 104 side in FIG. 4) and a well layer having a uniform thickness (the n-type in FIG. 4).
  • Formation of p-type semiconductor layer A superlattice composed of four layers of non-doped Al 0.06 Ga 0.94 N and three layers of Mg-doped GaN stacked alternately using the same MOCVD apparatus following the above-described steps. A p-type cladding layer 106 a having a structure was formed, and a p-type contact layer 106 b made of Mg-doped GaN having a thickness of 200 nm was formed thereon to form a p-type semiconductor layer 106.
  • the p-type semiconductor layer 106 was formed by the following method.
  • the p-type cladding layer 106a of the p-type semiconductor layer 106 was formed as follows. The substrate temperature was raised to 975 ° C. while supplying NH 3 gas, and then the carrier gas was switched from nitrogen to hydrogen at this temperature. Subsequently, the substrate temperature was changed to 1050 ° C. Then, by supplying TMG and TMA into the furnace, a 2.5 nm layer made of non-doped Al 0.06 Ga 0.94 N was formed. Subsequently, without taking an interval, the TMA valve was closed and the Cp 2 Mg valve was opened, and a Mg-doped GaN layer was deposited to 2.5 nm. The above operation was repeated three times, and finally a p-type cladding layer 106a having a superlattice structure was formed by forming an undoped Al 0.06 Ga 0.94 N layer.
  • the p-type contact layer 106b of the p-type semiconductor layer 106 was formed as follows. After forming the p-type cladding layer 106a, only Cp 2 Mg and TMG were supplied into the furnace to form a p-type contact layer 106b made of 200-nm p-type GaN. This p-type contact layer exhibited p-type characteristics even without annealing for activating p-type carriers.
  • the energization of the high-frequency induction heater used to heat the substrate is stopped immediately, and at the same time, the carrier gas is switched from hydrogen to nitrogen, and NH The flow rate of 3 gases was reduced. Specifically, during the growth, the amount of NH 3 gas that had been tightened by about 14% of the volume of the total circulation gas was reduced to 0.2%. Furthermore, after maintaining for 45 seconds in this state, the flow of NH 3 gas was stopped. In this state, it was confirmed that the substrate temperature was lowered to room temperature, and the substrate on which each layer was laminated was taken out into the atmosphere.
  • the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer constituting the LED structure are arranged in this order on the base layer manufactured in the same manner as in Examples 1-2 and Comparative Examples 1-2.
  • Samples (epitaxial wafers) of Examples 3 to 4 and Comparative Examples 3 to 4 formed in the above were produced.
  • the LED epitaxial wafer produced as described above has the following laminated structure. That is, after forming an AlN layer (buffer layer 102) having a single crystal structure on a substrate 101 made of sapphire having a c-plane, an 8 ⁇ m undoped GaN layer (underlayer 103), 5 ⁇ 10 18 cm -3 of 2 ⁇ m with electron concentration Si-doped GaNn type contact layer 104a, 4 has a Si concentration of ⁇ 10 18 cm -3, the 20 layers of 1.7nm Ga 0.99 in 0.01 N And 19 layers of a cladding layer (n-type cladding layer 104b) having a superlattice structure made of 1.7 nm of GaN.
  • a six-layer Si-doped GaN barrier layer (barrier layer 105a) that starts with the GaN barrier layer and ends with the GaN barrier layer and has a layer thickness of 6 nm, and a layer thickness of 3 nm 6 non-doped Ga 0.85 In 0.15 N well layers (well layers 105b) are alternately stacked, and the uppermost barrier layer made of non-doped GaN (the light emitting layer 105 in FIG.
  • a multi-quantum well structure (light-emitting layer 105) having a top barrier layer 105a in contact with the semiconductor layer 106 is stacked.
  • a p-type cladding layer 106a composed of three layers made of 0.01 Ga 0.99 N and having a superlattice structure, and a p-type contact layer 106b composed of Mg-doped GaN with a thickness of 200 nm.
  • a p-type semiconductor layer 106 is stacked.
  • a light-emitting diode which is a kind of semiconductor light-emitting element, was fabricated by the following procedure using the substrate on which each layer to be an LED structure obtained in this way was formed (see FIG. 3).
  • a light-transmitting positive electrode made of ITO is formed on a p-type contact layer of a substrate on which each layer to be an LED structure is formed by a known photolithography technique, and Ti, Al, and Au are sequentially formed on the light-transmitting positive electrode.
  • a positive electrode bonding pad having a laminated structure was formed.
  • dry etching was performed on the portion where the positive electrode bonding pad was not formed to expose the n-type semiconductor layer where the negative electrode bonding pad was formed.
  • a negative electrode bonding pad composed of four layers of Ni, Al, Ti, and Au was formed on the exposed n-type semiconductor layer.
  • substrate with which the positive electrode bonding pad and the negative electrode bonding pad were formed was ground and grind
  • the substrate was cut into 350 ⁇ m square chips to form LED chips. This chip was placed on the lead frame so that the positive electrode bonding pad and the negative electrode bonding pad were on top, and was connected to the lead frame with a gold wire to produce a lamp (see FIG. 5).
  • the forward voltage (driving voltage Vf) when a forward current of 20 mA was passed between the p-side electrode and the n-side electrode was measured, and the p-side transparency was measured.
  • the emission wavelength WD (nm) and the emission output Po (mW) were measured through the photocathode, and the results are shown in Table 2 below.
  • the samples of Examples 3 to 4 manufactured by the manufacturing method according to the present invention have a drive voltage Vf of 3.27 to 3.30 V, and an emission wavelength WD of 538 nm to 539 nm. While exhibiting good green light emission, the light emission output Po was 8.4 to 8.7 (mW).
  • the sample of Comparative Example 3 in which the base width of the convex portion of the substrate is 2 ⁇ m requires a driving voltage Vf of 3.37 V, which is higher than the samples of Examples 3 to 4, Further, the light emission output Po is 7.9 mW, which is lower than the samples of Examples 3 to 4. Further, in the sample of Comparative Example 4 having the conventional configuration in which the convex portion is not formed on the substrate, the driving voltage Vf is 3.35 V, and the light emission output Po is 7.7 mW. Luminous properties are inferior to the sample.
  • Example 1 In the same manner as in Examples 3 to 4, a 350 ⁇ m square Group III nitride semiconductor light emitting device chip was fabricated, and the lead frame was similarly placed so that the positive electrode bonding pad and the negative electrode bonding pad were on top. The sample was placed on top and connected to a lead frame with a gold wire to prepare a light emitting device sample. At this time, a sample in which the base width of the convex portion of the substrate was 1 ⁇ m was designated as Experimental Example 1, and a sample in which the base width of the convex portion was 2 ⁇ m was designated as Experimental Example 2, and five samples were produced. The emission intensity of each sample was measured while moving the detector in the direction perpendicular to the top surface of the chip, and the measurement results are shown in the graphs of FIGS. 6A and 6B.
  • the light-emitting element chip of Experimental Example 1 in which the interval between the protrusions formed on the substrate is 1 ⁇ m has an interval between the protrusions of 2 ⁇ m as shown in the graph of FIG. 6B. It can be seen that the light emission output is higher than that of the light emitting element chip of Experimental Example 2. From this result, it was found that the light emission output of the light emitting element can be improved when the interval between the convex portions formed on the substrate is smaller.
  • the group III nitride semiconductor light-emitting device of the present invention has excellent light extraction efficiency without reducing the internal quantum efficiency of the LED structure exhibiting green light emission, and high emission intensity. It is clear that
  • the present invention it is possible to provide a group III nitride semiconductor light-emitting device having excellent light extraction efficiency, a method for manufacturing the same, and a lamp without reducing the internal quantum efficiency of the LED structure that emits green light.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)

Abstract

L'invention porte sur un élément électroluminescent à semi-conducteur au nitrure du groupe III dans lequel une structure de diode électroluminescente (DEL) est formée sur une couche de semi-conducteur au nitrure du groupe III monocristallin formée sur un substrat. Le substrat comprend une surface principale, qui est composée d'une section de surface plate composée d'une surface (0001)C et d'une pluralité de sections saillantes, et une surface arrière, et la largeur d'une partie de base de la section saillante est de 0,05-1,5 µm. La couche de semi-conducteur au nitrure du groupe III est formée sur la surface principale du substrat par croissance épitaxiale d'un semi-conducteur au nitrure du groupe III afin de couvrir la section de surface plate et les sections saillantes. La longueur d'onde d'émission de la structure DEL est incluse dans l'intervalle de 490-570 nm.
PCT/JP2009/059357 2008-05-21 2009-05-21 Élément électroluminescent à semi-conducteur au nitrure du groupe iii et son procédé de fabrication, et lampe WO2009142265A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-133199 2008-05-21
JP2008133199A JP2009283620A (ja) 2008-05-21 2008-05-21 Ｉｉｉ族窒化物半導体発光素子及びその製造方法、並びにランプ

Publications (1)

Publication Number Publication Date
WO2009142265A1 true WO2009142265A1 (fr) 2009-11-26

Family

ID=41340192

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/059357 WO2009142265A1 (fr) 2008-05-21 2009-05-21 Élément électroluminescent à semi-conducteur au nitrure du groupe iii et son procédé de fabrication, et lampe

Country Status (2)

Country Link
JP (1) JP2009283620A (fr)
WO (1) WO2009142265A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013084832A (ja) * 2011-10-12 2013-05-09 Sharp Corp 窒化物半導体構造の製造方法
WO2015189088A1 (fr) * 2014-06-12 2015-12-17 Osram Opto Semiconductors Gmbh Puce semi-conductrice et procédé de fabrication d'une telle puce semi-conductrice

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4865047B2 (ja) * 2010-02-24 2012-02-01 株式会社東芝 結晶成長方法
JP5376462B2 (ja) * 2010-03-31 2013-12-25 国立大学法人山口大学 半導体発光素子及びその製造方法
JP2012028495A (ja) * 2010-07-22 2012-02-09 Showa Denko Kk 半導体発光素子の製造方法および半導体発光素子、ランプ、電子機器、機械装置
JP6024533B2 (ja) 2012-03-28 2016-11-16 日亜化学工業株式会社 サファイア基板及びその製造方法並びに窒化物半導体発光素子
JP2014038941A (ja) 2012-08-16 2014-02-27 Toyoda Gosei Co Ltd 半導体発光素子、発光装置
JP5880383B2 (ja) 2012-10-11 2016-03-09 豊田合成株式会社 半導体発光素子、発光装置
JP2018050063A (ja) * 2017-11-02 2018-03-29 ローム株式会社 半導体発光素子

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019318A (ja) * 2005-07-08 2007-01-25 Sumitomo Chemical Co Ltd 半導体発光素子、半導体発光素子用基板の製造方法及び半導体発光素子の製造方法
JP2007273659A (ja) * 2006-03-31 2007-10-18 Showa Denko Kk ＧａＮ系半導体発光素子およびランプ
JP2007329312A (ja) * 2006-06-08 2007-12-20 Showa Denko Kk Ｉｉｉ族窒化物半導体積層構造体の製造方法
JP2008091608A (ja) * 2006-10-02 2008-04-17 Sony Corp 発光ダイオードおよびその製造方法ならびに光源セルユニットならびに発光ダイオードバックライトならびに発光ダイオード照明装置ならびに発光ダイオードディスプレイならびに電子機器ならびに電子装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019318A (ja) * 2005-07-08 2007-01-25 Sumitomo Chemical Co Ltd 半導体発光素子、半導体発光素子用基板の製造方法及び半導体発光素子の製造方法
JP2007273659A (ja) * 2006-03-31 2007-10-18 Showa Denko Kk ＧａＮ系半導体発光素子およびランプ
JP2007329312A (ja) * 2006-06-08 2007-12-20 Showa Denko Kk Ｉｉｉ族窒化物半導体積層構造体の製造方法
JP2008091608A (ja) * 2006-10-02 2008-04-17 Sony Corp 発光ダイオードおよびその製造方法ならびに光源セルユニットならびに発光ダイオードバックライトならびに発光ダイオード照明装置ならびに発光ダイオードディスプレイならびに電子機器ならびに電子装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013084832A (ja) * 2011-10-12 2013-05-09 Sharp Corp 窒化物半導体構造の製造方法
WO2015189088A1 (fr) * 2014-06-12 2015-12-17 Osram Opto Semiconductors Gmbh Puce semi-conductrice et procédé de fabrication d'une telle puce semi-conductrice

Also Published As

Publication number Publication date
JP2009283620A (ja) 2009-12-03

Similar Documents

Publication Publication Date Title
JP4908381B2 (ja) Ｉｉｉ族窒化物半導体層の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ
WO2009154215A1 (fr) Élément électroluminescent à semi-conducteurs de nitrure de groupe iii, procédé de fabrication dudit élément et lampe
JP5521981B2 (ja) 半導体発光素子の製造方法
KR101067122B1 (ko) Ⅲ족 질화물 반도체의 제조 방법, ⅲ족 질화물 반도체 발광 소자의 제조 방법 및 ⅲ족 질화물 반도체 발광 소자, 및 램프
US8502254B2 (en) Group III nitride semiconductor light-emitting device and method of manufacturing the same, and lamp
WO2009142265A1 (fr) Élément électroluminescent à semi-conducteur au nitrure du groupe iii et son procédé de fabrication, et lampe
KR101268139B1 (ko) Ⅲ족 질화물 반도체 발광 소자의 제조 방법, ⅲ족 질화물 반도체 발광 소자 및 램프
WO2010032423A1 (fr) Procédé de fabrication d'un élément électroluminescent à semi-conducteurs de nitrure iii, élément électroluminescent à semi-conducteurs de nitrure iii et luminaire
KR101071450B1 (ko) Ⅲ족 질화물 반도체층의 제조 방법 및 ⅲ족 질화물 반도체 발광 소자, 및 램프
WO2009139376A1 (fr) Procédé de production d’un élément électroluminescent semi-conducteur en nitrure de groupe iii, élément électroluminescent semi-conducteur en nitrure de groupe iii et lampe
JP6910341B2 (ja) 縦型紫外発光ダイオード
JP5504618B2 (ja) Ｉｉｉ族窒化物半導体発光素子及びその製造方法
CN101558502A (zh) Ⅲ族氮化物半导体层的制造方法以及ⅲ族氮化物半导体发光元件和灯
JP2005268581A (ja) 窒化ガリウム系化合物半導体発光素子
JP2008034444A (ja) Ｉｉｉ族窒化物半導体発光素子の製造方法、ｉｉｉ族窒化物半導体発光素子及びランプ
WO2010100900A1 (fr) Élément photoémetteur à semi-conducteurs aux nitrures d'éléments du groupe iii, procédé de fabrication correspondant, et lampe
JP2010010444A (ja) 半導体発光素子、ランプ及び半導体発光素子の製造方法
JP2011082248A (ja) 半導体発光素子及びその製造方法、並びにランプ
JP5648446B2 (ja) 半導体発光素子の製造方法
JP2011091442A (ja) 窒化ガリウム系化合物半導体発光ダイオード

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09750627

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09750627

Country of ref document: EP

Kind code of ref document: A1