WO2009134089A2 - 무 커패시터 메모리 소자 - Google Patents

무 커패시터 메모리 소자 Download PDF

Info

Publication number
WO2009134089A2
WO2009134089A2 PCT/KR2009/002284 KR2009002284W WO2009134089A2 WO 2009134089 A2 WO2009134089 A2 WO 2009134089A2 KR 2009002284 W KR2009002284 W KR 2009002284W WO 2009134089 A2 WO2009134089 A2 WO 2009134089A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate electrode
voltage
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2009/002284
Other languages
English (en)
French (fr)
Korean (ko)
Other versions
WO2009134089A3 (ko
Inventor
박재근
심태헌
이곤섭
김성제
김태현
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industry University Cooperation Foundation IUCF HYU
Industry University Cooperation Foundation of Sogang University
Original Assignee
Industry University Cooperation Foundation IUCF HYU
Industry University Cooperation Foundation of Sogang University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industry University Cooperation Foundation IUCF HYU, Industry University Cooperation Foundation of Sogang University filed Critical Industry University Cooperation Foundation IUCF HYU
Priority to JP2011507351A priority Critical patent/JP5496184B2/ja
Priority to US12/990,353 priority patent/US8860109B2/en
Priority to EP09738995.1A priority patent/EP2284879B1/en
Publication of WO2009134089A2 publication Critical patent/WO2009134089A2/ko
Publication of WO2009134089A3 publication Critical patent/WO2009134089A3/ko
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Definitions

  • the present invention relates to a capacitorless memory device, and more particularly to a memory device that may not form a separate capacitor for charge storage.
  • a memory device refers to a device that stores and stores certain information and can be taken out at a necessary time.
  • a memory device is a DRAM (Dynamic Random Access Memory) device.
  • DRAM integrates a plurality of unit cells composed of one transistor and one capacitor. That is, one bit of information is stored in the capacitor of the unit cell on the basis of charging or not.
  • the height of the capacitor must be increased. That is, for example, when the DRAM design rule is 60 nm, the height of the capacitor is about 1.6 mu m. If the DRAM design rule is reduced to 40nm, the height of the capacitor is increased to about 2.0 ⁇ m. As such, when the height of the capacitor is increased, a problem occurs that smooth patterning becomes difficult because the aspect ratio is large when forming a hole for manufacturing a capacitor having a cylinder structure. In addition, as the spacing between adjacent capacitors decreases, and the height of the capacitors increases, there is a problem that the adjacent capacitors are electrically connected due to the collapse of the capacitors. Therefore, when the DRAM design rule is reduced to 40 nm or less, it is difficult to apply a capacitor having a cylinder structure.
  • a capless memory device ie, a capacitorless memory device
  • a charge is charged to a silicon body of a transistor instead of a conventional capacitor.
  • the present invention provides a capacitorless memory device capable of improving information storage capability by increasing charge retention time by forming a storage layer that prevents leakage of charge in a part of a body in which charges (that is, holes or electrons) are to be accumulated. .
  • a semiconductor substrate In the capacitorless memory device according to the present invention, a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region formed in a portion of the insulating layer, a storage region and a balance band energy located on the storage region
  • the present invention provides a capacitorless memory device including a channel region having a difference, a gate insulating layer and a gate electrode sequentially formed on the channel region, and source and drain electrodes connected to the channel region and positioned at both sides of the gate electrode.
  • the capacitorless memory device for storing charge in a region under the gate electrode there is provided a semiconductor substrate, an insulating layer on the semiconductor substrate, a storage region formed on at least a portion of the insulating layer, and A channel region positioned on the storage region, a gate insulating layer and a gate electrode sequentially formed on at least the channel region, and source and drain electrodes connected to at least the channel region and positioned at both sides of the gate electrode;
  • a capacitorless memory device is provided in which regions and material components forming the channel regions are different from each other.
  • the storage region preferably has a balance band energy difference with the channel region.
  • the storage region may effectively store charges having a different polarity than the charges constituting the channel to be formed in the channel region.
  • a channel is formed in the storage area, and the channel area stores charges having a different polarity than the electric charges constituting the channel to be formed in the storage area.
  • the band gap of the storage area is smaller than the band gap of the channel area, and the electron affinity of the storage area is smaller than the electron affinity of the channel area.
  • the band gap of the storage area may be greater than the band gap of the channel area, and the electron affinity of the storage area may be greater than the electron affinity of the channel area.
  • the balance band energy of the storage region is preferably higher than the balance band energy of the channel region.
  • the balance band energy difference is 0.1 to 1 eV.
  • the source and drain electrodes may be formed by implanting impurity ions into at least the second layer on both sides of the gate electrode.
  • the said 1st layer contains Ge containing material
  • said 2nd layer contains Si containing material
  • the first layer comprises a SiGe based material
  • the second layer comprises a Si based material
  • any one of the first and second layers is a strained layer.
  • An electrode may be formed, and the storage region may be the first layer, and the channel region may be formed in the second layer located at least above the first layer.
  • the source and drain electrodes may be formed by implanting impurity ions into at least the second layer on both sides of the gate electrode.
  • the first layer contains a Ge-containing material
  • the second layer includes a Si-containing material
  • the first layer comprises a SiGe based material
  • the second layer comprises a Si based material
  • any one of the first and second layers is a strained layer.
  • a first layer formed in an island or bar shape on a portion of the insulating layer, and a second layer formed on sidewalls and an upper surface of the first layer, wherein the gate insulating layer surrounds the second layer,
  • a gate electrode is formed on the gate insulating film in the sidewall surface region of the second layer, the storage region is formed in the first layer overlapping the gate electrode, and the channel region overlaps the gate electrode. It can be formed in two layers.
  • the source and drain electrodes are preferably formed by implanting impurity ions into at least the second layer on both sides of the gate electrode.
  • the said 1st layer contains Ge containing material
  • said 2nd layer contains Si containing material
  • the first layer comprises a SiGe based material
  • the second layer comprises a Si based material
  • Either of the first layer and the second layer is effectively a strained layer.
  • a first layer formed in an island or bar shape on a portion of the insulating layer, and a second layer formed on sidewalls and an upper surface of the first layer, wherein the gate electrode surrounds at least a portion of the second layer;
  • the storage region may be formed in the first layer overlapping the gate electrode, and the channel region may be formed in the second layer overlapping the gate electrode.
  • the source and drain electrodes are preferably formed by implanting impurity ions into at least the second layer on both sides of the gate electrode.
  • the said 1st layer contains Ge containing material
  • said 2nd layer contains Si containing material
  • the first layer comprises a SiGe based material
  • the second layer comprises a Si based material
  • Either of the first layer and the second layer is effectively a strained layer.
  • the storage region preferably comprises a Ge containing material and the channel region comprises a Si containing material.
  • the storage region comprises a strained Ge containing layer and the channel region effectively comprises a Si containing layer.
  • the storage region comprises a relaxed Ge containing layer and the channel region comprises a strained Si containing layer.
  • the storage region may comprise a SiGe based material and the channel region may comprise a Si based material.
  • the storage region comprises a strained SiGe layer and the channel region comprises a Si layer.
  • the storage region may comprise a relaxed SiGe layer and the channel region may comprise a strained Si layer.
  • the Ge concentration of the SiGe-based material is preferably 10 to 95 at%.
  • interlayer insulating film formed on the entire structure including the gate electrode, and first and second wirings respectively connected to the source and drain electrodes through a portion of the interlayer insulating film.
  • a gate voltage and a bias voltage are applied to the gate electrode and the semiconductor substrate, respectively, and the polarities of the gate voltage and the bias voltage are effectively reversed.
  • a first bit is driven by applying a gate voltage having a different polarity from the bias voltage to the gate electrode, and a gate voltage and a back bias voltage having a different polarity than the first bit is applied to the gate electrode and the semiconductor substrate by a second bit drive. It is desirable to drive bits.
  • the magnitude of the absolute value of the back bias voltage is larger than the magnitude of the absolute value of the gate voltage.
  • a storage region having a different balance band energy from the channel region may be disposed under the channel region so that charges may be trapped in the storage region, thereby eliminating the capacitor used for conventional charge charging.
  • the present invention can improve the information storage capacity by increasing the retention time of the charge by increasing the balance band energy of the storage area portion than the channel region portion so that the charge trapped in the storage area portion can not easily escape.
  • the present invention can improve the reliability of the device by increasing the retention time of the charge.
  • the present invention can reduce the dependence of the back bias on the charge trap by the storage region.
  • the present invention can implement a multi-level cell by adjusting the voltage applied to the device, it is possible to implement a plurality of bits in a single cell.
  • FIG. 1 is a cross-sectional view of a capacitorless memory device according to an embodiment of the present invention.
  • FIGS. 2 to 4 are cross-sectional views of capacitorless memory devices according to first to third modified examples of the embodiment
  • FIG. 5 is a cross-sectional view of a capacitorless memory device according to another example of one embodiment.
  • FIG. 6 is a cross-sectional view of a capacitorless memory device according to another example of the second modification.
  • FIG. 7 is a conceptual diagram illustrating an operation of a capacitorless memory device according to an exemplary embodiment.
  • FIGS. 8 and 9 are conceptual cross-sectional views illustrating an operation of a capacitorless memory device according to example embodiments.
  • FIG. 10 is a graph illustrating a balance band energy difference between a channel layer and a storage layer and corresponding hole concentration according to an exemplary embodiment.
  • 11 is a graph showing a balance band energy difference according to Ge concentration in a storage layer of an embodiment.
  • 12 and 13 are graphs for describing memory margins according to example embodiments and modified examples.
  • 14 and 15 are graphs for describing hole retention times according to one embodiment and variations.
  • 16 is a graph showing memory margin and balance band energy difference according to Ge concentration in a storage layer according to a third modification.
  • 17 is a graph showing the charge retention time according to the Ge concentration in the storage layer according to the third modification.
  • FIG. 18 is a graph illustrating a drain voltage current change of a capacitorless memory device according to an exemplary embodiment.
  • FIG. 19 is a graph illustrating a drain voltage current change of a capacitorless memory device according to a comparative example.
  • semiconductor substrate 120 insulating layer
  • gate electrode portion 160 source electrode portion
  • 1 is a cross-sectional view of a capacitorless memory device according to an exemplary embodiment of the present invention.
  • 2 to 4 are cross-sectional views of the capacitorless memory device according to the first to third modified examples of the embodiment.
  • 5 is a cross-sectional view of a capacitorless memory device according to another example embodiment.
  • 6 is a cross-sectional view of a capacitorless memory device according to another example of the second modification.
  • a capacitorless memory device may include a semiconductor substrate 110, an insulating layer 120 disposed on an upper side thereof, and a first layer 130 sequentially stacked on the insulating layer 120.
  • the storage area T is located in the first layer 130
  • the channel area C is located in the second layer 140.
  • First and second wiring parts 190 and 200 directly connected to the electrode parts 160 and 170 are further provided.
  • the first wiring part 190 is connected to the source electrode part 160 through the first contact plug 191
  • the second wiring part 200 is connected to the drain electrode part 170 through the second contact plug 201. Is connected to.
  • the first and second contact plugs 191 and 201 may remove a portion of the interlayer insulating layer 180 to expose a portion of the source and drain electrode portions 160 and 170 under the contact hole, and the inside of the contact hole. It includes a conductive material filled in.
  • the capacitorless memory device of the present exemplary embodiment may directly connect the wiring part and the source and drain electrode parts 160 and 170 without using a capacitor.
  • a single element semiconductor substrate or a compound semiconductor substrate may be used as the semiconductor substrate 110.
  • the semiconductor substrate 110 may be doped with a predetermined impurity.
  • the insulating layer 120 It is possible to use a silicon oxide film layer or a silicon nitride film layer as the insulating layer 120.
  • a silicon oxide film is used as the insulating layer.
  • the silicon oxide film may be manufactured by oxidizing a part of the semiconductor substrate 110.
  • the present invention is not limited thereto, and the insulating layer 120 may be manufactured by ion implantation.
  • the gate electrode unit 150 may be formed on the gate insulating layer 151 formed in the upper partial region of the second layer 140, the gate electrode 152 formed on the gate insulating layer 151, and at least on the side of the gate electrode 152.
  • a spacer 153 is provided.
  • the gate insulating layer 151 may be manufactured in a single layer or multiple layers.
  • a silicon oxide film is used as the gate insulating film 151.
  • the present invention is not limited thereto, and an insulating film having a low dielectric constant may be used as the gate insulating film 151.
  • the gate electrode 152 may be manufactured in a single layer or multiple layers, and although not shown in the present embodiment, a polysilicon layer doped with impurities (for example, N type or P type) with the gate electrode 152 and formed thereon It may also include a metal layer. If necessary, a part of the gate electrode 152 may protrude into the second layer 140. As described above, the gate electrode unit 150 controls a channel formed in the second layer 140 according to a voltage applied through a word line (or a gate line; not shown). Accordingly, the shape of the gate electrode unit 150 is not limited to the above description, and various shapes for the channel control are possible.
  • the source and drain electrode parts 160 and 170 are formed by implanting impurity ions into the first layer 130 and the second layer 140 on both sides of the gate electrode part 150.
  • impurity ions can be used as impurity ions.
  • the source and drain electrode portions 160 and 170 are formed by implanting N-type impurities.
  • lightly doped drain (LDD) ion implantation may be performed.
  • LDD lightly doped drain
  • the present invention is not limited thereto, and regions corresponding to the source electrode 160 and the drain electrode 170 on both sides of the gate electrode 150 are not formed in the first layer 130 and the second layer 140. Instead, separate junction layers (not shown) may be formed to form the source and drain electrode portions 160 and 170.
  • the source and drain electrode portions 160 and 170 move electrons along the channel formed in the second layer 140 according to the applied voltage. Accordingly, the shape of the source and drain electrode portions 160 and 170 is not limited to the above description, and various shapes for moving electrons to the channel are possible.
  • the second layer 140 of the present embodiment is a layer that prevents the movement of charges (holes in this embodiment) stored in the storage region T by using a balance band energy difference with the first layer 130 formed below. It is the layer which acts and in which part the channel is formed.
  • the second layer 140 positioned in the region between the gate electrode unit 150 and the source and drain electrodes 160 and 170 among the second layers 140 serves as the channel region C.
  • the first layer 130 is a layer that functions as a space for storing electric charges by using a balance band energy difference with the second layer 140 formed thereon.
  • the first layer 130 positioned in the region between the lower part of the second layer 140 below the gate electrode part 150 and the source and drain electrode parts 160 and 170 stores charge. Acts as a storage area (T).
  • T storage area
  • the lower side of the channel region C serves as the storage region T.
  • an energy barrier is formed by the balance band energy difference between the first layer 130 and the second layer 140.
  • the charges inside the first layer 130 are not easily leaked or destroyed by the energy barrier. This means that the retention time of the charge in the first layer 130 can be increased.
  • the balance band energy of the first layer 130 is higher (that is, larger) than the balance band energy of the second layer 140.
  • the balance band energy difference between the second layer 140 and the first layer 130 preferably has a range of 0.1 to 1 eV.
  • the energy difference is less than 0.1 eV, the energy barrier between the two layers is lowered, which does not effectively prevent the leakage of charge. Therefore, it is effective that the energy difference is larger than 0.1 eV.
  • the energy difference is 1 eV or more, a problem arises in that the voltage required for charging the charge increases because the energy barrier is too large.
  • Si when Si is used as the second layer 140 and Ge is used as the first layer 130 as follows.
  • Si has an energy band gap of 1.1 eV, an electron affinity of 4.05 eV
  • Ge has an energy band gap of 0.65 eV, and an electron affinity of 3.9 eV (vacuum level reference).
  • the balance band energy offset between the two materials is about 0.374 eV due to the difference in energy band gap and electron affinity between the two materials. This balance band energy difference creates a well barrier between the two materials, and charges are confined by the well barrier.
  • SiGe has a smaller bandgap and electron affinity than Si, and has excellent bonding interface properties with Si. Accordingly, the SiGe layer has excellent characteristics as the first layer 130. In addition, SiGe can easily control the desired properties according to the content of Ge.
  • the electrons move in the channel of the second layer 140 and the hole is used as the charge accumulated in the first layer 130.
  • the present invention is not limited thereto, and holes may be moved in the channel of the second layer 140, and electrons may be used as charges accumulated in the first layer 130.
  • the energy band gap and electron affinity described above may be opposite to each other. That is, the energy band gap and electron affinity of the second layer 140 may be smaller than the energy band gap and electron affinity of the first layer 130 (vacuum level reference).
  • a silicon (Si) layer is used as the second layer 140 and a silicon germanium (SiGe) layer is used as the first layer 130.
  • SiGe silicon germanium
  • a first Si substrate is prepared, and a strain SiGe layer is formed on the first Si substrate, for example, epitaxially.
  • the 2nd Si substrate in which the oxide film was formed in the surface is provided.
  • the SiGe layer of a 1st Si substrate and the oxide film of a 2nd Si substrate are bonded.
  • a portion of the first Si substrate on the SiGe layer is then cleaved.
  • a modified SOI-type material in which an insulating layer, a strain SiGe layer, and a Si layer are sequentially stacked on a semiconductor substrate may be manufactured.
  • the device having the first layer 130 that stores charge therein by using the balance band energy difference with the second layer 140 is not limited to the above-described configuration, and various modifications are possible.
  • the capacitorless memory device includes a first layer 130 formed in an island or line shape on a portion of the insulating layer 120 and an upper side of the first layer 130.
  • a second layer 140 formed on the source layer, source and drain electrode portions 160 and 170 formed on side surfaces of the first layer 130 and the second layer 140, and an upper portion of the second layer 140.
  • the gate electrode part 150 is included.
  • all of the first layer 130 may be the storage region T, and the channel region C may be formed in the second layer 140. It may be formed between the drain electrode portions 160 and 170.
  • the second layer 140 and the source and drain electrode portions 160 and 170 are the same material layer
  • the first layer 130 is the second layer 140 and the source and drain electrode portions 160 and 170. It is effective to be a material layer having a higher balance band energy than 170). This allows the hole to be confined inside the first layer 130.
  • a Si layer is used as the second layer 140 and a strained SiGe layer is used as the first layer 130. Therefore, at least three surfaces of the first layer 130 may be surrounded by the Si layer to further enhance the retention property of the hole.
  • a material in which the insulating layer 120, the strained SiGe layer, and the Si layer are sequentially stacked on the semiconductor substrate 110 is manufactured as in the previous embodiment. Subsequently, all of the Si layer and the SiGe layer of the remaining region except for the region where the gate electrode unit 150 is to be formed are removed by an etching process using a mask. As a result, the SiGe layer and the Si layer remain on the insulating layer 120 in the region where the gate electrode unit 150 is to be formed. At this time, the Si layer on the SiGe layer can be removed as needed.
  • the insulating layer 120 and the strained SiGe layer may be stacked on the semiconductor substrate 110, and then the strained SiGe layer may be removed except for the region where the gate electrode unit 150 is to be formed by an etching process.
  • a Si layer is grown on the insulating layer 120 on which the strained SiGe layer is patterned. This allows the Si layer to be fabricated to cover the strained SiGe layer.
  • a gate electrode part 150 is formed on the strained SiGe layer.
  • the source and drain electrode parts 160 and 170 are manufactured by implanting impurity ions into the Si layers on both sides of the gate electrode part 150.
  • the present invention is not limited thereto, and the semiconductor substrate 110 in which the insulating layer 120 and the Si layer are stacked is prepared. Subsequently, the Si layer of the region where the gate electrode part 150 is to be formed is removed. Subsequently, a SiGe layer is formed on the insulating layer 120 in the region where the Si layer is removed, and then a Si layer is formed on the SiGe layer. In this case, selective deposition may be performed using a separate seed layer to form a SiGe layer on the insulating layer 120, and a selective deposition may be performed on only a corresponding region by applying a mask to the Si layer of the remaining region. Subsequently, the gate electrode part 150 is formed on the Si layer on the strained SiGe layer, and the source and drain electrode parts 160 and 170 are manufactured by implanting impurity ions into the Si layers on both sides of the gate electrode part 150. .
  • the strained (strained) SiGe layer can be a compressively strained SiGe layer.
  • a strained SiGe layer as the first layer 130 and a strained Si layer as the second layer 140 as in the second variant of FIG. 3.
  • a first Si substrate having a gradient SiGe layer and a buffer SiGe layer is prepared.
  • the 2nd Si substrate in which the insulating layer was formed in the surface is provided.
  • the buffer SiGe layer of the first Si substrate and the insulating layer of the second Si substrate are bonded to each other, and the first Si substrate and the second Si substrate are separated by wall based on a part of the buffer SiGe layer.
  • the insulating layer 120 and the buffer SiGe layer ie, the first layer 130
  • a strained Si layer is then formed on the buffer SiGe layer, for example epitaxially.
  • the gate electrode part 150 is formed on the strained Si layer, and impurities are implanted into the strained Si layer and the buffer SiGe layer on both sides of the gate electrode part 150 to form the source and drain electrode parts 160 and 170.
  • the channel region C may be formed in the region between the source and drain electrode portions 160 and 170 of the second layer 140, and the storage region T may be a first layer below the channel region C. And may be formed within 130.
  • the present invention is not limited thereto, and the semiconductor substrate 110 having the insulating layer 120 and the upper Si layer is provided.
  • a strained SiGe layer is formed on the upper Si layer.
  • the strained SiGe layer is changed into a relaxed SiGe layer through an oxidation process, and the upper Si layer is oxidized to form the insulating layer 120.
  • the oxide film formed on the SiGe layer is removed.
  • a strained Si layer may be formed on the exposed SiGe layer.
  • the first layer 130 is manufactured in an island or line shape, and a second layer 140 is formed on the first layer 130.
  • the SiGe layer is used as the first layer 130, and at least the second layer 140 on the upper side of the first layer 130 is manufactured as the strained Si layer.
  • fabrication techniques as described in the foregoing second and third modifications can be introduced.
  • the use of a strained Si layer increases the mobility of electrons in the second layer 140, thereby further increasing memory margin and charge retention time.
  • the strained (strained) Si layer may be a tensile strained Si layer.
  • the present invention is not limited to the above-described embodiment and the second modified example, and the source and drain electrode portions 160 and 170 may be formed in the second layer 140. That is, referring to another example of the embodiment illustrated in FIG. 5, ion implantation is performed only in the region of the second layer 140 on both sides of the gate electrode unit 150, so that the source and drain electrode units 160 and 170 are connected to the second layer 140. It was formed in the area. In addition, referring to another example of the second modified example of FIG. 6, source and drain electrode portions 160 and 170 may be formed in the second layers 140 on both sides of the gate electrode 150. Through this, leakage of charges by the source and drain electrode units 160 and 170 may be prevented.
  • the Si and SiGe are used as the second layer 140 and the first layer 130.
  • the second layer 140 may be formed of a Si-based material
  • the first layer 130 may be formed of a Ge-based material.
  • the present invention is not limited thereto, and various materials having a difference in electron affinity, energy band gap, and balance band gap difference may be selected as described above.
  • FIG. 7 is a conceptual diagram illustrating an operation of a capacitorless memory device according to an embodiment.
  • 8 and 9 are conceptual cross-sectional views for describing an operation of a capacitorless memory device according to example embodiments.
  • FIG. 8A is a conceptual sectional view for explaining a write operation
  • FIG. 8B is a conceptual sectional view for explaining a read operation of an element to which data of " 1 " is written
  • FIG. ) Is a conceptual cross-sectional view for explaining the erase operation
  • FIG. 9B is a conceptual cross-sectional view for explaining a read operation of an element to which " 0 " data (i.e., erase data) is written.
  • the voltage current in the unit cell of a typical memory device converges as the current increases constantly as the voltage increases, as illustrated by the N1 graph shown in FIG. 7.
  • the capacitorless memory device described in the present embodiment when the voltage increases as shown by the N2 graph of FIG. 7 due to the kink effect, a section in which the current increases again occurs. This is because charges (that is, holes) are accumulated in the first layer 130 under the channel region C. In the case where charge is accumulated in the first layer 130 as described above, even though the voltage is reduced as shown in the N3 graph of FIG. Therefore, the current flow changes depending on whether or not holes are accumulated in the first layer 130, and the information written in the device is determined using the current flow difference.
  • a write voltage equal to or greater than the voltage causing the kink effect is provided to the drain electrode unit 170 to write data corresponding to "1" to the device, and the drain electrode part to erase the data corresponding to "0" to the device.
  • a case where a voltage of 3 V is used as the write voltage, a voltage of ⁇ 1 V is used as the erase voltage, and 1.5 V is used as the read voltage is as follows. .
  • a voltage of 2V is applied to the gate electrode unit 150, a ground voltage GND is provided to the source electrode unit 160, and a drain electrode unit is used to perform a write operation.
  • 3V was applied to 170.
  • holes are stacked in the first layer 130 as shown in FIG.
  • holes accumulated in the first layer 130 are trapped in the first layer 130 by an energy difference between the first layer 130 and the second layer 140.
  • a voltage of 2 V is applied to the gate electrode unit 150, a ground voltage GND is provided to the source electrode unit 160, and a drain electrode is performed to perform an erase operation.
  • -1V was applied to the unit 170. In this case, as shown in FIG. 9A, holes are not accumulated in the first layer 130.
  • a voltage of 2 V is applied to the gate electrode unit 150, and a ground voltage GND is applied to the source electrode unit 160.
  • 1.5V was applied to the drain electrode portion 170.
  • FIG. 8B when the hole is trapped in the first layer 130 (that is, when "1" data is written), the "1" data shown in FIG. 7 is written. Current will flow.
  • FIG. 9B when the hole is not trapped in the first layer 130 as shown in FIG. 9B (that is, when "0" data is written), the "0" data shown in FIG. 7 is written. Current flows. This is because when a hole is trapped in the first layer 130 as described above, a change occurs in the threshold voltage of the device, so that more current flows.
  • the holes in the first layer 130 are trapped by the energy band difference between the first layer 130 and the second layer 140. Therefore, the hole retention time in the first layer 130 can be greatly increased as compared with the case where the conventional first layer 130 is not formed.
  • the first layer 130 may be applied to both a full depletion and a partial depletion structure.
  • the hole holding time can be further increased by applying a back bias to the semiconductor substrate of the device. That is, the applied back bias may hold the hole, thereby increasing the hole retention time in the first layer 130. It is also possible to apply a smaller back bias voltage than a full depletion structure that does not use the existing first layer 130.
  • the capacitorless memory device according to the present exemplary embodiment may be multi-level driven according to voltages applied to the source electrode 160 and the drain electrode 170.
  • FIG. 10 is a conceptual cross-sectional view for describing multilevel operation of a capacitorless memory device according to example embodiments.
  • the source voltage VS and the drain applied to the source electrode unit 160 while the gate voltage VG and the back bias voltage VB applied to the gate electrode unit 150 are kept constant.
  • the drain voltage VD applied to the electrode unit 170 multi-level driving is possible. This is because the amount of charge charged in the first layer 130 of the present embodiment is more than 100 times higher than that of the conventional Si layer alone, thereby controlling the amount of charge charged in the first layer 130 through the source voltage. Level driving is possible (see Fig. 12).
  • the drain voltage VD is applied and -2V is applied to the back bias VB, the drain current D0 of the first level flows.
  • a gate voltage VG of 2V is applied to the gate electrode unit 150, -2V is applied to the back bias VB, and a source voltage VS of 0V is provided to the source electrode unit 160.
  • the drain voltage VD of 3V is applied to the drain electrode unit 170, the drain current D1 of a second level different from the first level flows.
  • a gate voltage VG of 2V is applied to the gate electrode unit 150, -2V is applied to the back bias VB, and a source voltage VS of 0.5V is provided to the source electrode unit 160.
  • the drain voltage VD of 3V is applied to the drain electrode part 170, the drain current D2 having a third level different from the first and second levels flows.
  • a gate voltage VG of 2V is applied to the gate electrode unit 150, -2V is applied to the back bias VB, and a source voltage VS of 1V is provided to the source electrode unit 160.
  • the drain voltage VD of 3V is applied to the drain electrode part 170, the drain current D3 having a fourth level different from the first to third levels flows.
  • drain voltage is fixed and the source voltage is gradually raised from 0V, the amount of charge charged decreases.
  • the charge charged in the storage area is erased, thereby reducing the source and drain voltage.
  • drain currents of different magnitudes may flow.
  • voltages of 0 V, 0.5 V, and 1 V are used as the source voltage VS.
  • the present invention is not limited thereto, and more levels of voltage may be used as the source voltage.
  • -1V and 3V are used as the drain voltage, it is possible to use the first drain voltage of a level lower than the source voltage or a voltage higher than the source voltage as the drain voltage.
  • the capacitorless memory device according to the present embodiment may implement a multi-bit.
  • FIG. 11 is a conceptual cross-sectional view illustrating a multi-bit operation of a capacitorless memory device according to an embodiment.
  • a first bit operation and a second bit operation may be performed by changing the gate voltage VG and the back bias voltage VB.
  • the output voltage can be changed by changing the drain voltage VD in each bit operation.
  • a gate voltage VG of 2V is applied to the gate electrode unit 150, a ground voltage GND is provided to the source electrode unit 160 as the source voltage VS, and -2V is supplied as a back bias.
  • 3V and ⁇ 1V are respectively applied to the drain electrode unit 170 as the drain voltage VD to perform the operation of the first bit (see FIG. 11A).
  • the gate voltage VG of -2V is applied to the gate electrode unit 150, the ground voltage GND is provided to the source electrode unit 160, and the drain is provided in the state of providing 20V to the back bias VB.
  • 3V and -1V are respectively applied to the electrode unit 170 as the drain voltage VD to perform the operation of the second bit (see FIG. 11B).
  • a first bit operation is performed by applying a voltage having a different polarity from the bias voltage as a gate voltage of the gate electrode, and a gate voltage and a bias having a different polarity than the first bit operation are applied to the gate electrode and the semiconductor substrate.
  • the voltage may be applied to perform the operation of the second bit.
  • the absolute value of the bias voltage is greater than the absolute value of the gate voltage in the second bit operation.
  • the cap-less memory device of the present invention has a balance band energy difference with the channel layer at least under the second layer 140 under the gate electrode part 150. Thereby forming a first layer 130 that stores charge (ie, holes). This can increase the retention of charge as well as the retention time.
  • FIG. 12 is a graph illustrating a balance band energy difference between a channel layer and a storage layer and corresponding hole concentration according to an embodiment.
  • Line A1 in FIG. 12 is a graph showing the change of the balance band energy when the Si layer is used as the second layer 140 and the SiGe layer is used as the first layer 130 as in the present embodiment.
  • the line is a graph of the comparative example showing the change of the balance band energy in the case of producing a single Si layer without distinguishing the second layer 140 and the first layer 130.
  • the line A2 of FIG. 12 is a graph showing the hole concentration distribution when the Si layer is used as the second layer 140 and the SiGe layer is used as the first layer 130
  • the line B2 of FIG. It is a graph which shows distribution of the hole concentration in a Si layer.
  • the energy barrier was not formed in the B1 line.
  • the balance band A1 line it can be seen that an energy barrier is formed between the Si layers (ie, the second layer 140) and the SiGe layer (that is, the first layer 130) having different energies.
  • the hole concentration is higher (about 100 times or more) when the Si layer and the SiGe layer (see the A2 line in FIG. 12) than the single Si layer alone (see line B2 in FIG. 12). This is because, as mentioned above, an energy barrier is formed between the Si layer and the SiGe layer, so that the holes in the SiGe layer do not easily escape.
  • the size of the energy barrier (that is, the balance band energy difference between the second layer 140 and the first layer 130) may be controlled by adjusting the Ge concentration in the first layer 130.
  • FIG. 13 is a graph illustrating a balance band energy difference according to Ge concentration in a storage layer according to an embodiment.
  • a line C1 in FIG. 13 is a graph of a comparative example showing a balance band energy when the entire Si layer is formed without forming a SiGe layer (ie, the first layer 130).
  • Line C2 of FIG. 13 is a graph showing balance band energy when the Ge concentration in the SiGe layer (ie, the first layer 130) is 30 at%
  • line C3 is the balance band when the concentration of Ge is 60at%. It is a graph which shows energy
  • the C4 line is a graph which shows the balance band energy when Ge concentration is 90at%.
  • the Ge concentration in the first layer 130 is preferably maintained at 95 at% or less. Of course, the Ge concentration is preferably maintained at 90 at% or less. In addition, the Ge concentration in the first layer 130 is preferably maintained at 10 at% or more. If the Ge concentration is lower than this, the balance band energy difference between the first layer 130 and the second layer 140 is small, thereby preventing the hole from being smoothly trapped.
  • the Ge concentration is preferably maintained at 20 at% or more.
  • the interface property between the first layer 130 and the second layer 140 changes according to the Ge concentration. Therefore, it is better to keep it within the above range.
  • the Ge concentration in the first layer 130 is 100 at%.
  • FIG. 14 is a graph illustrating a memory margin according to an embodiment and modified examples
  • FIG. 15 is a graph illustrating a hole retention time according to an exemplary embodiment and modified examples.
  • Comparative examples in the graphs of FIGS. 14 and 15 refer to a structure in which the first layer 130 is not formed.
  • the embodiment and the first to third modifications refer to the structure described above with reference to FIGS. 1 to 4.
  • the Ge margin in the first layer 130 is set to 50 at% to measure the memory margin and the retention time of the holes.
  • FIG. 14 illustrates memory margin and hole retention time according to a back bias
  • FIG. 15 illustrates memory margin and hole retention time using about ⁇ 5 V as a back bias.
  • the transistor has a W / L of 1/1 mu m. And this is the value measured at normal temperature (about 25 degree
  • FIG. 14 it can be seen that memory margins of the embodiments in which the first layer 130 is formed and the first to third modified examples are increased compared to the comparative example in which the first layer 130 is not formed.
  • the third modification has a memory margin of about 2.6 times.
  • the hole retention time of the embodiment in which the first layer 130 is formed and the first to third modified examples are increased compared to the comparative example in which the first layer 130 is not formed. That is, it can be seen that the third modified example has a hole retention time of about twice as compared with the comparative example at 589 msec.
  • the capacitorless memory device of the present invention may increase hole retention time and improve memory margin by trapping holes through the first layer 130.
  • the memory margin, the balance band energy difference, and the charge retention time may vary according to the Ge concentration of the first layer 130.
  • FIG. 16 is a graph illustrating a memory margin and a balance band energy difference according to Ge concentration in a storage layer according to a third modification
  • FIG. 17 is a graph showing charge retention time according to Ge concentration in a storage layer according to a third modification. to be.
  • the Si concentration is about 50 nm and the Si concentration is about 40 nm, and the Ge concentration in each SiGe layer is increased from 0 at% to 80 at%. It is a graph measuring retention time.
  • the back bias voltage was applied at ⁇ 5 V during the measurement.
  • a circular point D1 in FIG. 16 is a value showing a memory margin different from Ge concentration. Looking at the circular point, it can be seen that as the concentration of Ge increases, the memory margin increases. Here, it can be seen that when the Ge concentration is increased to 80at% than that of 0at%, the memory margin is increased about 4 times.
  • the line D2 of FIG. 16 is a graph showing a balance band energy difference between the Si layer and the SiGe layer according to the Ge concentration. Looking at the D2 line, it can be seen that as the Ge concentration increases, the balance band energy difference between the two layers increases.
  • the line D4 is a graph measuring the charge retention time according to the Ge concentration at 85 degrees. Looking at the lines D3 and D4, it can be seen that as the concentration of Ge increases, the charge retention time increases. In addition, when the Ge concentration is about 70 at% or more at a temperature of 25 ° C, it can be seen that the charge retention time is 1 second or more. In other words, when the Ge concentration is 0at%, the charge retention time was about 285msec, but when the Ge concentration was 80at%, the charge retention time was increased by about 4 times to 1228msec.
  • the capacitorless memory device of the present embodiment can lower the back bias dependency on the read voltage.
  • FIG. 18 is a graph illustrating a drain voltage current change of a capacitorless memory device according to an embodiment
  • FIG. 19 is a graph of a drain voltage current change of a capacitorless memory device according to a comparative example.
  • FIG. 18 and 19 are graphs illustrating drain voltage-current changes measured by applying back bias voltages of 0 V, ⁇ 1 V, ⁇ 2 V, ⁇ 3 V, ⁇ 4 V, and ⁇ 5 V, respectively. It is a graph showing the change of voltage and current with 0V applied as a back bias voltage, -1V for VB1, -2V for VB2, -3V for VB3, -4V for VB4, and -5V for VB4.
  • FIG. 18 shows that the Ge concentration in the first layer 130 is 30 at%, the thickness of the second layer 140 is 20 nm, and the thickness of the first layer 130 in the structure according to the embodiment of the present invention. It was set to 70 nm. In the comparative example of FIG. 19, the voltage current change of the memory device of the capacitorless without the first layer 130 formed and only the Si layer having a thickness of about 90 nm is formed.
  • the amount of change in current at the same voltage was about 12 mA according to the back bias voltage.
  • the amount of change in current at the same voltage was 9 mA according to the back bias voltage. It was reduced by two thirds. It can be seen that the capacitorless memory device of this embodiment is less dependent on the back bias voltage than the modified example.
  • the electron mobility of the channel region C may be reduced by using the strained Si layer as the second layer 140 on the upper side of the first layer 130. You can increase it.
  • the structure of the capacitorless memory device according to the present embodiment is not limited to the above-described embodiment and the first to third modifications, and various modifications are possible.
  • 20 to 23 are diagrams of capacitorless memory devices according to fourth to seventh modifications.
  • the insulating layer 120, the first layer 130, and the second layer 140 are sequentially stacked on the substrate 110 as illustrated in FIG. 20.
  • a portion of the second layer 140 is recessed, and the gate electrode 150 is formed on the recessed region.
  • the source and drain electrode portions 160 and 170 are formed on both sides of the recessed region (ie, both sides of the gate electrode portion 150).
  • a part of the gate electrode part 150 may protrude and extend into the second layer 140.
  • the source and drain electrode portions 160 may be positioned in an upper region of the second layer 140.
  • the capacitorless memory device removes a portion of the insulating layer 120 to connect the first layer 130 and the semiconductor substrate 110. It is further provided.
  • the first layer 130 may be grown from the semiconductor substrate 110 through the connection layer 131 to form the first layer 130 on the insulating layer 120.
  • the insulating layer 120 is formed on the semiconductor substrate 110.
  • a portion of the insulating layer 120 is etched to form a groove exposing a portion of the semiconductor substrate 110.
  • the first layer 130 is formed through the deposition process, but the connection layer 131 is formed first inside the groove, and the continuous deposition is performed to form the first layer 130.
  • the first layer 130 including SiGe may be formed on the insulating layer 120 without performing a separate bonding or cleaving process.
  • the first layer 130 having a bar or island shape is formed in a portion of the upper portion of the insulating layer 120.
  • the second layer 140 surrounding at least three surfaces of the first layer 130 and the gate insulating layer 151 surrounding the second layer 140 are formed.
  • the gate electrode 152 is formed in the sidewall surface region of the second layer 140 to be in contact with the insulating layer 120 and the gate insulating layer 151.
  • source and drain electrode layers 160 and 170 are formed in the second layer 140 and the first layer 130 at both sides of the gate electrode 152 through ion implantation. This can simplify the structure of the device, it is possible to reduce the height of the device.
  • the first layer 130 may be wrapped with the second layer 140 to increase the charge storage capability in the first layer 130.
  • a first layer 130 having a bar or island shape is formed on a portion of the insulating layer 120 and the first layer 130 is formed.
  • a gate insulating layer 151 and a gate electrode 152 covering at least three surfaces of the second layer 140 are sequentially formed in a portion of the second layer 140.
  • the source and drain electrode portions 160 and 170 are formed by ion implantation into the second layer 140 and the first layer 130 on both sides of the gate electrode 152. As such, the length of the channel and the cross-sectional area of the channel may be extended by manufacturing the second layer 140 in the shape of the gate electrode 152.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
PCT/KR2009/002284 2008-04-30 2009-04-30 무 커패시터 메모리 소자 Ceased WO2009134089A2 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2011507351A JP5496184B2 (ja) 2008-04-30 2009-04-30 キャパシタレスメモリ素子
US12/990,353 US8860109B2 (en) 2008-04-30 2009-04-30 Capacitor-less memory device
EP09738995.1A EP2284879B1 (en) 2008-04-30 2009-04-30 Capacitor-less memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2008-0040888 2008-04-30
KR1020080040888A KR101505494B1 (ko) 2008-04-30 2008-04-30 무 커패시터 메모리 소자

Publications (2)

Publication Number Publication Date
WO2009134089A2 true WO2009134089A2 (ko) 2009-11-05
WO2009134089A3 WO2009134089A3 (ko) 2010-02-11

Family

ID=41255563

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2009/002284 Ceased WO2009134089A2 (ko) 2008-04-30 2009-04-30 무 커패시터 메모리 소자

Country Status (6)

Country Link
US (1) US8860109B2 (https=)
EP (1) EP2284879B1 (https=)
JP (1) JP5496184B2 (https=)
KR (1) KR101505494B1 (https=)
TW (1) TWI419327B (https=)
WO (1) WO2009134089A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8878191B2 (en) 2008-12-05 2014-11-04 Micron Technology, Inc. Fin field effect transistors including energy barriers

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105707B2 (en) 2013-07-24 2015-08-11 International Business Machines Corporation ZRAM heterochannel memory
KR20160074826A (ko) 2014-12-18 2016-06-29 삼성전자주식회사 반도체 장치
US10403628B2 (en) 2014-12-23 2019-09-03 International Business Machines Corporation Finfet based ZRAM with convex channel region
US9978772B1 (en) * 2017-03-14 2018-05-22 Micron Technology, Inc. Memory cells and integrated structures
US11056571B2 (en) * 2019-06-18 2021-07-06 Micron Technology, Inc. Memory cells and integrated structures

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840855A (ja) * 1981-09-04 1983-03-09 Hitachi Ltd 半導体記憶素子
JPH06177375A (ja) * 1992-12-10 1994-06-24 Hitachi Ltd 半導体装置及びその製造方法
JP3361922B2 (ja) * 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3407232B2 (ja) * 1995-02-08 2003-05-19 富士通株式会社 半導体記憶装置及びその動作方法
JPH1092952A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体記憶装置
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
KR100257765B1 (ko) * 1997-12-30 2000-06-01 김영환 기억소자 및 그 제조 방법
JP4713783B2 (ja) * 2000-08-17 2011-06-29 株式会社東芝 半導体メモリ装置
JP3884266B2 (ja) * 2001-02-19 2007-02-21 株式会社東芝 半導体メモリ装置及びその製造方法
JP2003031693A (ja) * 2001-07-19 2003-01-31 Toshiba Corp 半導体メモリ装置
KR20030034470A (ko) * 2001-10-23 2003-05-09 주식회사 하이닉스반도체 실리콘-게르마늄 채널을 포함하는 트랜지스터의 제조방법
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
JP4880867B2 (ja) * 2002-04-10 2012-02-22 セイコーインスツル株式会社 薄膜メモリ、アレイとその動作方法および製造方法
US7042052B2 (en) * 2003-02-10 2006-05-09 Micron Technology, Inc. Transistor constructions and electronic devices
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US20050062088A1 (en) * 2003-09-22 2005-03-24 Texas Instruments Incorporated Multi-gate one-transistor dynamic random access memory
US7057216B2 (en) * 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US7244958B2 (en) * 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
JP4239203B2 (ja) * 2005-05-31 2009-03-18 株式会社東芝 半導体装置とその製造方法
US7517741B2 (en) * 2005-06-30 2009-04-14 Freescale Semiconductor, Inc. Single transistor memory cell with reduced recombination rates
US8410539B2 (en) * 2006-02-14 2013-04-02 Stmicroelectronics (Crolles 2) Sas MOS transistor with a settable threshold
JP2008213624A (ja) 2007-03-02 2008-09-18 Toyota Motor Corp 操作機構および操作機構を備えた車両
US7928426B2 (en) * 2007-03-27 2011-04-19 Intel Corporation Forming a non-planar transistor having a quantum well channel
US7948008B2 (en) * 2007-10-26 2011-05-24 Micron Technology, Inc. Floating body field-effect transistors, and methods of forming floating body field-effect transistors
JP5403212B2 (ja) 2008-10-06 2014-01-29 株式会社Ｉｈｉ 白色ｌｅｄの製造装置と方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
None
See also references of EP2284879A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8878191B2 (en) 2008-12-05 2014-11-04 Micron Technology, Inc. Fin field effect transistors including energy barriers

Also Published As

Publication number Publication date
EP2284879A4 (en) 2012-05-23
TWI419327B (zh) 2013-12-11
EP2284879B1 (en) 2020-05-06
WO2009134089A3 (ko) 2010-02-11
US8860109B2 (en) 2014-10-14
US20110127580A1 (en) 2011-06-02
KR20090114981A (ko) 2009-11-04
JP2011519483A (ja) 2011-07-07
EP2284879A2 (en) 2011-02-16
TW200950088A (en) 2009-12-01
KR101505494B1 (ko) 2015-03-24
JP5496184B2 (ja) 2014-05-21

Similar Documents

Publication Publication Date Title
WO2010041838A2 (ko) 고집적 플래시 메모리 셀 스택, 셀 스택 스트링 및 그 제조 방법
US6632723B2 (en) Semiconductor device
US6222234B1 (en) Semiconductor device having partially and fully depleted SOI elements on a common substrate
CN101295735B (zh) 非易失性半导体存储器件
WO2009134089A2 (ko) 무 커패시터 메모리 소자
KR930009138B1 (ko) 반도체기억장치의 셀구조
WO2017175955A1 (ko) 수직 반도체 컬럼을 구비한 메모리 소자
WO2019235701A1 (ko) 수직형 메모리 소자 및 그의 제조 방법
CN104716097A (zh) 半导体装置的制造方法
US6995025B2 (en) Asymmetrical programming ferroelectric memory transistor
WO2019245106A1 (ko) 셀 신뢰성 향상을 위한 수직 집적형 삼차원 플래시메모리 및 그 제조 방법
WO2018101770A1 (ko) 2단자 수직형 1t-디램 및 그 제조 방법
JP2011519483A5 (https=)
US7283394B2 (en) Trench corner effect bidirectional flash memory cell
WO2021137432A1 (ko) 트랜지스터, 이를 포함하는 삼진 인버터, 및 트랜지스터의 제조 방법
KR0151053B1 (ko) Soi 구조를 갖는 반도체장치의 제조방법
WO2024005610A1 (ko) 박막 트랜지스터 및 박막 트랜지스터의 제조 방법
WO2018135914A1 (ko) 디램 셀 소자 및 그 제조방법
KR100866125B1 (ko) 스위치드 스토리지 노드 콘택 구조를 이용한 디램
KR100876878B1 (ko) 새로운 디램 셀 구조
WO2019177287A1 (ko) 디램 셀 메모리 소자
TWI884880B (zh) 光學檢測裝置及光學檢測裝置的製作方法
WO2010013886A9 (ko) 고집적 플래시 메모리 셀 소자, 셀 스트링 및 그 제조 방법
WO2023287174A1 (ko) 컴팩트 드레인 및 이종 물질 구조에 기반하는 트랜지스터
Sanjeevi et al. Effect of Charge Retention of Non-Volatile Memory TFTs Under Multiple Read Cycles

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09738995

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2011507351

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2009738995

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 12990353

Country of ref document: US