WO2009119103A1 - 半導体基板、半導体装置、および半導体装置の製造方法 - Google Patents
半導体基板、半導体装置、および半導体装置の製造方法 Download PDFInfo
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- WO2009119103A1 WO2009119103A1 PCT/JP2009/001375 JP2009001375W WO2009119103A1 WO 2009119103 A1 WO2009119103 A1 WO 2009119103A1 JP 2009001375 W JP2009001375 W JP 2009001375W WO 2009119103 A1 WO2009119103 A1 WO 2009119103A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 230
- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 150000001875 compounds Chemical class 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 25
- 230000001590 oxidative effect Effects 0.000 claims abstract description 21
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 13
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000005684 electric field Effects 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims description 20
- 238000007254 oxidation reaction Methods 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- 238000009279 wet oxidation reaction Methods 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 202
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
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- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Definitions
- the present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing the semiconductor device.
- the present invention particularly relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing the semiconductor device, which are effective when applied to a compound semiconductor device capable of forming a MOS structure by a simple process.
- Non-Patent Document 1 discloses an oxidation process of InAlAs and its application to a semiconductor substrate for manufacturing a semiconductor device. That is, assuming a gate insulating layer in an InAlAs / InGaAs MOS type HEMT (High Electron Mobility Transistor), an n-type InAlAs layer formed on a semiconductor substrate and functioning as a channel layer is oxidized. A semiconductor substrate is described.
- a first semiconductor layer of a Group 3-5 compound that does not contain arsenic that lattice matches or pseudo-lattice matches with InP, and the first semiconductor layer is in contact with the first semiconductor layer.
- a substrate is provided.
- the first semiconductor layer may not contain aluminum.
- a semiconductor of a Group 3-5 compound that is formed in contact with the first semiconductor layer, lattice-matched or pseudo-lattice-matched to InP, and has an electron affinity greater than InP may be provided.
- the second semiconductor layer may include aluminum. Specifically, the second semiconductor layer may be In x Al 1-x As, and x may be a value between 0 and 1.
- the first semiconductor layer of a Group 3-5 compound that does not contain arsenic that is lattice-matched or pseudo-lattice-matched to InP, and the InP formed in contact with the first semiconductor layer are latticed.
- a control electrode that applies an electric field to the semiconductor device.
- the oxide layer may be a control electrode insulating layer formed between the first semiconductor layer and the control electrode, or a buried oxide layer formed so as to be embedded on the substrate side from the first semiconductor layer.
- a non-oxidized portion of the second semiconductor layer remains in the same layer as the oxide layer, and is an ohmic layer formed above the non-oxidized portion of the second semiconductor layer, wherein the oxide layer is formed
- An ohmic layer having an opening at a portion thereof, and a pair of input / output electrodes formed in a layer above the ohmic layer and supplying a current flowing through the channel.
- the control electrode may be formed on the insulating layer inside the opening.
- the ohmic layer may be an aluminum-free group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and the ohmic layer may be doped p-type or n-type.
- the first semiconductor layer of a Group 3-5 compound that does not contain arsenic that is lattice-matched or pseudo-lattice-matched to InP, and the InP formed in contact with the first semiconductor layer are latticed.
- a method for manufacturing a semiconductor device comprising: an oxidation step for forming an oxide layer; and a control electrode formation step for forming a control electrode above the oxide layer formed in the oxidation step.
- the oxidation step may be a step of oxidizing the second semiconductor layer exposed in the opening to selectively form the oxide layer in the opening.
- the oxidizing step may be a step of forming the oxide layer in a self-aligned manner on the mask by exposing the second semiconductor layer exposed in the opening using the ohmic layer as a mask to an oxidizing atmosphere.
- the ohmic layer may be a p-type semiconductor layer or an n-type semiconductor layer of a group 3-5 compound that does not contain aluminum and lattice matches or pseudo-lattice matches with InP.
- the oxidation step may be a step of forming the oxide layer by a wet oxidation method.
- the first semiconductor is made of a group 3-5 compound not containing arsenic and functions as a channel of a transistor, and is provided on the first semiconductor and is oxidized in an oxidizing atmosphere to be insulated.
- a semiconductor substrate including a second semiconductor serving as a body is provided.
- the first semiconductor and the second semiconductor may be lattice-matched or pseudo-lattice-matched to InP.
- the first semiconductor may not be oxidized in an oxidizing atmosphere.
- the second semiconductor may be selectively oxidized by disposing a mask covering the non-oxidized region and exposing the oxidized region on the surface of the second semiconductor.
- An example of a cross section of the semiconductor device 100 of this embodiment is shown.
- An example of a cross section in the manufacturing process of the semiconductor device 100 is shown.
- An example of a cross section in the manufacturing process of the semiconductor device 100 is shown.
- An example of a cross section in the manufacturing process of the semiconductor device 100 is shown.
- the current voltage characteristic of an experimental sample is shown.
- the capacitance-voltage characteristic of the sample which performed wet oxidation for 45 minutes is shown.
- FIG. 1 shows a cross-sectional example of the semiconductor device 100 of the present embodiment.
- the semiconductor device 100 includes a substrate 102, a buffer layer 104, a first semiconductor layer 106, a second semiconductor layer 108, an oxide layer 110, a control electrode 112, an ohmic layer 114, and an input / output electrode 116.
- the substrate 102 can be made of any material as long as a compound semiconductor crystal layer can be formed on the surface thereof.
- Examples of the substrate 102 include a single crystal silicon wafer, a sapphire substrate, and a single crystal InP substrate.
- the buffer layer 104 may be a compound semiconductor layer that is lattice-matched or pseudo-lattice-matched with the first semiconductor layer 106, and is formed between the first semiconductor layer 106 and the substrate 102.
- the buffer layer 104 may be formed for the purpose of increasing the crystallinity of the first semiconductor layer 106 or reducing the influence of impurities from the substrate 102.
- Examples of the buffer layer 104 include an InP layer, an InGaAs layer, an InAlAs layer, or a stacked layer thereof, which are doped or not doped with impurities.
- the InP layer, InGaAs layer, or InAlAs layer can be formed by using, for example, an MOCVD method (organic metal vapor deposition method) using an organic metal gas as a source gas.
- the first semiconductor layer 106 may be a group 3-5 compound that does not contain arsenic that lattice matches or pseudo-lattice matches with InP.
- the first semiconductor layer 106 may not contain aluminum. By not containing aluminum, the first semiconductor layer 106 can be prevented from being oxidized when the second semiconductor layer 108 is oxidized to form the oxide layer 110.
- the first semiconductor layer 106 may have a higher electron affinity than InP. By increasing the electron affinity, the depth of the interface state formed at the interface between the first semiconductor layer 106 and the oxide layer 110 can be reduced. As a result, the performance of the device can be improved.
- the first semiconductor layer 106 may function as a functional layer of an electronic device, and may be, for example, a channel layer in which a MISFET channel is formed.
- An example of the first semiconductor layer 106 is an InP layer.
- the first semiconductor layer 106 may be doped with impurities or may not be doped.
- the first semiconductor layer 106 can be formed using, for example, an MOCVD method using an organometallic gas as a source gas.
- another semiconductor layer may be formed between the buffer layer 104 and the first semiconductor layer 106.
- Other semiconductor layers may include arsenic.
- An example of the semiconductor layer containing arsenic is an InGaAs layer.
- the other semiconductor layer may be a channel layer of MISFET, for example, and the other semiconductor layer and the first semiconductor layer 106 may be a channel layer.
- the channel may be formed at the interface between the other semiconductor layer and the first semiconductor layer 106, and is away from the interface with the oxide layer 110 formed above the first semiconductor layer 106.
- the second semiconductor layer 108 is formed in contact with the first semiconductor layer 106.
- the second semiconductor layer 108 may be a group 3-5 compound semiconductor layer lattice-matched or pseudo-lattice-matched to InP.
- the semiconductor layer 108 may be capable of being selectively oxidized with respect to the first semiconductor layer 106.
- the second semiconductor layer 108 may contain aluminum, specifically, In x Al 1-x As (where 0 ⁇ x ⁇ 1). However, it is desirable that aluminum is 50% or more with respect to indium.
- the oxide layer 110 is formed in contact with the first semiconductor layer 106 and is formed by selectively oxidizing at least part of the second semiconductor layer 108 with respect to the first semiconductor layer 106.
- the selective oxidation of the second semiconductor layer 108 can be performed by, for example, forming a mask covering the other non-oxidized regions on the second semiconductor layer 108 by exposing an oxidized region that becomes the oxidized layer 110.
- the oxide layer 110 may be an insulating layer that insulates the control electrode formed between the first semiconductor layer 106 and the control electrode 112, that is, a gate insulating layer in the case of a MOSFET. Alternatively, it may be a buried oxide layer formed by being buried closer to the substrate 102 than the first semiconductor layer 106. When the oxide layer 110 is formed as a buried oxide layer, a double-gate MOSFET can be formed.
- the composition of the oxide layer 110 is formed by oxidizing the second semiconductor layer 108, it is determined according to the composition of the second semiconductor layer 108.
- a wet method can be exemplified.
- the oxide layer 110 is formed by oxidizing the second semiconductor layer 108 by a wet method under a processing condition of 500 ° C. or higher, the density of interface states can be reduced to 1012 units.
- the control electrode 112 is formed on the oxide layer 110 and applies an electric field to the channel formed in the first semiconductor layer 106.
- the control electrode 112 can function as a gate electrode of MISFET, for example. Examples of the control electrode 112 include any metal, polysilicon, metal silicide, and the like.
- the control electrode 112 is formed in the opening region 118 where the oxide layer 110 obtained by oxidizing the second semiconductor layer 108 is formed.
- the ohmic layer 114 is in ohmic contact with the input / output electrode 116.
- the ohmic layer 114 is formed above the region 120 where the non-oxidized portion of the second semiconductor layer 108 that is the same layer as the oxide layer 110 remains.
- the ohmic layer 114 has an opening region 118 in a portion where the oxide layer 110 is formed.
- the ohmic layer 114 may be a group 3-5 compound semiconductor layer that does not contain aluminum and lattice matches or pseudo-lattice matches with InP.
- the ohmic layer 114 may be doped p-type or n-type.
- the input / output electrodes 116 are formed in a layer above the ohmic layer 114 as a pair of electrodes.
- the input / output electrode 116 supplies a current flowing through the channel.
- the input / output electrode 116 functions as, for example, a source or drain electrode of a MISFET.
- Examples of the input / output electrodes 116 include metals such as nickel, platinum, and gold, heavy-doped polysilicon, and metal silicide.
- the substrate 102, the buffer layer 104, the first semiconductor layer 106, and the second semiconductor layer 108 may be grasped as one semiconductor substrate.
- a semiconductor substrate can arbitrarily oxidize the second semiconductor layer 108 to form a control electrode oxide layer, and can quickly manufacture a device such as a MOSFET.
- the buffer layer 104 is not essential for the semiconductor substrate, and the first semiconductor layer 106 itself may be the substrate 102.
- the MOSFET is exemplified as the semiconductor device 100, but another electronic device may be used.
- the semiconductor device 100 may be a capacitor in which an oxide layer 110 formed by oxidizing the second semiconductor layer 108 is sandwiched between the control electrode 112 and the first semiconductor layer 106.
- FIG. 2 to 5 show cross-sectional examples in the manufacturing process of the semiconductor device 100.
- FIG. 2 a substrate 102 having a buffer layer 104 and a first semiconductor layer 106 is prepared.
- the buffer layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using, for example, the MOCVD method.
- the second semiconductor layer 108 is formed above the first semiconductor layer 106.
- the second semiconductor layer 108 can be formed by, for example, the MOCVD method.
- the second semiconductor layer 108 may be formed by p-type or n-type doping.
- an opening is formed in the ohmic layer 114, and the second semiconductor layer 108 is exposed on the bottom surface of the opening.
- the second semiconductor layer 108 exposed in the opening is oxidized using the ohmic layer 114 as a mask. Oxidation is performed on the second semiconductor layer 108 selectively with respect to the first semiconductor layer 106. In addition, oxidation is performed on the second semiconductor layer 108 selectively in the opening of the ohmic layer 114.
- An oxide layer 110 is formed by oxidation of the second semiconductor layer 108.
- the second semiconductor layer 108 contains aluminum, while the first semiconductor layer 106 and the ohmic layer 114 do not contain aluminum. For this reason, the first semiconductor layer 106 and the ohmic layer 114 are not oxidized, and the oxidation is performed selectively on the second semiconductor layer 108 and in a self-aligned manner with respect to the opening. Thereby, the oxide layer 110 can be easily formed.
- the oxidation treatment in this case can be performed by exposing the second semiconductor layer 108 exposed in the opening to an oxidizing atmosphere.
- control electrode 112 and the input / output electrode 116 are formed by forming and patterning a conductive film. Then, the semiconductor device 100 shown in FIG. 1 can be manufactured.
- the oxide layer 110 is formed by selectively oxidizing the second semiconductor layer 108, the MOSFET can be easily manufactured.
- a wet method can be used for the oxidation, the interface state can be reduced and a practical compound semiconductor MOSFET can be formed.
- Example 10 nm of InAlAs was formed on the (100) plane of the InP substrate not doped with impurities. Thereafter, the InAlAs layer was selectively oxidized to form an insulating film. A wet method at a treatment temperature of 525 ° C. was used for the oxidation. An aluminum electrode was formed on the insulating film by vapor deposition to prepare an experimental sample.
- Fig. 6 shows the current-voltage characteristics of the experimental sample. Good insulation was confirmed in the sample subjected to wet oxidation for 45 minutes. In the sample in which the wet oxidation shown as a comparison was performed for 30 minutes, a decrease in insulating property could be confirmed. Further, in the sample not subjected to the wet oxidation shown as a comparison, it was confirmed that the insulation was further lowered.
- FIG. 7 shows the capacity-voltage characteristics of a sample subjected to wet oxidation for 45 minutes. Capacitance change with respect to voltage change was confirmed in the range of 5 kHz to 1 MHz. That is, it was confirmed that an inversion layer was formed in the InP layer below the insulating layer and operated as a MOS. As a result of evaluating the interface state by the conductance method, 1012 interface states could be measured.
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Abstract
Description
102 基板
104 バッファ層
106 第1半導体層
108 第2半導体層
110 酸化層
112 制御電極
114 オーミック層
116 入出力電極
118 開口領域
120 領域
不純物をドープしないInP基板の(100)面上にInAlAsを10nm形成した。その後、InAlAs層を選択的に酸化して絶縁膜を形成した。酸化には525℃の処理温度でのウェット法を用いた。絶縁膜上にアルミニウム電極を蒸着法により形成して実験サンプルとした。
Claims (20)
- InPに格子整合または擬格子整合し、砒素を含まない3-5族化合物の第1半導体層と、
前記第1半導体層に接して形成され、InPに格子整合または擬格子整合する3-5族化合物の半導体層であって、前記第1半導体層に対し選択的に酸化が可能な第2半導体層と、
を備えた半導体基板。 - 前記第1半導体層は、アルミニウムを含まない、
請求項1に記載の半導体基板。 - 前記第1半導体層に接して形成され、InPに格子整合または擬格子整合し、電子親和力がInPより大きい、3-5族化合物の半導体を備えた、
請求項1に記載の半導体基板。 - 前記第2半導体層は、アルミニウムを含む、
請求項1から請求項3の何れか一項に記載の半導体基板。 - 前記第2半導体層は、InxAl1-xAsであり、
xは、0と1との間の値であること、
を特徴とする請求項4に記載の半導体基板。 - InPに格子整合または擬格子整合し、砒素を含まない3-5族化合物の第1半導体層と、
前記第1半導体層に接して形成され、InPに格子整合または擬格子整合する3-5族化合物の第2半導体層の少なくとも一部を前記第1半導体層に対し選択的に酸化して形成した酸化層と、
前記第1半導体層に形成されるチャネルに電界を加える制御電極と、
を備えた半導体装置。 - 前記酸化層は、前記第1半導体層と前記制御電極との間に形成された制御電極絶縁層、または、前記第1半導体層より基板側に埋め込んで形成された埋め込み酸化層である、
請求項6に記載の半導体装置。 - 前記酸化層と同一の層に、前記第2半導体層の非酸化部が残存し、
前記第2半導体層の前記非酸化部より上層に形成されたオーミック層であって、前記酸化層が形成された部分に開口部を有するオーミック層と、
前記オーミック層より上層に形成された、前記チャネルに流れる電流を供給する一対の入出力電極と、
を備えた請求項6または請求項7に記載の半導体装置。 - 前記制御電極は、前記開口部の内部の前記酸化層の上に形成された、
請求項8に記載の半導体装置。 - 前記オーミック層は、InPに格子整合または擬格子整合する、アルミニウムを含まない3-5族化合物半導体層である、
請求項8または請求項9に記載の半導体装置。 - 前記オーミック層は、p形またはn形にドープされている、
請求項10に記載の半導体装置。 - InPに格子整合または擬格子整合し、砒素を含まない3-5族化合物の第1半導体層と、前記第1半導体層に接して形成され、InPに格子整合または擬格子整合する3-5族化合物の第2半導体層と、を有する半導体基板を準備する基板準備段階と、
前記第2半導体層を前記第1半導体層に対して選択的に酸化して酸化層を形成する酸化段階と、
前記酸化段階で形成した前記酸化層より上層に制御電極を形成する制御電極形成段階と、
を備えた半導体装置の製造方法。 - 前記基板準備段階の後に、前記第2半導体層を覆うオーミック層を形成する段階と、
前記オーミック層に開口部を形成して、前記開口部の底面に前記第2半導体層を露出する段階と、をさらに備え、
前記酸化段階は、前記開口部に露出した前記第2半導体層を酸化して、前記開口部に選択的に前記酸化層を形成する段階である、
請求項12に記載の半導体装置の製造方法。 - 前記酸化段階は、前記オーミック層をマスクとして前記開口部に露出した前記第2半導体層を酸化雰囲気に曝露することにより、前記酸化層を前記マスクに自己整合的に形成する段階である、
請求項13に記載の半導体装置の製造方法。 - 前記オーミック層は、InPに格子整合または擬格子整合する、アルミニウムを含まない3-5族化合物のp形半導体層またはn形半導体層である、
請求項13に記載の半導体装置の製造方法。 - 前記酸化段階は、ウェット酸化法により前記酸化層を形成する段階である、
請求項12から請求項15の何れか一項に記載の半導体装置の製造方法。 - 砒素を含まない3-5族化合物からなり、トランジスタのチャネルとして機能する第1半導体と、
前記第1半導体の上に設けられ、酸化雰囲気において酸化されて絶縁体となる第2半導体と
を備えた半導体基板。 - 前記第1半導体および前記第2半導体は、InPに格子整合または擬格子整合する
請求項17に記載の半導体基板。 - 前記第1半導体は、酸化雰囲気において酸化されない
請求項17または請求項18に記載の半導体基板。 - 前記第2半導体は、非酸化領域を覆うマスクであって酸化領域を露出するマスクを前記第2半導体の表面に配置することにより、選択的に酸化できる
請求項17から請求項19の何れかに記載の半導体基板。
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