TWI449107B - 半導體裝置，及半導體裝置之製造方法 - Google Patents

半導體裝置，及半導體裝置之製造方法 Download PDF

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TWI449107B
TWI449107B TW098110343A TW98110343A TWI449107B TW I449107 B TWI449107 B TW I449107B TW 098110343 A TW098110343 A TW 098110343A TW 98110343 A TW98110343 A TW 98110343A TW I449107 B TWI449107 B TW I449107B
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semiconductor layer
semiconductor
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ohmic
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Mitsuru Takenaka
Shinichi Takagi
Masahiko Hata
Osamu Ichikawa
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Univ Tokyo
Sumitomo Chemical Co
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Description

半導體裝置，及半導體裝置之製造方法
本發明係關於半導體基板、半導體裝置、及半導體裝置之製造方法。本發明是特別有關可以用簡單的工程形成MOS構造的可有效適用於化合物半導體裝置的半導體基板、半導體裝置、以及半導體裝置之製造方法。
由於具有高電子移動度的特性，故實用的以化合物半導體所製的MOSFET(金屬氧半導體場效電晶體)相當受到期望。例如，非專利文獻1係揭示有關InAlAs之氧化處理、以及將其應用於半導體裝置製造用之半導體基板。亦即，記載有假想InAlAs/InGaAs系的MOS型HEMT(高電子移動度電晶體)中的閘極絕緣層，並氧化形成於半導體基板，作為通道層功能的InGaAs層上的n形InAlAs，而構成半導體基板。
(非專利文獻1)N.C.Paul等著，Jpn.J.Appl.Phys...第44卷(2005年)，No.3，第1174至1180頁。
然而，化合物半導體例如於具有3-5族化合物半導體的半導體基板中，難以形成良好的MOS界面(半導體層與氧化物層間的界面)，而成為製造半導體裝置的阻礙。因此，期望能夠以實用且簡單的手法，形成3-5族化合物半導體與氧化層間之良好界面的半導體基板。
為了解決上述課題，於本發明之第一形態中所提供的半導體基板，係具有：第1半導體層，格子整合或擬似格子整合於InP且不包含砷的3-5族化合物；以及第2半導體層，為鄰接於前述第1半導體層而形成且格子整合或擬似格子整合於InP的3-5族化合物半導體層，相對於前述第1半導體層可選擇性的氧化。前述第1半導體層亦可以不含有鋁。亦可具有鄰接前述第1半導體層而形成，格子整合或擬似格子整合於InP，且電子親和力比InP更大的3-5族化合物半導體。前述第2半導體層，可以包含鋁，具體而言，前述第2半導體層可為Inx Al1-x As，且x為0與1之間的值。
於本發明之第二型態中所提供的半導體裝置，係具有：第1半導體層，格子整合或擬似格子整合於InP且不包含砷的3-5族化合物；第2半導體層，鄰接前述第1半導體層而形成且格子整合或擬似格子整合於InP的3-5族化合物；歐姆層，覆蓋前述第2半導體層而形成，且具有開口部；氧化層，將前述第2半導體層在前述開口部露出的部分相對於前述第1半導體層而選擇性的氧化形成；以及控制電極，在形成於前述第1半導體層的通道施加電場。在前述歐姆層上形成前述開口部的階段之後，不對前述第2半導體層進行蝕刻，形成前述氧化層。前述氧化層可以是形成於前述第1半導體層與前述控制電極之間的控制電極絕緣層，或是比前述第1半導體層更埋入基板側而 形成的埋入氧化層。且亦可進一步具有：在與前述氧化層同一層，殘留有前述第2半導體層的非氧化部；前述歐姆層形成於比前述第2半導體層之前述非氧化部更上層，在形成有前述氧化層的部分有開口部之歐姆層；以及一對輸出入電極，形成於比前述歐姆層更上層，且供給於前述通道流動之電流。前述控制電極可形成於前述開口部之內部的前述絕緣層之上。前述歐姆層可為格子整合或擬似格子整合於InP，且不含鋁的3-5族化合物半導體層，前述歐姆層係可被摻雜為p型或n型。
於本發明之第三型態中所提供的半導體裝置之製造方法，係具有：基板準備階段，準備一種半導體基板，其係具有：第1半導體層，為格子整合或擬似格子整合於InP且不包含砷的3-5族化合物；以及第2半導體層，為鄰接於前述第1半導體層而形成且格子整合或擬似格子整合於InP的3-5族化合物；形成將前述第2半導體層覆蓋之歐姆層的階段；於前述歐姆層形成開口部，且於前述開口部之底面露出前述第2半導體層的階段；氧化階段，在形成前述開口部並將前述第2半導體層露出的階段之後，不對前述第2半導體層進行蝕刻，將前述第2半導體層相對於前述第1半導體層選擇性氧化而形成氧化層；以及控制電極形成階段，在比前述氧化階段所形成的前述氧化層更上層形成控制電極。亦可復具有：於前述基板準備階段之後，形成將前述第2半導體層覆蓋之歐姆層(ohmic layer)的階段；以及於前述歐姆層形成開口部，且於前述開口部之底 面露出前述第2半導體層的階段；前述氧化階段，可以是使露出於前述開口部的前述第2半導體層氧化，而於前述開口部選擇性地形成前述氧化層的階段。前述氧化階段，可以是以前述歐姆層作為遮罩而使前述開口部露出的前述第2半導體層曝露於氧化環境下，藉此使前述氧化層自我整合地形成於前述遮罩的階段。前述歐姆層可為格子整合或擬似格子整合於InP，且不含鋁的3-5族化合物之p型半導體層或n型半導體層。前述氧化階段亦可為藉由濕化氧化法而形成前述氧化層的階段。
於本發明之第四型態中所提供的半導體基板，係具有：第1半導體層，由不包含砷的3-5族化合物所構成，而作為電晶體之通道功能；以及第2半導體層，設置於前述第1半導體層之上，且於氧化環境中被氧化而成為絕緣體。前述第1半導體層及前述第2半導體可為格子整合或擬似格子整合於InP。前述第1半導體較好為在氧化環境中不會被氧化。前述第2半導體，可將覆蓋非氧化區域之遮罩且使氧化區域露出的遮罩，藉由配置於前述第2半導體之表面，而可選擇性地進行氧化。
第1圖表示本實施形態之半導體裝置100之剖面例。半導體裝置100係具備基板102、緩衝層104、第1半導體層106、第2半導體層108、氧化層110、控制電極112、歐姆(ohmic)層114、以及輸出入電極116。
基板102是限定於其表面可形成化合物半導體之結晶 層即可，可以選擇任意之材質等。就基板102而言，可以列舉例如單晶矽晶圓、藍寶石基板、單晶InP基板等。
緩衝層104為與第1半導體層106格子整合或擬似格子整合的化合物半導體層，其係形成於第1半導體層106與基板102之間。緩衝層104可以是以提昇第1半導體層106之結晶性為目的，或著，以減低來自基板102之雜質影響的目的而形成。就緩衝層104而言，可例示有摻雜雜質或沒有摻雜雜質的InP層、InGaAs層、或InAlAs層、或該等之積層。此時，InP層、InGaAs層、或InAlAs層例如係使用以有機金屬氣體作為原料氣體的MOCVD法(有機金屬氣相成長法)而形成。
第1半導體層106為格子整合或擬似格子整合於InP的不包含砷的3-5族化合物。另外，第1半導體層106亦可不包含鋁。藉由不包含鋁，在氧化第2半導體層108而形成氧化層110時，第1半導體層106不被氧化。再者，第1半導體層106可以電子親和力比InP更大。藉由增大電子親和力，而可縮小形成於第1半導體層106與氧化層110間之界面的界面準位之深度。結果即可提昇裝置之性能。
第1半導體層106係可作為電子裝置之功能層而運作，例如可為形成有MISFET之通道的通道層。就第1半導體層106而言，可例示InP層。第1半導體層106亦可摻雜雜質，亦可沒有摻雜雜質。第1半導體層106例如可以使用以有機金屬氣體作為原料氣體的MOCVD法而形 成。
又，亦可於緩衝層104與第1半導體層106之間，形成其他半導體層。就包含砷的半導體層而言，例如可例示InGaAs層。其他半導體層例如可為MISFET的通道層，或也可藉由其他半導體層和第1半導體層106而形成通道層。此時，通道可形成於其他半導體層與第1半導體層106間的界面，而遠離形成於比第1半導體層106更上層的氧化層110的界面。藉由使通道遠離與氧化層110間的界面，可避免存在於半導體-絕緣體界面的界面準位之影響，而提昇裝置性能。
第2半導體層108係鄰接第1半導體層106而形成。第2半導體層108可為格子整合或擬似格子整合於InP的3-5族化合物之半導體層，第2半導體層108亦可為相對於第1半導體層106進行選擇性氧化者。第2半導體層108可包含鋁，具體而言，可為Inx Al1-X As(0<x<1)。但較好為鋁相對於銦為50%以上。
氧化層110係鄰接於第1半導體層106而形成，第2半導體層108之至少一部份係相對於第1半導體層106而選擇性氧化後形成。第2半導體層108之選擇性氧化，例如於第2半導體層108之上，露出成為氧化層110的氧化區域，可藉由形成覆蓋其他非氧化區域的遮罩而實施。另外，氧化層110係將形成於第1半導體層106與控制電極112之間的控制電極予以絕緣的絕緣層，亦即於MOSFET的情形亦可為閘極絕緣層。或著，亦可為比第1半導體層 106更埋入基板102側所形成的埋入氧化層。當形成氧化層110作為埋入氧化層時，可形成雙閘極構造的MOSFET。
氧化層110之組成因係氧化第2半導體層108而形成，故其組成可因應第2半導體層108之組成而定。就第2半導體層108之氧化方法而言，例如可例示濕化(wet)法。當藉由500℃以上之處理條件下的濕化法而氧化第2半導體層108形成氧化層110時，可將界面準位之密度減少為1012 左右。
控制電極112係形成於氧化層110上，且將形成在第1半導體層106的通道施加電場。控制電極112例如可作為MISFET之閘極電極而發揮功能。就控制電極112而言，例如可例示任意之金屬、多晶矽(polysilicon)、金屬矽化物等。控制電極112係於形成有氧化後之第2半導體層108的氧化層110之開口領域118形成。
歐姆層114係歐姆接合輸出入電極116。歐姆層114係形成於與氧化層110同一層的第2半導體層108之殘存有非氧化部區域120的上層。歐姆層114係在形成氧化物110的部分有開口區域118。歐姆層114亦可為格子整合或擬似格子整合於InP且不包含鋁的3-5族化合物半導體層。歐姆層114可摻雜為p型亦可為n型。
輸出入電極116係形成為位於比歐姆層114更上層的一對電極。輸出入116係供給於通道流動的電流。輸出入電極116例如作為MISFET的源極或汲極電極之功能。就輸出入電極116而言，例如可例示鎳、白金、金等、重度 摻雜的多晶矽、金屬矽化物等。
又，於上述說明中，雖以半導體裝置100進行說明，但亦可將基板102、緩衝層104、第1半導體層106、以及第2半導體層108視為一個半導體基板。如上所述的半導體基板可任意氧化第2半導體層108而形成控制電極氧化層，而可迅速地製造MOSFET等裝置。於半導體基板中緩衝層104並非必須，第1半導體層106自身亦可為基板102。
另外，於前述說明中，雖以MOSFET作為半導體裝置100之例示而進行說明，但亦可為其他的電子裝置。例如半導體裝置100亦可為將第2半導體層108氧化形成的氧化層110以控制電極112以及第1半導體層106挾持的電容器。
於第2圖至第5圖表示半導體裝置100之製造過程中的剖面例。如第2圖所示，準備具有緩衝層104及第1半導體層106的基板102。緩衝層104及第1半導體層106矽例如藉由使用MOCVD法的磊晶成長而形成。
如第3圖所示，係於比第1半導體層106更上層形成第2半導體層108。第2半導體層108，例如可藉由MOCVD法而形成。第2半導體層108亦可被摻雜為p形或n形。
如第4圖所示，在形成覆蓋第2半導體層108的歐姆層114後，於歐姆層114形成開口部，使第2半導體層108於開口部之底面露出。且如第5圖所示，以歐姆層114作為遮罩，而氧化於開口部露出的第2半導體層108。氧化係相對於第1半導體層106而選擇性地於第2半導體層108 上實施。另外，氧化係於歐姆層114之開口部選擇性地於第2半導體層108上實施。且藉由第2半導體層108之氧化而形成氧化層110。
於第2半導體層108含有鋁，相對地，於第1半導體層106及歐姆層114不包含鋁。因此，第1半導體層106及歐姆層114不會被氧化，氧化係在第2半導體層108選擇性地且對於開口部自我整合地實施。藉此，可簡單地形成氧化層110。此時的氧化處理可藉由使露出於開口部的第2半導體層108曝露於氧化環境下而實施。
之後，藉由導電膜的形成及圖案化而形成控制電極112以及輸出入電極116。於是，可以製造如第1圖所示的半導體裝置100。
依據如上所述的半導體裝置100，由於係選擇性地氧化第2半導體層108而形成氧化層110，故可簡單地製造MOSFET。另外，由於氧化可以利用濕化法，故可降低界面準位，而可形成實用的化合物半導體MOSFET。
(實驗例)
於未摻雜雜質的InP基板之(100)面上形成10nm的InAlAs，之後，將InAlAs層選擇性地氧化以形成絕緣膜。氧化係使用在525℃之處理溫度的濕化法。於絕緣膜上藉由蒸鍍法形成鋁電極而作為實驗樣本。
第6圖係表示實驗樣本之電流電壓特性。可以確認已實施濕化氧化45分鐘後的樣本有良好的絕緣性。而在作為比較例而僅實施濕化氧化30分鐘的樣本，則可確認絕緣性 的降低。且於作為比較例而未實施濕化氧化的樣本中，可確認絕緣性更為降低。
第7圖係顯示實施了45分鐘濕化氧化的樣本之電容電壓特性。可確認相對於電壓變化，電容變化是在5kHz至1MHz的範圍內。亦即，於絕緣層之下部的InP層係形成有反轉層，而可確認其係動作為MOS。藉由電導法評估界面準位之結果，可以測得1012 左右之界面準位。
100‧‧‧半導體裝置
102‧‧‧基板
104‧‧‧緩衝層
106‧‧‧第1半導體層
108‧‧‧第2半導體層
110‧‧‧氧化層
112‧‧‧控制電極
114‧‧‧歐姆層
116‧‧‧輸出入電極
118‧‧‧開口區域
120‧‧‧區域
第1圖係顯示本實施形態之半導體裝置100的剖面例。
第2圖係顯示半導體裝置100之製造過程中的剖面例。
第3圖係顯示半導體裝置100之製造過程中的剖面例。
第4圖係顯示半導體裝置100之製造過程中的剖面例。
第5圖係顯示半導體裝置100之製造過程中的剖面例。
第6圖係顯示實驗樣本之電流電壓特性。
第7圖係表示已實施濕化氧化45分鐘的樣本之電容電壓特性。
100‧‧‧半導體裝置
102‧‧‧基板
104‧‧‧緩衝層
106‧‧‧第1半導體層
108‧‧‧第2半導體層
110‧‧‧氧化層
112‧‧‧控制電極
114‧‧‧歐姆層
116‧‧‧輸出入電極
118‧‧‧開口區域
120‧‧‧區域

Claims (10)

  1. 一種半導體裝置，係具有：第1半導體層，格子整合或擬似格子整合於InP且不包含砷的3-5族化合物；第2半導體層，鄰接於前述第1半導體層而形成，且格子整合或擬似格子整合於InP的3-5族化合物；歐姆層，覆蓋前述第2半導體層而形成，且具有開口部；氧化層，將前述第2半導體層在前述開口部露出的部分相對於前述第1半導體層進行選擇性的氧化而形成；以及控制電極，在形成於前述第1半導體層的通道施加電場；在前述歐姆層上形成前述開口部的階段之後，不對前述第2半導體層進行蝕刻，形成前述氧化層。
  2. 如申請專利範圍第1項之半導體裝置，其中，前述氧化層為形成於前述第1半導體層與前述控制電極之間的控制電極絕緣層。
  3. 如申請專利範圍第1項或第2項之半導體裝置，其係進一步具有：在與前述氧化層同一的層，殘留有前述第2半導體層的非氧化部；前述歐姆層，為形成於比前述第2半導體層之前述非氧化部更上層的歐姆層，且係於形成有前述氧化 層的部分具有開口部；以及一對輸出入電極，形成於比前述歐姆層更上層，且供給於前述通道流動之電流。
  4. 如申請專利範圍第3項之半導體裝置，其中，前述控制電極係形成於前述開口部之內部的前述氧化層之上。
  5. 如申請專利範圍第3項之半導體裝置，其中，前述歐姆層係格子整合或擬似格子整合於InP，且不含鋁的3-5族化合物半導體層。
  6. 如申請專利範圍第5項之半導體裝置，其中，前述歐姆層係被摻雜為p型或n型。
  7. 一種半導體裝置之製造方法，係具有：基板準備階段，準備一種半導體基板，其係具有：第1半導體層，為格子整合或擬似格子整合於InP且不包含砷的3-5族化合物；以及第2半導體層，為鄰接於前述第1半導體層而形成，且格子整合或擬似格子整合於InP的3-5族化合物；形成將前述第2半導體層覆蓋之歐姆層的階段；於前述歐姆層形成開口部，且於前述開口部之底面露出前述第2半導體層的階段；氧化階段，在形成前述開口部並將前述第2半導體層露出的階段之後，不對前述第2半導體層進行蝕刻，將前述第2半導體層相對於前述第1半導體層進行選擇性氧化而形成氧化層；以及 控制電極形成階段，在比於前述氧化階段所形成的前述氧化層更上層形成控制電極。
  8. 如申請專利範圍第7項之半導體裝置之製造方法，其中，前述氧化階段係以前述歐姆層作為遮罩而使於前述開口部露出的前述第2半導體層曝露於氧化環境下，藉此使前述氧化層自我整合地形成於前述遮罩的階段。
  9. 如申請專利範圍第7項或第8項之半導體裝置之製造方法，其中，前述歐姆層係格子整合或擬似格子整合於InP，且不含鋁的3-5族化合物之p型半導體層或n型半導體層。
  10. 如申請專利範圍第7項或第8項的半導體裝置之製造方法，其中，前述氧化階段係藉由濕化氧化法而形成前述氧化層的階段。
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US20110018033A1 (en) 2011-01-27
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