WO2009048604A2 - Robust multi-layer wiring elements and assemblies with embedded microelectronic elements - Google Patents

Robust multi-layer wiring elements and assemblies with embedded microelectronic elements Download PDF

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Publication number
WO2009048604A2
WO2009048604A2 PCT/US2008/011632 US2008011632W WO2009048604A2 WO 2009048604 A2 WO2009048604 A2 WO 2009048604A2 US 2008011632 W US2008011632 W US 2008011632W WO 2009048604 A2 WO2009048604 A2 WO 2009048604A2
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WO
WIPO (PCT)
Prior art keywords
metal layer
metal
conductive protrusions
dielectric layer
conductive
Prior art date
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Ceased
Application number
PCT/US2008/011632
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English (en)
French (fr)
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WO2009048604A3 (en
Inventor
Belgacem Haba
Vage Oganesian
Kimitaka Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
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Publication date
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Priority to JP2010528888A priority Critical patent/JP2011501410A/ja
Priority to EP08837045A priority patent/EP2213148A4/en
Publication of WO2009048604A2 publication Critical patent/WO2009048604A2/en
Publication of WO2009048604A3 publication Critical patent/WO2009048604A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0361—Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0382—Continuously deformed conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

  • a multiple wiring layer interconnect element having at least one of an active or passive component incorporated therein can include a dielectric layer having a top face and a bottom face remote from the top face.
  • a first metal layer can define a plane extending along the bottom face and a second metal layer can extend along the top face.
  • At least one of the first and second metal layers can include a plurality of conductive traces.
  • a plurality of conductive protrusions can extend from the plane upwardly through the dielectric layer.
  • the at least one of an active or passive component can be disposed between the first and second metal layers .
  • the component can have a plurality of terminals confronting the second metal layer and separated from the second metal layer by the dielectric layer.
  • the method as set forth herein can include after forming the plated features, patterning the first and second metal layers to form wiring patterns.
  • the third metal layer can fill the recesses to form solid conductive protrusions.
  • the third metal layer can coat the inner walls of the recesses to form hollow conductive protrusions.
  • the conductive protrusions can include solid conductive protrusions.
  • the hollow conductive protrusions can have continuous metal surfaces extending away from the plane.
  • the first metal layer can include the planar portions and the hollow conductive protrusions can extend continuously away from the planar portions.
  • the hollow conductive protrusions can have a frustoconical shape.
  • FIGS. l(a) through 1 (g) are sectional views illustrating stages in a method of fabricating a multi-layer wiring element such as a circuit panel having multiple layers of wiring patterns, in accordance with an embodiment of the invention.
  • FIG. 3 (a) is a sectional view illustrating a particular example of a multi-layer wiring element fabricated in accordance with the embodiment illustrated in FIGS. l(a) through 1 (g) .
  • FIG. 14 is a sectional view illustrating a stacked arrangement including a plurality of microelectronic assemblies such as shown in FIG. 12. DETAILED DESCRIPTION
  • the dielectric layer 116 may have a rough surface or smooth surface prior to lamination of the metal layer 118 thereto.
  • the surface roughness of particular dielectric materials can vary widely. Certain dielectric materials such as particular pre-preg type layers can have a surface roughness ranging between about 500 nm and 700 nm prior to laminating the metal layer thereto.
  • a completed interconnect element 130 illustrated in FIG. 1 (d) , includes conductive traces 132, 134 exposed at a bottom surface 116a and a top surface 116b of the dielectric layer 116. Some of the conductive traces 132 exposed at the bottom surface 116a conductively connect with some of the metal posts 112. Some of the metal posts, in turn, are conductively connected to some of the wiring patterns 134, e.g., conductive traces exposed at the top surface 116b through the connectors 128.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
PCT/US2008/011632 2007-10-10 2008-10-08 Robust multi-layer wiring elements and assemblies with embedded microelectronic elements Ceased WO2009048604A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010528888A JP2011501410A (ja) 2007-10-10 2008-10-08 頑健な多層配線要素および埋設された超小型電子素子とのアセンブリ
EP08837045A EP2213148A4 (en) 2007-10-10 2008-10-08 ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES WITH EMBEDDED MICROELECTRONIC ELEMENTS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99856407P 2007-10-10 2007-10-10
US60/998,564 2007-10-10

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WO2009048604A2 true WO2009048604A2 (en) 2009-04-16
WO2009048604A3 WO2009048604A3 (en) 2009-09-24

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PCT/US2008/011632 Ceased WO2009048604A2 (en) 2007-10-10 2008-10-08 Robust multi-layer wiring elements and assemblies with embedded microelectronic elements

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US (2) US20090115047A1 (enExample)
EP (1) EP2213148A4 (enExample)
JP (1) JP2011501410A (enExample)
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WO (1) WO2009048604A2 (enExample)

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JP2011501410A (ja) 2011-01-06
EP2213148A2 (en) 2010-08-04
US20090115047A1 (en) 2009-05-07
US10032646B2 (en) 2018-07-24
EP2213148A4 (en) 2011-09-07
KR101572600B1 (ko) 2015-11-27
US20170018440A1 (en) 2017-01-19
WO2009048604A3 (en) 2009-09-24
KR20100086472A (ko) 2010-07-30

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