Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/8506—Containers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/855—Optical field-shaping means, e.g. lenses
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
  • H10H20/036—Manufacture or treatment of packages
  • H10H20/0363—Manufacture or treatment of packages of optical field-shaping means
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
  • H10H20/841—Reflective coatings, e.g. dielectric Bragg reflectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/855—Optical field-shaping means, e.g. lenses
  • H10H20/856—Reflecting means
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations

Definitions

• the invention relates to an optoelectronic semiconductor module and to a method for producing an optoelectronic semiconductor module
• An optoelectronic semiconductor module has a chip carrier on which a light-emitting semiconductor chip is mounted.
• the chip carrier contains, for example, a ceramic material, for example aluminum nitride.
• the chip carrier has a printed conductor structure - -
• the chip carrier has a multilayer structure and has a conductor track structure which runs in places inside the chip carrier.
• the chip carrier is a metal core board.
• a printed conductor structure is achieved which has two printed conductors which overlap and / or intersect in plan view on the main extension plane of the chip carrier and which are electrically insulated from one another.
• the light-emitting semiconductor chip is preferably a light-emitting diode (LED, light emitting diode). Alternatively, it may be an organic light emitting diode (OLED, organic light emitting diode) or a laser diode.
• LED light-emitting diode
• OLED organic light emitting diode
• laser diode a laser diode
• the optoelectronic semiconductor module is described below in conjunction with a light-emitting semiconductor chip.
• a light-receiving semiconductor chip such as a photodiode or a light emitting and receiving semiconductor chip may be used instead of a light emitting one.
• light-emitting or “light-receiving” is understood to mean that the semiconductor chip emits and / or detects electromagnetic radiation in the infrared, visible and / or ultraviolet spectral range.
• the light-emitting semiconductor chip has in particular an active semiconductor layer sequence which has a pn junction, a double heterostructure, a single quantum well or a multiple quantum well structure (MQW) for light generation and / or light reception.
• an active semiconductor layer sequence which has a pn junction, a double heterostructure, a single quantum well or a multiple quantum well structure (MQW) for light generation and / or light reception.
• MQW multiple quantum well structure
• quantum well structure unfolds no significance with regard to the dimensionality of the quantization. It thus includes u. a. Quantum wells, quantum wires and quantum dots and any combination of these structures. Examples of MQW structures are described in the publications WO 01/39282, US 5,831,277, US 6,172,382 Bl and US 5,684,309, the disclosure content of which is hereby incorporated by reference.
• the semiconductor chip is a thin-film semiconductor chip.
• the thin-film semiconductor chip includes a
• An epitaxial growth element which is not the growth substrate on which the active
• the growth substrate of the epitaxial active semiconductor layer sequence is of the epitaxial active Semiconductor layer sequence removed or thinned so that it together with the epitaxial active
• Semiconductor layer sequence alone is not free-bearing, or - the epitaxial active semiconductor layer sequence has a thickness in the range of 20 microns or less, in particular in the range of 10 microns or less.
• the epitaxial growth element is preferably permeable to a radiation emitted by the semiconductor chip.
• the epitaxial active semiconductor layer sequence preferably contains at least one semiconductor layer having at least one surface which has a mixing structure which, in the ideal case, leads to an approximately ergodic distribution of the light in the epitaxial epitaxial layer sequence, i. it has as ergodically stochastic scattering behavior as possible.
• a basic principle of a thin-film light-emitting diode chip is described, for example, in I. Schnitzer et al. , Appl. Phys. Lett. 63 (16), 18 October 1993, pp. 2174-2176, the disclosure content of which is hereby incorporated by reference.
• Examples of thin-film light-emitting diode chips are described in the publications EP 0905797 A2 and WO 02/13281 A1, the disclosure content of which is hereby incorporated by reference.
• a thin-film light-emitting diode chip is, to a good approximation, a Lambert surface radiator and is therefore particularly well suited for use in a headlight.
• the semiconductor chip has a luminescence conversion layer, which is applied to the active semiconductor layer sequence.
• the luminescence conversion layer has at least one phosphor, in particular an inorganic phosphor.
• the phosphor is, for example, yttrium aluminum garnet doped with a rare earth material such as cerium.
• a rare earth material such as cerium.
• Other garnet phosphors and other phosphors such as aluminates and / or orthosilicates are conceivable.
• the luminescence conversion layer converts the wavelength of the active semiconductor layer sequence in a first spectral range emitted light into a second, different from the first spectral range.
• the semiconductor chip emits mixed light which contains unconverted light of the first spectral range (primary radiation) and converted light of the second spectral range (secondary radiation).
• the light emitted by the semiconductor chip with luminescence conversion layer produces a white color impression.
• the cover member has a cover plate and a frame part.
• the cover plate is at least partially transparent to the light emitted and / or received by the semiconductor chip.
• the cover plate is transparent.
• the frame part is opaque to light or at least impermeable to light emitted by the semiconductor chip.
• the cover in particular the cover plate, in one embodiment, a ceramic material and / or a glass material.
• the frame part has a semiconductor material in one embodiment.
• ceramic materials, glass materials and / or semiconductor materials are particularly well suited for headlamp applications in which, for example, often high operating temperatures and, in particular at
• the optoelectronic semiconductor module has a long service life.
• cover elements have ceramic
• the optoelectronic semiconductor module is therefore particularly well suited, for example, for use in a projection apparatus, in particular for displaying information which has, for example, a plurality of pixels.
• An embedding of the semiconductor chip in a potting compound can be dispensed with advantage. Instead, the coupling-out and / or coupling of the light emitted and / or received by the semiconductor chip takes place against air. - -
• a region enclosed by the cover element and the chip carrier and containing the semiconductor chip is free of a potting compound encapsulating the semiconductor chip.
• the efficiency of the decoupling in this way is increased by about 15% in the case of a light-emitting thin-film semiconductor chip, and by about 25% in the case of a semiconductor chip having a luminescence conversion layer, for example, as compared to decoupling into a potting compound.
• the cover plate of the cover is arranged on the side facing away from the chip carrier side of the semiconductor chip.
• the frame part of the cover element surrounds the semiconductor chip laterally.
• the frame part encloses the semiconductor chip in plan view of the chip carrier completely.
• the cover element and the chip carrier completely enclose an interior containing the semiconductor chip.
• the semiconductor chip is protected, for example, against dust and / or moisture.
• the frame part contains at least one breakthrough.
• the semiconductor chip is not completely enclosed laterally in a plan view of the chip carrier.
• the frame part consists of a plurality of individual, spaced-apart sections such as webs and / or posts. In this way, a good dissipation of heat loss, which is generated in the operation of the semiconductor chip is achieved.
• This embodiment is also advantageous if the cover element, the chip carrier and / or optionally an attachment layer, by means of which the cover is connected to the chip carrier, a particular gaseous substance segregates, in which there is a risk that it accumulates in a completely enclosed interior and affects the efficiency and / or life of the semiconductor module.
• the frame part isyogge Mrslos connected to the cover plate and preferably connected at its side remote from the cover plate side with the chip carrier, in particular fixed mechanically stable.
• Adhesive layer - such as an adhesive layer - is made.
• the connection is made without adhesive.
• the cover element preferably has no connecting layer arranged between the frame part and the cover plate. Rather, the cover plate and the frame part border in particular directly to each other. It is, in other words, preferably a cohesive connection between the cover plate and the frame part. In particular, the connection is insoluble, so only by destroying the cover plate and / or the frame part solvable.
• the optoelectronic semiconductor module thus has particularly good optical properties, in particular a high contrast and / or a sharp boundary of the luminous surface.
• the optoelectronic semiconductor module emits light beams during operation which, with the main extension plane of the chip carrier, form an angle of less than or equal to 10 °, preferably less than or equal to 8 °, particularly preferably less than or equal to 6 °.
• Such a flat beam angle are advantageously achieved due to the means of Polge Mrs. connection between the cover plate and frame part particularly low tolerances of the cover.
• the semiconductor module for example, advantageously illuminates a particularly large solid angle range.
• the frame part has at least one oblique side surface facing the semiconductor chip.
• at least one inner surface of the frame part extends at an angle to the main extension plane of the frame part, which deviates from a right angle.
• the main extension plane of the frame part is in particular parallel to the main extension plane of the cover plate. If the side surface is not a flat surface but, for example, a surface of revolution, then the angle between the oblique side surface and the main extension plane is to be understood as the angle which the oblique side surface and the main extension plane enclose in a sectional plane, which also contains the solder on the main extension plane of the frame part.
• the inclined side surface with the main extension plane of the frame part includes an angle of between 40 ° and 70 °, for example between 50 ° and 60 °, preferably between 53 ° and 56 °, more preferably of about 54.7 °.
• the limits of the angular range are included here. In particular, the angle deviates by 0.5 ° or less from 54.7 °.
• the angle is greater than or equal to 80 °.
• the frame may also have a curved side surface facing the semiconductor chip.
• a lateral distance between the oblique or curved side surface and the semiconductor chip decreases in the course of the chip carrier towards the cover plate.
• a lateral distance between an outer edge of the cover plate and the inclined inner surface of the frame part decreases in the course of the cover plate away.
• the oblique or curved side surface in this embodiment shadows a defined portion of the light emitted by the light-emitting semiconductor chip during operation.
• the cover plate adjacent - and in particular to this adjacent edge of the oblique or curved side surface advantageously represents a sharp boundary for the shaded part, a so-called "shutter edge". This is particularly advantageous for the use of the semiconductor module in a headlight, for example in a motor vehicle headlight.
• light emitted by the semiconductor chip which impinges on the inclined inner surface is advantageously not coupled out of the semiconductor module directly or only to a small extent directly through the cover plate. This is particularly advantageous when the semiconductor module is used in a headlight. For example, a high homogeneity of the luminance over the light-emitting surface of the semiconductor module is achieved in this way.
• a lateral distance between the oblique or curved side surface and the semiconductor chip increases in the course of the chip carrier to the cover plate.
• the optoelectronic semiconductor module is particularly well suited for general lighting, for example for use in luminaires, in particular for illuminating interior spaces such as offices or aircraft cabins.
• the thermal expansion coefficients of the cover plate and the frame part and / or the thermal expansion coefficients of the frame part and the chip carrier are matched to one another.
• Thermal expansion coefficients of the cover plate, the frame part and the chip carrier by 2 x ICT 6 l / ° C or less, preferably by 1.5 x 10 ⁇ 6 1 / ° C or less.
• the coefficient of thermal expansion indicates by what amount in relation to the total length, a solid body increases or decreases with a temperature change of one degree Kelvin or one degree Celsius.
• coordinated thermal expansion coefficients reduce mechanical stresses in the event of temperature fluctuations, so that the cover element and the optoelectronic semiconductor module have a long service life even with frequent temperature changes. This is particularly advantageous for use in automotive lighting, for example.
• the cover plate is provided with an antireflection layer.
• the antireflection layer reduces the reflection coefficient of the cover plate for light emitted by the semiconductor chip.
• the cover plate is on the semiconductor chip facing and / or on the Side facing away from the semiconductor chip provided with the anti-reflection layer.
• the frame part is provided with an electrical insulation layer on a side facing away from the cover plate and in particular facing the chip carrier.
• the electrical insulation layer advantageously electrically insulates the frame part from at least one conductor track of the conductor track structure of the chip carrier.
• the cover plate is provided in places with a reflective and / or absorbent layer.
• the reflective and / or absorbing layer reflects or absorbs light emitted by the semiconductor chip and thus advantageously shadows a further defined part of the light emitted by the light-emitting semiconductor chip during operation.
• the reflective and / or absorbing layer transmits less than 15%, preferably less than 5%, more preferably less than 2% of the
• the reflective and / or absorbing layer contains, for example, a tantalum nitride such as TaN, silicon and / or chromium or consists of one of these materials.
• the cover plate on a Strahlformungseiement is preferably integrated with the cover plate, in particular the cover plate has a projection and / or a recess.
• the cover plate includes a lens element and / or a prism element, at which light passing through the cover plate is refracted and / or reflected.
• the cover plate is provided with a phosphor.
• phosphors for example, in connection with the
• the phosphor can be applied to the cover plate, for example by means of a vapor deposition or a powder coating method.
• the phosphor or another phosphor can be contained in the cover plate.
• the phosphor or the further phosphor is melted into the cover plate.
• Soldered chip carrier In particular, in the case of a frame part which completely surrounds the semiconductor chip in a plan view of its main extension plane, a special one becomes possible - -
• the frame part contains silicon.
• the cover plate contains
• Borosilicate glass which is in particular a float glass.
• the borosilicate glass has about 80-81% SiO 2 , about 13% B 2 O 3 , about 2-2.5% Al 2 O 3 and about 4% Na 2 O and / or K 2 O.
• Such borosilicate glass is available, for example, under the trade names "Pyrex” or "Borofloat 33" (BF33).
• the cover plate borosilicate glass and the frame part of silicon.
• the thermal expansion coefficients of borosilicate glass and silicon differ only slightly from each other, so they are coordinated.
• the chip carrier contains aluminum nitride.
• the thermal expansion coefficient of aluminum nitride is based on both the thermal expansion coefficient of
• Borosilicate glass and matched to the coefficients of thermal expansion of silicon are matched to the coefficients of thermal expansion of silicon.
• the values of the thermal expansion coefficients of borosilicate glass, silicon and aluminum nitride differ by 2 ⁇ 10 -6 1 / ° C or less, in particular by 1.5 ⁇ 10 -6 1 / ° C or less.
• the optoelectronic semiconductor module is contained for example in a headlight, in particular a motor vehicle headlight.
• the optoelectronic semiconductor module is contained in a projection device.
• it is contained in a luminaire, in particular for general lighting, such as Lighting an interior such as an office space or an aircraft cabin, is provided.
• a method for producing a cover element for an optoelectronic semiconductor module comprises the steps:
• the opening has, for example, a circular, elliptical, rectangular or square
• Cross-sectional area is completely contained in the portion of the frame wafer, which forms the frame part.
• the opening has a strip-shaped cross-section.
• the length preferably has a value greater than or equal to 2, more preferably by a factor greater than or equal to 5 higher value than the width.
• the portion of the frame wafer forming the frame part contains only a portion of the opening.
• the frame part has two spaced, disjoint sections such as webs.
• At least one of the sections has a common edge with the cover plate.
• a particularly accurate positioning of the cover plate and the frame part is achieved.
• a cover member is produced in this way, which has particularly low manufacturing tolerances. In this way, for example, a cover with particularly small dimensions is achieved.
• a plurality of openings are made in the frame wafer, and the composite of frame wafers and cover plate wafers are cut by cuts through the composite into a plurality of cover elements.
• the separation of the covering element from the composite of frame wafer and cover plate wafer preferably takes place by means of cuts through the composite, the cuts separating the section of the cover plate wafer which forms the cover plate of the cover element and separating the section of the frame wafer which at least partially contains the opening and forms with the cover plate connected frame part.
• the cuts are preferably produced by means of a sawing process, a laser separation process or a wet or dry chemical etching process.
• Producing the non-fuss connection of the frame wafer with the cover plate wafer in one embodiment comprises an anodic bonding process.
• the frame wafer and the cover plate wafer are brought into mechanical contact and it
• An electric voltage is applied between the frame wafer and the cover plate wafer.
• the application of the electrical voltage is preferably carried out at a temperature higher than room temperature.
• At least the surface of the frame wafer which is brought into mechanical contact with the cover plate wafer and / or the surface of the cover plate wafer which is brought into mechanical contact with the frame wafer is preferably polished.
• the frame wafer comprises or consists of silicon.
• the frame wafer is a monocrystalline silicon wafer in (100) orientation, which is preferably polished on both sides.
• the frame wafer has a diameter of 6 inches or 8 inches.
• the cover plate wafer comprises, for example, a ceramic material and / or a glass material, in particular borosilicate glass, or consists thereof.
• the glass material contains sodium oxide.
• Cover plate wafer containing sodium oxide and a frame wafer containing silicon is advantageously produced in the anodic bonding process a particularly stable mechanical connection.
• the production of the opening comprises a wet and / or dry-chemical etching process, for example by means of potassium hydroxide and / or tetramethylammonium hydroxide, and / or a sandblasting process, for example by means of aluminum oxide powder.
• a structured mask layer is preferably applied to the frame wafer, which defines the opening, and through which the etching and / or sandblasting he follows.
• Suitable materials for the structured mask layer are, for example, lacquers, metals, nitrides such as silicon nitride and / or oxides such as silicon oxide. Nitrides and oxides are particularly suitable for etching processes.
• the etching process or the sandblasting process is, in particular, an anisotropic process.
• the patterned mask layer may be removed after making the opening. Alternatively, it may also remain on the frame wafer. For example, in the
• Cover part contained portion of the mask layer is the insulating layer.
• the opening is preferably produced, in particular by means of the anisotropic etching and / or sandblasting method, in such a way that it has oblique side faces or at least one oblique side face.
• the oblique side surface (s) include an angle with the main extension plane of the frame wafer that deviates by 0.5 ° or less from 54.7 °.
• an antireflection layer is applied to the cover plate wafer.
• the antireflection layer is applied to the side of the cover plate wafer remote from the frame wafer. Additionally or alternatively, it can also be applied to the side of the cover plate wafer facing the frame wafer. In this case, at a
• the frame wafer Design also coated the frame wafer with the antireflection coating.
• one or both major surfaces of the cover plate wafer are provided with the antireflective layer prior to bonding cover plate wafers and frame wafers.
• the antireflection layer is applied to the first main surface of the cover plate wafer, which is connected to the frame wafer in a subsequent method step, it is preferably applied in a structured manner on at least this main surface. More preferably, the method is performed such that those locations of the first major surface that are brought into mechanical contact with frame wafers are uncovered by the antireflective layer.
• the antireflection layer is applied on the region of the first main surface which overlaps in the connection plane of cover plate wafer and frame wafer with the opening of the frame wafer.
• Embodiment is particularly advantageous for an embodiment of the cover, wherein the opening tapers in the course of the cover plate away.
• the structured application comprises, for example, a photolithographic process, for example using a negative photoresist.
• the main surface is first provided with a structured photoresist layer, then the antireflection layer is applied to the cover plate wafer and the photoresist layer, and subsequently the photoresist layer with the part of the antireflection layer applied thereon is removed again.
• the portion of the cover plate wafer, which forms the cover plate provided in places before or after the separation of the cover with a reflective and / or absorbent layer.
• the portion of the Abdeckplattenwafers, which forms the cover plate a beam-shaping element.
• a method for producing an optoelectronic semiconductor module additionally comprises the steps of: mounting a light emitting and / or receiving semiconductor chip on a chip carrier; - Attaching the frame part to the chip carrier, such that the frame part laterally surrounds the semiconductor chip and the semiconductor chip between the cover plate and the chip carrier is arranged.
• FIGS. 1A- 1 show schematic plan views of different variants of cover elements
• Figures 8-12 schematic cross sections of various stages of a method for producing a
• FIG. 14 shows a schematic cross section through an optoelectronic semiconductor module according to a third exemplary embodiment
• FIG. 15 schematic plan view of the optoelectronic semiconductor module of FIG. 14,
• FIG. 16B schematic top view of the cover element of FIG. 16A
• FIG. 17 schematic cross section through an optoelectronic semiconductor module according to a fourth exemplary embodiment
• FIG. 18 shows a schematic cross section through an optoelectronic semiconductor module according to a fifth exemplary embodiment
• FIG. 17 schematic cross section through an optoelectronic semiconductor module according to a fourth exemplary embodiment
• FIG. 18 shows a schematic cross section through an optoelectronic semiconductor module according to a fifth exemplary embodiment
• FIG. 19 diagram with thermal expansion coefficients of different materials.
• FIGS. 1 to 5 show various stages of a first exemplary embodiment of a method for producing a cover element for an optoelectronic semiconductor module in schematic cross sections.
• FIG. 1 shows a first method step of the method.
• An opaque frame wafer 1 is provided which is coated with a mask layer 2 of silicon oxide or silicon nitride.
• the frame wafer in the present embodiment is a double-sided polished Si wafer in (100) orientation with a diameter of 6 inches or 8 inches.
• the mask layer 2 is applied in a structured manner, in the present case has recesses 210, which in plan view the shape of a Have rectangles.
• the mask layer 2 is applied over the entire surface.
• the mask layer 2 is applied, for example, by means of a thermal oxidation process or by means of a plasma-assisted evaporation process, such as physical vapor deposition (PVD).
• openings 110 are subsequently produced in the frame wafer 1.
• the openings are created by etching the frame wafer 1 with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) through the recesses 210 of the mask layer 2.
• KOH potassium hydroxide
• TMAH tetramethylammonium hydroxide
• the side surfaces 111 of the openings 110 enclose an angle ⁇ of about 54.7 ° with the main extension plane of the frame wafer 1 in this etching process.
• the main extension plane of the frame wafer 1 is at least in
• a possible deviation of the angle ⁇ from a value of 54.7 ° is usually based essentially on a tilting of the main surfaces 101, 102 of the frame wafer 1 to ⁇ 100 > Level.
• the tilt preferably has a value of 0.5 ° or less, so that the angle ⁇ preferably deviates by 0.5 ° or less from 54.7 °.
• the openings 110 taper in the direction from the first main surface 101 to the second main surface 102 of the frame wafer.
• the mask layer 2 is removed from the frame wafer 1, for - -
• the patterned mask layer 2 may also remain as an insulating layer on the first main surface 101 of the frame wafer 1.
• a first main surface 301 of a cover plate wafer 3 is subsequently connected to the first main surface 101 of the frame wafer 1 by means of an anodic bonding process.
• the cover plate wafer 3 is presently transparent and consists of a borosilicate float glass, in particular BF33, which contains sodium oxide.
• the first main surface 101 of the frame wafer 1 and the first main surface 301 of the cover plate wafer 3 are brought into mechanical contact at a temperature increased to room temperature, for example, greater than or equal to 350 0 C and / or less than or equal to 500 0 C.
• the first main surface 101 of the frame wafer 1 and the first main surface 301 of the cover plate wafer 3 directly adjoin one another. They are included in particular in a common connection level.
• the electrical voltage has, for example, a value of greater than or equal to 100 V and / or less than or equal to 5 kV. For example, it has a value between 500 V and 2500 V, with the limits included.
• the cover plate wafer 3 is coated on both sides with an antireflection layer 4, such as a TaN, Si or Cr layer (see FIG. 4).
• an antireflection layer 4 such as a TaN, Si or Cr layer (see FIG. 4).
• the coating of the first main surface 301 of the cover plate wafer 3 takes place through the openings 110 of the frame wafer 1.
• the cover plate wafer 3 may be coated with the antireflection film 4 prior to bonding to the frame wafer 1.
• the cover plate wafer 3 may be coated with the antireflection film 4 prior to bonding to the frame wafer 1.
• the cover plate wafer 3 may be coated with the antireflection film 4 prior to bonding to the frame wafer 1.
• only those points of the first main surface 301 are coated, which overlap in the connecting plane with the openings 110, as described in the general part.
• cover plate wafer 3 and frame wafer 1 is singulated into individual cover elements 5. This is done with cuts 6 through the composite, such as sawing or laser cutting.
• the composite is preferably arranged on a sawing foil 6, not shown in FIG. 5, which is tensioned in particular in a holding frame.
• Each of the separated cover elements 5 has a
• the cover plate 300 is a part of the cover plate wafer 3.
• the frame part 100 is a part of the frame wafer 1, which one of the openings 110 at least partially, but in the present case completely contains.
• Figure 6 shows a stage of a variant of the method according to the first embodiment, which corresponds to the stage of Figure 3, in a schematic cross section.
• the variant of the method instead of the first main surface 101 of the frame wafer 1, its second main surface 102 is connected to the cover plate wafer 3. In this way, cover elements 5 are achieved, in which the
• FIGS. 7A-7C Various variants of the geometry of openings 110 are shown in schematic plan views of the cover plates 300 of cover elements 5 in FIGS. 7A-7C.
• FIG. 7A shows a cover element 5 with a rectangular or square base.
• the cover plate 300 and the frame part 100 in plan view of their main extension planes have a rectangular or square base and are preferably arranged congruently, that is arranged such that their outer edges coincide in plan view.
• the opening 110 has a circular or elliptical cross-sectional area.
• the cross-sectional area decreases in the course of the cover plate 300 away.
• the opening 110 thus has the shape of a truncated cone.
• the cover plate 300 has a rectangular base area.
• the frame part 100 has two openings 120. More precisely, it consists of two - -
• Figure 7C shows a schematic plan view of the cover 5 of Figure 5 according to the first embodiment.
• FIGS. 8 to 12 A second exemplary embodiment of a method for producing a cover element is shown in schematic cross sections in FIGS. 8 to 12.
• first the frame wafer 1 and the cover plate wafer 3 are joined without bonding (see FIG. 8).
• Thephilge Anlagenvant connection is made, for example, as in the first embodiment by means of anodic bonding.
• the production of the openings 110 in the frame wafer 1 takes place only subsequently on the connection of the frame wafer 1 and the cover plate wafer 3.
• a structured mask layer 2 is applied to the first main surface 101 of the frame wafer 1 (see FIG 9).
• the frame wafer 1 is etched through the recesses 210, for example again by means of KOH or TMAH, whereby the openings 110 are formed (see FIG. 10).
• the optional removal of the mask layer 2 takes place analogously to the first exemplary embodiment.
• the composite of frame wafer 1 and cover plate wafer 3 is provided on both sides with an antireflection layer 4 (see FIG. 11) and singulated into a plurality of cover elements 5 (see FIG. 12).
• FIG. 13 shows a method step of an exemplary embodiment of a method for producing an optoelectronic semiconductor module in a schematic sectional representation.
• the stage of the method shown in FIG. 13 follows the separation of the cover element 5 from the composite of frame wafer 1 and cover plate wafer 3, for example according to the first exemplary embodiment (see FIG. 5) or the second exemplary embodiment (see FIG. 12).
• the cover is still arranged on the sawing foil 6 after separation.
• the cover element 5 is lifted at least in places from the sawing foil 6 by means of cutout tips 8, as a result of which the adhesion between cover element 5 and sawing foil 6 is advantageously reduced.
• the covering element is lifted off the sawing foil 6 by means of a suction needle 7.
• the cover plate 300 of the sawing foil 3 faces.
• the suction needle 7 engages in this embodiment for lifting the cover from the side of the frame member 100 ago in the opening 110 a.
• the cover is transferred from the suction needle 7 to another tool, which engages the cover 5 from the side of the cover plate 300 ago it subsequently, for example, with a chip carrier 9 (see Figure 14) to connect.
• FIG. 14 shows a schematic cross section of an optoelectronic semiconductor module according to a third exemplary embodiment.
• the optoelectronic semiconductor module includes a cover 5 according to the second embodiment.
• the cover 5 is connected to the chip carrier 9. For example, it is soldered to this.
• the opening 110 represents an interior which is completely enclosed by the cover element 5 and the chip carrier 9.
• a light-emitting semiconductor chip 10 which in the present case is a thin-film light-emitting diode chip, is mounted on the chip carrier 9 and electrically contacted with conductor tracks of a conductor track structure (not shown) of the chip carrier 9.
• the chip carrier 9 has, for example, aluminum nitride.
• AlN aluminum nitride
• Si silicon
• BF33 borosilicate glass
• the thermal expansion coefficients of the cover plate 300 (BF33), the frame part 100 (Si) and the chip carrier 9 (AlN) are matched.
• the difference (diff) between the thermal expansion coefficients is very low at less than 1.5 x 10 -6 / ° C.
• the frame part 100 completely encloses the semiconductor chip 10 in a top view of the chip carrier 9.
• the cross-sectional area of the opening 110 decreases in the direction from the chip carrier 9 toward the cover plate 300.
• a lateral distance between the semiconductor chip 10 and one, in particular each, of the side surfaces 111 of the opening 110 decreases in the direction from the chip carrier 9 toward the cover plate 300.
• the side surfaces 111 selectively shadow a defined part of the light emitted by the semiconductor chip 10 during operation.
• a shadowed light beam IIA is shown by way of example in the semiconductor module according to FIG. 16. In particular, light is shaded, which is emitted from the semiconductor chip 10 at an angle to the main extension plane of the chip carrier 9, which is smaller than a critical angle ß.
• the interior contains, in addition to the light-emitting semiconductor chip 10, a further electronic component 12.
• a further electronic component 12 for example, this is a
• the semiconductor chip 10 is not placed centrally between two side walls 111 of the opening 110, so that two different critical angles ⁇ , namely the critical angles ⁇ ⁇ and ⁇ 2 , occur, depending on whether the semiconductor chip 10 Light in the direction of 2 ) emitted from the side wall ( ⁇ x) or the opposite side wall ( 2 ) arranged closer to the semiconductor chip.
• the frame part is advantageously designed so that the side flanks 303 of the cover plate 300 are not illuminated by the light emitted by the semiconductor chip 10. Instead, the light is coupled out of the semiconductor module by the second main surface 302 of the cover plate 300 facing away from the semiconductor chip. This is exemplified by the light beam IIB in the semiconductor module according to FIG. 16.
• FIG. 15 shows a schematic plan view of the semiconductor module according to the third exemplary embodiment.
• the semiconductor module includes a plurality of light-emitting semiconductor chips 10, in the present case contains five light-emitting semiconductor chips 10, which are arranged together in the opening 110.
• the semiconductor chips 10 are connected for example by means of the bonding wires 15 in series.
• the semiconductor chips 10 are arranged in a row.
• the chip carrier 9 has a width b of 4 mm or less, for example, about 3.6 mm.
• the semiconductor chips 10 have, for example, a width of about 2.1 mm. The width is in this case the dimension transverse to the direction of the row.
• solder barriers 14 on the tracks 13 reduce the risk that solder during soldering over a distributed to large area of the track 13.
• the solder barriers 14 substantially confine the solder to the region of the conductor track 13 covered by the semiconductor chip 10.
• the solder barriers 14 have, for example, a layer of a hydrophobic material, such as a Cr layer, or consist thereof.
• FIGS. 16A and 16B A variant of the optoelectronic semiconductor module according to the third exemplary embodiment is shown schematically in cross section in FIGS. 16A and 16B.
• the semiconductor module according to FIGS. 16A and 16B differs from that of FIGS. 14 and 15 in that a reflective layer 17 is applied in places on the main surface 302 of the cover plate 300 facing away from the semiconductor chip 10 emitted light selectively shaded.
• a reflective layer 17 is applied in places on the main surface 302 of the cover plate 300 facing away from the semiconductor chip 10 emitted light selectively shaded.
• an asymmetrical geometry of the light extraction region of the cover plate 300 is achieved by means of the reflective layer 17, as shown schematically in plan view in FIG. 16B.
• the semiconductor module according to FIGS. 16A and 16B differs from that of FIGS. 14 and 15 in that the chip carrier 9 has a multilayer structure.
• a conductor track 13 contacting the semiconductor chip extends in places inside the chip carrier 9. In this way, a completely circumferential attachment of the frame part 100 to the chip carrier 9 is achieved. An interruption of the attachment in order to lead the electrical connections for the semiconductor chip 10 out of the inner space 110 is advantageously not necessary. The interior is therefore particularly well sealed.
• the conductor track 13 extending inside the chip carrier 9 is led laterally from the cover element 5 back to the front side of the chip carrier 9, on which the semiconductor chip 5 and the cover element 5 are mounted.
• the conductor track is guided onto the rear side opposite the front side, as indicated by dashed lines in FIG. 16A.
• the optoelectronic semiconductor module according to the fourth exemplary embodiment shown schematically in cross section in FIG. 17 has, in addition to the semiconductor modules according to the preceding exemplary embodiments, a beam-shaping element 16, in the present case a lens, in particular a convex lens.
• the beam-shaping element 16 is glued to the cover plate 300, for example.
• the beam-shaping element is embodied as a convex lens element 16 which is integrated with the cover plate.

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• 2007
  • 2007-08-20 DE DE102007039291A patent/DE102007039291A1/de not_active Withdrawn
• 2008
  • 2008-08-06 TW TW097129884A patent/TWI513029B/zh not_active IP Right Cessation
  • 2008-08-11 JP JP2010521295A patent/JP5466641B2/ja not_active Expired - Fee Related
  • 2008-08-11 US US12/673,800 patent/US9564555B2/en not_active Expired - Fee Related
  • 2008-08-11 CN CN2008801038032A patent/CN101785119B/zh not_active Expired - Fee Related
  • 2008-08-11 WO PCT/DE2008/001327 patent/WO2009024125A1/de not_active Ceased
  • 2008-08-11 EP EP08827587.0A patent/EP2188852B1/de not_active Not-in-force
  • 2008-08-11 KR KR1020107006175A patent/KR101501795B1/ko not_active Expired - Fee Related
  • 2008-08-11 CN CN201110400131.5A patent/CN102437269B/zh not_active Expired - Fee Related

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