WO2008155876A1 - Ｓｏｉウェーハの製造方法 - Google Patents

Ｓｏｉウェーハの製造方法 Download PDF

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Publication number
WO2008155876A1
WO2008155876A1 PCT/JP2008/001312 JP2008001312W WO2008155876A1 WO 2008155876 A1 WO2008155876 A1 WO 2008155876A1 JP 2008001312 W JP2008001312 W JP 2008001312W WO 2008155876 A1 WO2008155876 A1 WO 2008155876A1
Authority
WO
WIPO (PCT)
Prior art keywords
soi wafer
manufacturing
soi
wafer manufacturing
layer
Prior art date
Application number
PCT/JP2008/001312
Other languages
English (en)
French (fr)
Inventor
Isao Yokokawa
Nobuhiko Noto
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Priority to CN2008800210341A priority Critical patent/CN101689478B/zh
Priority to US12/451,533 priority patent/US8361888B2/en
Priority to KR1020097026718A priority patent/KR101446517B1/ko
Priority to EP08763912A priority patent/EP2159826A4/en
Publication of WO2008155876A1 publication Critical patent/WO2008155876A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition

Abstract

　本発明は、テラス部に酸化膜を有するＳＯＩウェーハのＳＯＩ層の全面にシリコンエピタキシャル層を形成する工程（ｆ）において、反応ガスにＨＣｌガスを混合することを特徴とするＳＯＩウェーハの製造方法である。これにより、テラス部に酸化膜を有するＳＯＩウェーハのＳＯＩ層上にシリコンエピタキシャル層を簡単に成長させることができ、製造されるＳＯＩウェーハの反りを抑制することができ、また、デバイス製造等といった後の工程においてもパーティクルの発生を低減することができ、さらにそのようなＳＯＩウェーハ製造のコスト削減を図ることができるＳＯＩウェーハの製造方法が提供される。
PCT/JP2008/001312 2007-06-21 2008-05-27 Ｓｏｉウェーハの製造方法 WO2008155876A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2008800210341A CN101689478B (zh) 2007-06-21 2008-05-27 Soi芯片的制造方法
US12/451,533 US8361888B2 (en) 2007-06-21 2008-05-27 Method for manufacturing SOI wafer
KR1020097026718A KR101446517B1 (ko) 2007-06-21 2008-05-27 Ｓｏｉ 웨이퍼의 제조방법
EP08763912A EP2159826A4 (en) 2007-06-21 2008-05-27 PROCESS FOR PRODUCING SOI WAFERS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007164238 2007-06-21
JP2007-164238 2007-06-21

Publications (1)

Publication Number Publication Date
WO2008155876A1 true WO2008155876A1 (ja) 2008-12-24

Family

ID=40156040

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/001312 WO2008155876A1 (ja) 2007-06-21 2008-05-27 Ｓｏｉウェーハの製造方法

Country Status (6)

Country Link
US (1) US8361888B2 (ja)
EP (1) EP2159826A4 (ja)
JP (1) JP5245380B2 (ja)
KR (1) KR101446517B1 (ja)
CN (1) CN101689478B (ja)
WO (1) WO2008155876A1 (ja)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5477277B2 (ja) 2010-12-20 2014-04-23 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR2978868A1 (fr) * 2011-08-01 2013-02-08 Soitec Silicon On Insulator Procede de fabrication d'une structure de type semi-conducteur sur isolant, a "box" epais et couche active fine
FR2984597B1 (fr) * 2011-12-20 2016-07-29 Commissariat Energie Atomique Fabrication d’une structure souple par transfert de couches
JP6200273B2 (ja) 2013-10-17 2017-09-20 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6036732B2 (ja) * 2014-03-18 2016-11-30 信越半導体株式会社 貼り合わせウェーハの製造方法
FR3032555B1 (fr) * 2015-02-10 2018-01-19 Soitec Procede de report d'une couche utile
JP6380245B2 (ja) * 2015-06-15 2018-08-29 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP6447439B2 (ja) * 2015-09-28 2019-01-09 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6473970B2 (ja) * 2015-10-28 2019-02-27 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US10249493B2 (en) * 2015-12-30 2019-04-02 Siltronic Ag Method for depositing a layer on a semiconductor wafer by vapor deposition in a process chamber
US20200135489A1 (en) * 2018-10-31 2020-04-30 Atomera Incorporated Method for making a semiconductor device including a superlattice having nitrogen diffused therein

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321822A (ja) * 1986-07-15 1988-01-29 Nec Corp シリコン気相エピタキシヤル成長方法
JPH021116A (ja) * 1988-03-09 1990-01-05 Tel Sagami Ltd 熱処理装置
JPH10321548A (ja) * 1997-05-15 1998-12-04 Denso Corp 半導体基板の製造方法
JP2000030995A (ja) 1998-07-07 2000-01-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP2000196047A (ja) * 1998-12-25 2000-07-14 Shin Etsu Handotai Co Ltd Ｓｏｉ基板及びその製造方法
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
JP2004281805A (ja) * 2003-03-17 2004-10-07 Sumitomo Mitsubishi Silicon Corp 半導体ウェーハの平坦化処理方法
JP2005340622A (ja) * 2004-05-28 2005-12-08 Sumco Corp Ｓｏｉ基板及びその製造方法
JP2006270039A (ja) 2005-02-28 2006-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法及び貼り合わせウエーハ
JP2008135720A (ja) * 2006-11-27 2008-06-12 Soitec Silicon On Insulator Technologies 表面を改善する方法

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JPH0719737B2 (ja) * 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
JPH04373121A (ja) * 1991-06-21 1992-12-25 Canon Inc 結晶基材の製造方法
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
SG78332A1 (en) * 1998-02-04 2001-02-20 Canon Kk Semiconductor substrate and method of manufacturing the same
TW437078B (en) * 1998-02-18 2001-05-28 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
US6600173B2 (en) * 2000-08-30 2003-07-29 Cornell Research Foundation, Inc. Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US7175709B2 (en) * 2004-05-17 2007-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxy layer and method of forming the same
WO2006092886A1 (ja) * 2005-02-28 2006-09-08 Shin-Etsu Handotai Co., Ltd. 貼り合わせウエーハの製造方法及び貼り合わせウエーハ

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321822A (ja) * 1986-07-15 1988-01-29 Nec Corp シリコン気相エピタキシヤル成長方法
JPH021116A (ja) * 1988-03-09 1990-01-05 Tel Sagami Ltd 熱処理装置
JPH10321548A (ja) * 1997-05-15 1998-12-04 Denso Corp 半導体基板の製造方法
JP2000030995A (ja) 1998-07-07 2000-01-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP2000196047A (ja) * 1998-12-25 2000-07-14 Shin Etsu Handotai Co Ltd Ｓｏｉ基板及びその製造方法
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
JP2004281805A (ja) * 2003-03-17 2004-10-07 Sumitomo Mitsubishi Silicon Corp 半導体ウェーハの平坦化処理方法
JP2005340622A (ja) * 2004-05-28 2005-12-08 Sumco Corp Ｓｏｉ基板及びその製造方法
JP2006270039A (ja) 2005-02-28 2006-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法及び貼り合わせウエーハ
JP2008135720A (ja) * 2006-11-27 2008-06-12 Soitec Silicon On Insulator Technologies 表面を改善する方法

Non-Patent Citations (1)

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Title
See also references of EP2159826A4

Also Published As

Publication number Publication date
JP2009027124A (ja) 2009-02-05
KR101446517B1 (ko) 2014-10-06
CN101689478B (zh) 2012-10-10
JP5245380B2 (ja) 2013-07-24
EP2159826A1 (en) 2010-03-03
CN101689478A (zh) 2010-03-31
KR20100022479A (ko) 2010-03-02
US20100129993A1 (en) 2010-05-27
EP2159826A4 (en) 2010-07-07
US8361888B2 (en) 2013-01-29

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