WO2006092886A1 - 貼り合わせウエーハの製造方法及び貼り合わせウエーハ - Google Patents
貼り合わせウエーハの製造方法及び貼り合わせウエーハ Download PDFInfo
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- WO2006092886A1 WO2006092886A1 PCT/JP2005/020202 JP2005020202W WO2006092886A1 WO 2006092886 A1 WO2006092886 A1 WO 2006092886A1 JP 2005020202 W JP2005020202 W JP 2005020202W WO 2006092886 A1 WO2006092886 A1 WO 2006092886A1
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- wafer
- etching
- oxide film
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- bonded wafer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 144
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 11
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- 239000003570 air Substances 0.000 claims description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 description 130
- 239000010409 thin film Substances 0.000 description 16
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- 239000001257 hydrogen Substances 0.000 description 5
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- 230000003628 erosive effect Effects 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
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- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
- H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Definitions
- the present invention relates to a method for manufacturing a bonded wafer and the bonded wafer, and more particularly to a method for etching an oxide film formed on a terrace portion of a bonded wafer.
- a bonded wafer is used in which a semiconductor wafer is bonded to another wafer and then a wafer on the side on which an element is manufactured is thin-filmed.
- two mirror-polished silicon wafers are prepared, and an oxide film is formed on at least one of the wafers.
- heat treatment is performed at a temperature of 200 to 1200 ° C. to increase the bond strength.
- the device fabrication side wafer (Bondue Ichino) is ground and polished to form a thin film to the desired thickness.
- a bonded SOI wafer in which a (silicon on insulator) layer is formed can be manufactured.
- a bond ion wafer such as hydrogen ions is formed in advance on the bond wafer before bonding and bonded to the base wafer.
- a method also referred to as Smart Cut (registered trademark) in which a bond wafer is thinned by peeling off the ion-implanted layer after combining.
- silicon wafers can be directly bonded without using an oxide film, and an insulating wafer such as quartz, silicon carbide, or alumina can be used as a base wafer. Sometimes used.
- a polishing sag When manufacturing a bonded wafer as described above, there are a part called a polishing sag and a chamfered part in which the thickness is slightly reduced in the peripheral part of the two mirror surface wafers to be bonded.
- the part is not bonded or remains as an unbonded part having a weak bonding force. If the thin film is formed by grinding or the like while such an unbonded portion exists, a part of the unbonded portion is peeled off during the thin film bonding process. Accordingly, the thinned bondeau has a smaller diameter than the base wafer (base wafer), and minute irregularities are continuously formed in the peripheral portion.
- the thickness of the silicon oxide film that forms the buried oxide film (BOX) of SOI wafer varies depending on the device application to be manufactured, but the range of about 0.1 to 2 111 is generally used. However, when used for special applications such as optical waveguides in integrated optical devices, for example, it is 4 ⁇ m or more, or 10 ⁇ m or more, and an extremely thick oxide film is required. May be.
- an SOI wafer having such an extremely thick buried oxide film is to be fabricated by peeling off the ion implantation layer as described above and performing thin film deposition, the ion implantation is performed through the oxide film. Is not practical because it requires extremely large ion implantation energy. Therefore, a method in which a thick oxide film is formed on the base wafer side and bonded is adopted. In this case, an extremely thick oxide film remains on the terrace portion after peeling, which causes the above-described problems. Disclosure of the invention
- the present invention has been made in view of such a problem, and an oxide film formed on the terrace portion of the base wafer without removing the oxide film on the back surface of the base wafer is efficiently formed.
- An object of the present invention is to provide a method for manufacturing a bonded wafer to be pinched.
- the present invention has been made to solve the above-described problems, and etches the oxide film on the terrace portion of the outer peripheral portion of the bonded wafer produced by bonding at least the base wafer and the bond wafer.
- a method for manufacturing wafers is provided.
- the etching solution is scattered outward by centrifugal force and wraps around the back surface of the base wafer. Absent. Accordingly, it is possible to efficiently and uniformly etch the oxide film formed on the terrace portion where the oxide film on the back surface of the wafer is removed.
- the work force can also be increased by reducing the number of processes that do not need to protect the back surface of the wafer with an etching solution by using a masking tape or the like as in the prior art.
- the base wafer and the bond wafer are made to adhere to each other in the production of the bonded wafer for etching the oxide film on the terrace portion, and heat treatment is performed in an oxidizing atmosphere.
- the outer periphery of the bondager is ground and removed to a predetermined thickness, and then the unbonded part of the bondueha outer periphery is removed by etching, and then the bondager is thinned to a desired thickness.
- the oxide film in the terrace portion can be etched by spin etching.
- the base wafer and the bond wafer are bonded to each other for manufacturing a bonded wafer for etching the acid film on the terrace.
- the outer peripheral portion of the bondueha is ground and removed to a predetermined thickness, and then the unbonded portion of the outer periphery of the bondueha is removed by etching, and then the bondueha is removed. It can be used when the oxide film on the terrace portion is etched by spin etching after the unbonded portion or the bond wafer is etched after thinning to a desired thickness.
- a bonded wafer for etching the oxide film on the terrace portion is manufactured. At least, after ion implantation into the bond wafer, the bond wafer and the base wafer are brought into close contact with each other, the bond wafer is peeled off by an ion implantation layer and thinned.
- the present application relates to the manufacture of a bonded wafer for etching the acid film of the terrace portion, by implanting ions into at least the bondueno, so that the bond wafer and the base wafer are brought into close contact with each other.
- the bonding wafer is peeled off from the ion-implanted layer and then thin-filmed, it can be used.
- the acid film can be efficiently etched using the HF aqueous solution.
- the spin etching is performed by supplying an etching solution directly to the terrace portion.
- the spin etching is performed by supplying the etching solution directly to the terrace portion in this way, the etching solution does not flow to the central portion of the bonded wafer (for example, the SOI layer surface). Even if there is a microdefect in the surface, the etching solution is less likely to erode the BOX through the microdefect in the SOI layer.
- the spin etching is preferably performed while supplying a fluid that also protects the central portion of the bonded wafer to the etching liquid force to the central portion of the bonded wafer.
- water, air, nitrogen gas, or inert gas can be used as the fluid.
- any of water, air, nitrogen gas, and inert gas can be used as the fluid for protecting the central portion of the bonded wafer with the etching liquid force.
- the remaining thickness of the oxide film formed on the terrace portion of the base wafer can be controlled by adjusting the processing time of the spin etching and the concentration of Z or the etching solution. Monkey.
- the thickness of the oxide film on the terrace portion can be controlled as desired by adjusting the processing time of spin etching and the concentration of Z or the etching solution.
- the base wafer and the bond wafer before being bonded are silicon single crystal wafers having an oxide film formed on at least one of them.
- the method of the present invention can be used for manufacturing a bonded SOI wafer in which a base wafer made of a silicon single crystal wafer and a bond wafer are joined via an insulating film made of an oxide film.
- the bond wafer is formed into a thin film to form an oxide film on the surface of the bond wafer.
- ozone water is supplied to the terrace portion after the spin etching.
- the terrace portion after the removal of the oxide film can be made hydrophilic, so that adhesion of particles can be suppressed.
- an SOI wafer can be manufactured as the bonded wafer.
- the present invention can be suitably used for manufacturing SOI wafers.
- the thickness of the SOI layer of the SOI wafer can be 0.5 ⁇ m or less.
- the present invention is effective for protecting the BOX when the SOI layer of the SOI wafer is as thin as 0.5 ⁇ m or less.
- an Si or SiGe epitaxial layer can be formed on the surface of the SOI layer of the SOI wafer.
- the present invention also provides a bonded wafer manufactured by the method for manufacturing a bonded wafer.
- the oxide film on the terrace portion of the base wafer is uniformly etched while leaving the oxide film on the back surface of the base wafer, so that the oxide film on the terrace portion is etched.
- This is a high-quality bonded wafer that suppresses warpage of the wafer, which is not a source of dust in the device manufacturing process.
- a bonded wafer in which the remaining thickness of the oxide film on the terrace portion is accurately controlled can be obtained.
- the masking tape is obtained by etching the oxide film formed on the terrace portion of the base wafer by spin etching while holding the bonded wafer. Even if the back surface of the base wafer is not protected by, for example, the oxide film on the terrace portion can be uniformly etched without removing the back surface oxide film. As a result, it is possible to efficiently perform the oxide film etching on the terrace on one side of the wafer by reducing the number of steps compared to the conventional method.
- FIG. 1 is a schematic diagram for explaining an example of a method for producing a bonded wafer according to the present invention.
- FIG. 2 shows a single wafer spin etching apparatus that can be used in the method for manufacturing a bonded wafer according to the present invention.
- FIG. 3 is a cross-sectional view schematically illustrating the structure of the oxide film on the terrace portion of the surface of the bonded wafer.
- FIG. 4 Photographs showing the remaining thickness of each part of the oxide film on the terrace for each processing time of spin etching.
- FIG. 5 is a schematic view for explaining an example of a method for producing a bonded wafer according to the present invention.
- FIG. 6 is a single wafer spin etching apparatus that can be used in the method for manufacturing a bonded wafer according to the present invention.
- FIG. 1 is a schematic view for explaining an example of a method for producing a bonded wafer according to the present invention.
- FIG. 1 first, a raw material wafer for producing an SOI wafer by bonding.
- the bondue and base wafer are not particularly limited, but for example, a silicon single crystal wafer can be used.
- the bondue 2 is subjected to a heat treatment to form an oxide film 4 on the bondueha surface (FIG. 1 (b)).
- the bond wafer 2 and the base wafer 3 on which the acid film is formed are brought into close contact with each other in a clean atmosphere (FIG. 1 (c)).
- This is heat-treated in an oxidizing atmosphere to bond Bondue 2 and Base 3 firmly together to form bonded wafer 1.
- the heat treatment may be performed at a temperature of 200 ° C. and 1200 ° C. in an atmosphere containing oxygen or water vapor (FIG. 1 (d)).
- the bond wafer 2 and the base wafer 3 are firmly bonded, and an oxide film (bonded oxide film) 5 is also formed on the entire outer surface of the bonded wafer 1.
- An unbonded portion of Bondue 2 and wafer 3 is present at about 2 mm of the outer peripheral portion of the bonded wafer 1 thus bonded.
- Such unbonded parts cannot be used as the SOI layer for manufacturing the device, and also peel off in a later process and cause various problems to be removed.
- the outer peripheral portion of the bond wafer 2 where the unbonded portion exists is ground and removed to a predetermined thickness. This is because grinding can be removed at high speed and the processing accuracy is good.
- the predetermined thickness t can be set to 20 150 microns, for example.
- etching is performed to obtain a wafer from which the unbonded portion at the outer peripheral portion of the bondue 2 is removed as shown in FIG. 1 (f).
- the bonded wafer 1 is immersed in an etching solution in which the etching rate of the silicon single crystal is significantly higher than that of the oxide film. It can be done easily. That is, since the silicon is exposed on the outer periphery of the bond wafer 2 by grinding, the other part of the force bonding wafer etched by the etching solution is covered with the oxide film 5. Therefore, it is not etched.
- Examples of such etching include so-called alkaline etching using KOH, NaOH, or the like.
- the terrace portion 7 is formed by such etching.
- the thin film means is not particularly limited, but can be performed by, for example, polishing IJ 'polishing by a normal method.
- the wafer holding means in the spin etching is not particularly limited.
- the wafer holding side can be sucked and held.
- An apparatus for performing the spin etching is not particularly limited, but for example, an apparatus as shown in FIG. 2 can be used.
- Etching is performed by rotating the bonding wafer 1 at a high speed while adhering and holding the bonding wafer 1 by the wafer holding means 10 and supplying the etching solution 9 from the nozzle 8.
- the etching solution 9 is scattered to the outside of the wafer by centrifugal force, and the shaken etching solution 9 is recovered through the recovery cup 11 and the back surface of the wafer. There is no wraparound. Therefore, the oxide film on the back side of the wafer remains without being etched, even if the back side of the wafer is not masked by masking tape, photo resist, or the like. Therefore, according to the present invention, there is no need to mask the wafer back surface with a masking tape or the like, and the number of steps can be reduced and the wafer side oxide film can be etched more efficiently.
- the etching solution does not enter the wafer back surface as described above, the adsorption / holding during spin etching only adsorbs part of the wafer back surface, so that the oxide film on the back surface of the wafer There is no problem that the material is etched. Of course, it may be adsorbed so as to cover the entire rear surface of the wafer or the area where the oxide film is left.
- the etchant used in the spin etching is not particularly limited as long as it can etch the oxide film, but for example, an HF aqueous solution is preferable. In this case, HF50% water soluble More preferably, a liquid is used. If the aqueous solution is 50% HF, the etching rate is large and the working efficiency can be increased. As described above, according to the spin etching, an etching solution having a relatively high concentration can be used. Therefore, even if a thick oxide film is formed on the terrace portion, the etching removal can be performed quickly and uniformly. it can.
- the remaining thickness of the oxide film on the terrace can be controlled with high accuracy by adjusting the spin etching processing time and the concentration of Z or the etching solution.
- the etching rate can be controlled more accurately by controlling the temperature of the etching solution.
- a bonded wafer having the SOI layer 6 according to the present invention, the oxide film 5 on the base wafer side, and the oxide film of the terrace portion 7 removed can be produced.
- spin etching was performed after thinning the surface of Bondueha 2, but the present invention is not limited to this. Spin etching may be performed after the unbonded portion is etched, and then thin film deposition may be performed.
- the oxide film 4 is formed on the bond wafer 2 and adhered to the base wafer 3.
- the acid film may be formed on the base wafer 3 and adhered to the base wafer 3, In some cases, an acid film is formed on both of them to bring the force into close contact. Further, the bondueha and the base wafer may be brought into direct contact with each other without using an acid film. Further, the base wafer and the bond wafer used in the method of the present invention are not limited to the silicon single crystal wafer.
- an SOI wafer is manufactured by a hydrogen ion stripping method (smart cut method (registered trademark)). I will explain.
- step (a) of Fig. 5 two silicon mirror wafers are prepared.
- step (b) at least one of them, in this case, the base wafer 21, is thermally oxidized, and an oxide film 23 having a thickness of about 0.1 / ⁇ ⁇ -2. Form. Depending on the application, an oxide film of 4. O / zm or more may be formed.
- step (c) at least one of hydrogen ions or rare gas ions, here hydrogen ions, is implanted into one side of Bondueha 22 to form a microbubble layer parallel to the surface at an average ion penetration depth.
- (Encapsulation layer) 24 is formed, and the injection temperature is preferably 25 to 450 ° C.
- the step (d) is a step in which the base wafer 21 is superposed on and bonded to the hydrogen ion-implanted surface of the bond ion wafer 22 into which hydrogen ions have been implanted through an oxide film, and is bonded in a clean atmosphere at room temperature. By bringing the two wafer surfaces into contact with each other, the wafers can be bonded to each other without using an adhesive or the like.
- step (2) separation is performed with the encapsulation layer 24 as a boundary, thereby separating the separation wafer 25 and the SOI wafer 26 in which the SOI layer 27 is formed on the base wafer 21 via the oxide film 23.
- the separation wafer 25 and the SOI wafer 26 are formed by crystal rearrangement and bubble aggregation.
- the film 23 is separated into the base wafer 21).
- the adhesion strength is increased by plasma-treating the surface to be used for the adhesion of both wafers, it can be mechanically peeled off by the encapsulating layer 24 without performing a heat treatment after the adhesion. It's pretty.
- the bonding force between the wafers bonded in the bonding process and the peeling process in the above steps (d) and (e) is weak to use in the device manufacturing process as it is.
- a high-temperature heat treatment is performed so that the bond strength is sufficient.
- This heat treatment is preferably performed, for example, in an inert gas atmosphere or an acidic gas atmosphere (in this case, an acidic gas atmosphere) at 1050 ° C. to 1200 ° C. for 30 minutes to 2 hours.
- the oxide film 31 is formed on the surface of the SOI layer 27, and at the same time the back surface of the base wafer and the oxide film on the terrace portion 30 are also formed. Become thicker.
- the spin etching step (g) is then performed. Then, the acid film on the terrace 30 is removed.
- An apparatus for performing spin etching is not particularly limited, and the above-described apparatus can be used.
- an apparatus as shown in FIG. 6 can be used.
- the SOI wafer 26 is adsorbed and held by the wafer holding means 10, the etching solution 9 is supplied directly to the terrace portion from the nozzle 8, and the fluid 12 protecting the central portion of the SOI wafer from the etching solution 9 is supplied to the central portion of the SOI wafer. While supplying, spin etching is performed by rotating SOI wafer 26 at high speed.
- the etching solution When the etching solution is directly supplied to the terrace portion in this way and spin etching is performed, the etching solution does not flow on the surface of the SOI layer, so even if the SOI layer is a thin layer of 0. or less, There is little risk that the etching solution will erode the BOX through minute defects in the SOI layer. Also, if spin etching is performed in this way while supplying the fluid 12 that also protects the central portion of the bonded wafer with the etching solution force, the possibility of the etching solution flowing on the surface of the SOI layer is further reduced.
- the fluid 12 is not particularly limited, and for example, water, air, nitrogen gas, or inert gas can be used.
- the bondue wafer before performing the spin etching step (g), the bondue wafer is thinned to form an oxide film 31 on the bondueha surface (the surface of the SOI layer 27). In this case, even if the etching solution 9 has entered the surface of the SOI layer 27 in the spin etching step (g), erosion of the BOX can be surely prevented.
- the etching solution 9 is scattered to the outside of the wafer by centrifugal force, and the scattered etching solution 9 passes through the recovery force 11. It is recovered and does not wrap around the back side of the wafer. Therefore, the oxide film on the backside of the wafer remains without being etched, even without masking the backside of the wafer with masking tape, photoresist, or the like. Therefore, according to the present invention, the step of masking the back surface of the wafer with a masking tape or the like is not necessary, and the number of steps can be reduced and the terrace-side oxide film on one side of the wafer can be etched more efficiently.
- ozone water is supplied to the terrace section 30.
- the terrace portion after the removal of the oxide film can be made hydrophilic, adhesion of particles can be suppressed.
- the oxide film is formed on the base wafer and the force is adhered to the bondueno.
- the oxide film may be formed and bonded to the bondue, or the base wafer, It is also possible to form an oxide film on both the bondager and bondueha.
- an Si or SiGe epitaxial layer can be formed on the surface of the SOI layer of the SOI wafer.
- the oxide film is not exposed. Therefore, even if an Si Ge epitaxial layer is formed, the formation of polysilicon is prevented. Therefore, the generation of particles can be suppressed without adversely affecting the crystallinity of the SOI layer.
- the method for manufacturing a bonded wafer according to the present invention is used, even if the SOI layer is a thin layer of 0.5 / zm or less, the fineness in the SOI layer can be reduced by spin etching. It is possible to manufacture high-quality SOI wafers with an SOI layer thickness of 0.5 m or less, with less risk of etchant eroding the BOX through defects.
- the bonded wafer obtained by the manufacturing method as described above is used to etch the oxide film formed on the terrace portion of the base wafer while leaving the oxide film on the back surface of the base wafer. It has been done. Therefore, it is possible to obtain a high-quality bonded wafer in which warpage of the wafer is suppressed, in which the oxide film on the terrace portion does not become a dust source in the device manufacturing process. Further, it is possible to obtain a bonded ueno in which the thickness of the oxide film on the terrace portion is precisely set to a desired thickness.
- mirror-polished CZ wafers with a diameter of 200 mm, conductive p-type, and resistivity of 4-6 ⁇ 'cm were prepared as base wafer and bond wafer, respectively. And these 1 c is bonded in accordance with the steps (a) to (c) in Fig. 1, and bonded heat treatment is performed for 1 hour at 1150 ° C in an oxygen atmosphere, as shown in Fig. 1 (d). Was made.
- the outer peripheral portion of the bondueha 2 was ground from the outer peripheral direction of the wafer toward the center using a grinding device.
- the thickness t was 50 / z m.
- the surface of the bond wafer 2 is ground and polished using a surface grinder and a single-side grinder to form a thin film to form an SOI layer 6 to obtain a wafer as shown in FIG. 1 (g). It was.
- Figure 3 shows the structure of the oxide film on the terrace of the bonded wafer surface at this time.
- the acid film in the region a can be used only by the bond film (embedded oxide film) 4 of Bondueha 2.
- the bond film (embedded oxide film) 4 of Bondueha 2 In the region b, in addition to the buried oxide film 4, there is an oxide film (bonded oxide film) 5 generated during the bond heat treatment between the bond wafer and the base wafer, and as a whole, an oxide film thicker than the region a is formed. .
- the binding oxide film 5 has a force.
- FIG. 4 shows the results obtained.
- Figure 4 is a photo of the wafer terrace and shows the thickness of the oxide film by area from the SOI layer at the bottom of the photo to the chamfer at the top.
- the oxide film formed on the terrace portion of the base wafer is completely obtained by adsorbing and holding the base wafer side of the bonded wafer and performing spin etching for 80 seconds. Can be removed.
- the remaining thickness of the oxide film on the wafer terrace can be controlled, and a bonded wafer having any desired terrace film thickness can be obtained. Can be manufactured.
- mirror-polished CZ wafers with a diameter of 200 mm, conductive p-type, and resistivity of 4-6 ⁇ 'cm were prepared as base wafer and bond wafer, respectively.
- Figure these woofers As shown in Fig. 5, an SOI wafer was obtained by forming a 5 m thick oxide film on the base wafer and transferring the Bondueha Si layer to the base wafer using the smart cut method (registered trademark). Thereafter, stabilization heat treatment was performed.
- an oxide film of 5 ⁇ m exists on the terrace portion of the SOI wafer.
- This oxide film was removed by spin etching using the apparatus shown in FIG. A 50% HF aqueous solution was used as an etching solution, and the etching solution was directly supplied to the terrace portion for 5 minutes to remove the oxide film on the terrace portion.
- pure water was supplied to the center of the SOI wafer as a fluid 12 that also protects the SOI layer from the etching solution.
- HF aqueous solution was removed by rinsing for 2 minutes. After the rinse treatment, spin drying was performed.
- the oxide film 31 of the SOI layer was removed, the surface was polished, and the SOI layer was flattened to obtain an SOI wafer.
- the SOI wafer obtained in this way was confirmed to be of a very high quality in which HF does not erode the BOX through micro-defects in the SOI layer during spin etching.
- mirror-polished CZ wafers with a diameter of 200 mm, conductivity type p-type, and resistivity of 4-6 ⁇ 'cm were prepared as base wafers and bond wafers, respectively. As shown in Fig. 5, these wafers were formed with a 400 nm oxide film on the base wafer, and the SOI wafer was obtained by transferring the Bondueha Si layer to the base wafer using the Smart Cut Method (registered trademark). Thereafter, stabilization heat treatment was performed.
- the present invention is not limited to the above embodiment.
- the above embodiment is an exemplification, and the present invention has the same configuration as the technical idea described in the scope of claims of the present invention, and any device that exhibits the same function and effect is the present embodiment. It is included in the technical scope of the invention.
- the thin film was formed by polishing ij ⁇ polishing or ion implantation separation method, but the thin film may be formed by etching or other methods.
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- Computer Hardware Design (AREA)
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- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Inorganic Chemistry (AREA)
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP05805496A EP1855309A4 (en) | 2005-02-28 | 2005-11-02 | METHOD FOR PRODUCING A BONDED WAFERS AND BONDED WAFER |
CN2005800484901A CN101124657B (zh) | 2005-02-28 | 2005-11-02 | 贴合晶圆的制造方法及贴合晶圆 |
US11/883,816 US20080315349A1 (en) | 2005-02-28 | 2005-11-02 | Method for Manufacturing Bonded Wafer and Bonded Wafer |
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JP2005054718 | 2005-02-28 | ||
JP2005-054718 | 2005-02-28 |
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WO2006092886A1 true WO2006092886A1 (ja) | 2006-09-08 |
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PCT/JP2005/020202 WO2006092886A1 (ja) | 2005-02-28 | 2005-11-02 | 貼り合わせウエーハの製造方法及び貼り合わせウエーハ |
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US (1) | US20080315349A1 (ja) |
EP (1) | EP1855309A4 (ja) |
KR (1) | KR101151458B1 (ja) |
CN (1) | CN101124657B (ja) |
TW (1) | TW200631068A (ja) |
WO (1) | WO2006092886A1 (ja) |
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US20120122299A1 (en) * | 2009-07-10 | 2012-05-17 | Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science | Method for forming substrate with buried insulating layer |
US8192822B2 (en) | 2008-03-31 | 2012-06-05 | Memc Electronic Materials, Inc. | Edge etched silicon wafers |
US8735261B2 (en) | 2008-11-19 | 2014-05-27 | Memc Electronic Materials, Inc. | Method and system for stripping the edge of a semiconductor wafer |
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EP2159826A1 (en) * | 2007-06-21 | 2010-03-03 | Shin-Etsu Handotai Co., Ltd. | Soi wafer manufacturing method |
EP2159826A4 (en) * | 2007-06-21 | 2010-07-07 | Shinetsu Handotai Kk | PROCESS FOR PRODUCING SOI WAFERS |
US8361888B2 (en) | 2007-06-21 | 2013-01-29 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI wafer |
WO2009069709A1 (ja) * | 2007-11-27 | 2009-06-04 | Shin-Etsu Chemical Co., Ltd. | 貼り合わせ基板の製造方法 |
CN101874290B (zh) * | 2007-11-27 | 2013-01-02 | 信越化学工业株式会社 | 贴合基板的制造方法 |
US8716106B2 (en) | 2007-11-27 | 2014-05-06 | Shin-Etsu Chemical Co., Ltd. | Method for producing a bonded substrate |
US8192822B2 (en) | 2008-03-31 | 2012-06-05 | Memc Electronic Materials, Inc. | Edge etched silicon wafers |
US8309464B2 (en) | 2008-03-31 | 2012-11-13 | Memc Electronic Materials, Inc. | Methods for etching the edge of a silicon wafer |
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US8853054B2 (en) | 2012-03-06 | 2014-10-07 | Sunedison Semiconductor Limited | Method of manufacturing silicon-on-insulator wafers |
Also Published As
Publication number | Publication date |
---|---|
EP1855309A4 (en) | 2010-11-17 |
CN101124657A (zh) | 2008-02-13 |
EP1855309A1 (en) | 2007-11-14 |
US20080315349A1 (en) | 2008-12-25 |
KR20070116224A (ko) | 2007-12-07 |
KR101151458B1 (ko) | 2012-06-01 |
TW200631068A (en) | 2006-09-01 |
CN101124657B (zh) | 2010-04-14 |
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