Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/81—Bodies
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
  • H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/03—Conductive materials
  • H05K2201/0332—Structure of the conductor
  • H05K2201/0364—Conductor shape
  • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
  • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
  • H10H20/018—Bonding of wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/81—Bodies
  • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/013—Manufacture or treatment of die-attach connectors
  • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
  • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/331—Shapes of die-attach connectors
  • H10W72/334—Cross-sectional shape, i.e. in side view
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/381—Auxiliary members
  • H10W72/387—Flow barriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/884—Die-attach connectors and bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

• the present invention relates to a device having a first component with a first surface, a second component having a second surface and a connection layer between the first surface of the first component and the second surface of the second component, and a method for producing such a device.
• connection layer for example of a solder or an adhesive
• a connection layer for example of a solder or an adhesive
• an electrically conductive adhesive or a metallic solder is generally used if an electrically conductive connection is desired, while an electrically insulating adhesive is used for electrically insulating connections.
• solder is not always possible due to the relatively high processing temperatures.
• electrically conductive adhesive due to the fillers compared to electrically insulating adhesives usually consuming.
• a device has a first component with a first surface and a second component with a second surface, wherein
• At least one of the first and second surfaces has topographical surface structures
• component not only finished components such as light emitting diodes (LEDs) or laser diodes are meant, but also substrates or Epitaxie Anlagenenmaschine, so that the first component and the second component connected by the connection layer form a parent third component or are part of such.
• a surface with a topographic surface structure, a microscopic and / or a have macroscopic height profile.
• a height profile may extend regularly or irregularly in one or in two directions parallel to the surface over the entire surface or over one or more subregions of the surface.
• both the first and the second surface may have topographical surface structures.
• the topographical surface structures may be the same, similar or different at least in one subregion.
• the topographic surface structures are due to the roughness of the first and / or second surface.
• This may in particular mean, for example, that topographic surface structures having the first surface are different from topographic surface structures having the second surface, for example due to different roughnesses of the first and second surfaces.
• the topographic surface structures of the first surface and the topographic surface structures of the second surface may be the same or similar. This may mean, in particular, that the roughnesses and roughness depths of the first and second surfaces are the same or at least similar.
• the electrically insulating connection layer advantageously a much thinner bonding layer between the two surfaces of the components than by an electrically conductive connection layer.
• the electrically insulating Connecting layer has an electrically insulating adhesive.
• the electrically insulating connection layer consists of an electrically insulating adhesive or a mixture of electrically insulating adhesives or of a mixture of an electrically insulating adhesive with further electrically insulating additives.
• An electrically insulating adhesive or a mixture of electrically insulating adhesives or a mixture of an electrically insulating adhesive with further electrically insulating additives may be advantageous, for example, in comparison to the use of an electrically conductive adhesive in that the electrically insulating adhesive, for example, has no electrically conductive fillers. Due to the fillers in electrically conductive adhesives adhesive thicknesses in the range of some 10 microns are required when using electrically conductive adhesives. By contrast, a very thin bonding layer, as is possible, for example, with an electrically insulating adhesive, may allow the thermal resistance of the bonding layer to be advantageously reduced compared to a bonding layer of greater thickness.
• electrically insulating connecting layers which have, for example, electrically insulating adhesives, with thicknesses of 100 nm, contribute less than 1 K / W to the heat transfer resistance with a planar, full-area connection and heat load.
• an electrically insulating adhesive may have a thermal conductivity in the range of 0.2 to 0.4 W / mK, in particular 0.293 W / mK at 24 ° C, 0.310 W / mK at 45 ° C and 0.324 W / mK at 66 ° C exhibit.
• the electrically insulating connection layer has an electrically insulating adhesive, which may in particular mean that the connection layer has no electrically conductive fillers.
• the connection layer has no electrically conductive fillers.
• an electrically insulating compound layer without electrically conductive fillers may be advantageous since, for example, gold-filled electrically conductive adhesive can increase the process costs.
• the usual electrically conductive adhesives are often not compatible with process chemicals, such as those used in thin-film LED manufacturing, for example.
• electrically insulating bonding layers which comprise, for example, electrically insulating adhesive
• electrically insulating bonding layers offer the advantage that electrically insulating bonding layers can be processed at significantly lower temperatures compared to soldering processes. So solder joints often require process temperatures of more than 200 0 C to produce a metallurgical bond, which are not necessarily compatible with the requirements of the components to be connected.
• an electrically insulating connection layer comprising, for example, an electrically insulating adhesive, does not require any additional effort with regard to the separation and protection of functional layers, for example by diffusion barriers, as is sometimes required in solder joints.
• the first component or the second component or both may be, for example, a substrate, a wafer, a glass substrate, a heat sink, an epitaxial layer sequence, a semiconductor chip such as a light-emitting diode chip or a laser diode chip or else an optoelectronic component such as an organic light-emitting diode (OLED) or a light-emitting diode Semiconductor basis.
• a semiconductor chip such as a light-emitting diode chip or a laser diode chip or else an optoelectronic component such as an organic light-emitting diode (OLED) or a light-emitting diode Semiconductor basis.
• OLED organic light-emitting diode
• an epitaxial layer sequence having an active zone in which electromagnetic radiation is generated in operation and a carrier such as a glass substrate or a wafer as the second component can be used as the first component.
• a carrier such as a glass substrate or a wafer as the second component.
• thin-film semiconductor chips are characterized by at least one of the following characteristic features:
• a reflective layer is applied or formed which at least a part of the electromagnetic radiation generated in the epitaxial layer sequence is reflected back into it;
• the epitaxial layer sequence has a thickness in the range of 20 microns or less, in particular in the range of 10 microns;
• the epitaxial layer sequence comprises at least one semiconductor layer having at least one surface which has a mixing structure which, in the ideal case, leads to an approximately ergodic distribution of the radiation in the epitaxial layer sequence, i. it has as ergodically stochastic scattering behavior as possible.
• the growth substrate of the radiation-generating epitaxial layer sequence may typically be removed or thinned, and the epitaxial layer sequence may be transferred to another substrate.
• the connection between carrier and epitaxial layer sequence should be electrically conductive, the presently proposed compound may be suitable in particular for a thin-film semiconductor chip in order to be able to contact the thin-film semiconductor chip via the carrier.
• this may result in the advantage that an electrically insulating connecting layer can be thin enough so that it can have a low thermal resistance in order to be able to effectively dissipate the heat from the epitaxial layer sequence that can arise during operation in the same.
• the first component can be a
• the second component may be a carrier, for example a substrate or a leadframe, which may likewise have at least two electrical contact surfaces.
• the respective at least two electrical contact surfaces of the first and the second component may have the same or different electrical polarities.
• the first component may be a structured epitaxial layer sequence for a thin-film semiconductor chip described above or a semiconductor chip for so-called flip-chip mounting which is electrically connected to a second component on one side by means of two electrical contact surfaces having different electrical polarity can be connected.
• optoelectronic semiconductor chips such as light-emitting diode chips or laser diode chips, can also be mounted on a heat sink or a component housing.
• the first surface or the second surface has recesses.
• the recesses can only on the first surface of the first component or only on the second surface of the - S -
• the first surface of the first component and / or the second surface of the second component have a joining region, may be mounted within the electrically insulating adhesive, which may form the electrically conductive bonding layer.
• the recesses in the first and / or second surface are preferably arranged around the respective joining region.
• the depressions may preferably serve as collecting reservoirs for the adhesive. As a result, it may be possible for excessively applied adhesive, which is displaced from the joining region, to flow off into the collecting reservoirs and remain there.
• the depressions can continue to be arranged regularly or irregularly spaced.
• the recesses or receiving reservoirs have a uniform arrangement.
• a uniform or regular arrangement may be advantageous, for example, since it may be possible to produce the depressions by means of photomasks customary in the epitaxial layer sequence production process, and since it may be possible to avoid a reduction of the epitaxial surface by a uniform or regular arrangement can.
• At least one of the surfaces may have a structured surface.
• the structuring can be given, for example, by microprism structuring or microreflector structuring. It can depressions or collecting reservoirs due to Micro prisms or micro-reflectors can be formed, which can be produced for example by etching.
• Recesses or catchment reservoirs may be embodied, for example, as mesa trenches or as parts of mesa trenches which may, for example, cut through an entire epitaxial layer sequence or a part thereof.
• the depth of the depressions may correspond to the thickness of the Epitaxie WegenUSD or be less than this.
• the depressions can furthermore have a width, which can be given by the width of the mesa trenches, which in turn can be predetermined, for example, by later processing steps such as singulation. It may be advantageous if the wells have a volume that is large enough to accommodate the entire displaced adhesive can.
• the volume of the recesses or collecting reservoirs and the desired thickness of the connecting layer can give a condition for the maximum adhesive layer to be applied.
• the recesses or collecting reservoirs are formed by mesa trenches which have a spacing of about 1000 ⁇ m and a trench width of about 40 ⁇ m and whose depth corresponds, for example, to the thickness of the epitaxial layer sequence of about 7 ⁇ m.
• a thickness of about 0.5 ⁇ m may prove advantageous for an adhesive layer for application.
• pits or catch reservoirs may be provided through the pits given by the roughness of a surface or portion of a surface.
• the average thickness of the connection layer is of the order of the topographical surface structures of the first and / or the second surface. This may mean, in particular, that the average thickness of the bonding layer is of the order of the roughness or roughness of the first surface and / or the second surface.
• Roughness may be the rms value of the height variations of a surface defined as the root of the mean square distance of a height profile of a surface from a mean height of the surface.
• the height profile of the surface can be determined for example by means of an atomic force microscope by height profiles are recorded within one or more sections of the surface. From the height profile of the surface obtained, for example, by means of atomic force microscopy, stylus profile profilometry or white light interferometry, an average height can be determined, which represents the arithmetic mean of the height profile. Using the mean height and the determined height profile, the rms value can be determined as the value for the roughness of the surface.
• the thickness of the tie layer is defined as the distance between the mean height of the first surface and the mean height of the second surface.
• the roughness of a surface or a region of a surface may correspond to the natural roughness that results in the deposition of metal layers, such as electrical metal-semiconductor contact layers or metallic reflective layers.
• the roughness of a surface or a portion of a surface can be increased, for example, by methods such as photolithographic patterning or sandblasting. Furthermore, increased roughness can be achieved by choosing suitable deposition conditions such as a slow vapor deposition rate and / or high substrate temperatures.
• a sufficiently thin connection layer can thus ensure an electrically conductive contact between the surfaces of the components in particular in that, for example, elevated areas of the topographic surface structures of the first surface are in direct contact with the second surface and / or vice versa.
• elevated area of the topographic surface structures of the first surface may be in direct contact with raised areas of the topographic surface structures of the second surface.
• the raised regions of the topographic surface structures may include or be in particular the roughness peaks of the first surface and / or the roughness peaks of the second surface, and it may also be that roughness peaks of the first surface with roughness peaks of the second surface are in direct contact with each other.
• the roughness of the first surface and / or the second surface at least within the joining region is at least a few nanometers.
• the first surface and the second surface are at least partially electrically conductive.
• at least a part of the joining region may preferably be designed to be electrically conductive.
• at least partial regions of the topographic surface structures can also be designed to be electrically conductive.
• An electrically conductive first surface and / or second surface is / are metallic, for example.
• the first and / or second surface may be of electrically conductive construction, but may also comprise or consist of a conductive transparent oxide (TCO).
• TCO conductive transparent oxide
• the electrically insulating adhesive forming the tie layer is solvent resistant to solvents such as N-methyl-pyrrolidone (NMP), for example, 1-methyl-2-pyrrolidinone, acetone, isopropanol, ethanol, and / or methanol.
• solvents such as N-methyl-pyrrolidone (NMP), for example, 1-methyl-2-pyrrolidinone, acetone, isopropanol, ethanol, and / or methanol.
• NMP N-methyl-pyrrolidone
• KOH potassium hydroxide
• NaOH sodium hydroxide
• phosphoric acid may be advantageous.
• the electrically insulating adhesive can preferably be vacuum-compatible with respect to a typical process vacuum between 0.1 millibar and a few hundred millibars, preferably about 100 millibars, and / or temperature-stable at temperatures above 200 ° C.
• Such features can generally be advantageous in terms of requirements in the following process steps and / or the later use of the components.
• the bonding technique to be used should be compatible with the common process steps and chemicals used in the manufacturing chain of the device.
• the bonding layer should not adversely affect the operation of the device or the individual components. In particular, it may be advantageous if no disadvantageous effects are caused by outgassing of solvents, plasticizers or other components.
• the electrically insulating adhesive is UV-curable. This can be advantageous if the connection layer is optically accessible from at least one side, for example when a component is transparent, so that the connection layer can be illuminated with UV light from the side of the transparent component.
• the electrically insulating adhesive comprises bisbenzocyclobutene (BCB) or consists of BCB.
• BCB bisbenzocyclobutene
• Processing properties of BCB are disclosed in T. Takahashi, Proc. 3rd Japan International SAMPE Symposium (1993), pp. 826-833, the disclosure of which is hereby incorporated by reference.
• BCB has the advantage that it cures without the production of by-products such as water and therefore has very little shrinkage.
• the first surface and the second surface have topographical structures.
• topographic structures are created by methods such as etching or grinding.
• the recesses are produced on at least one of the first and second surfaces to be joined by ablative structuring methods, such as etching or grinding, and / or by deforming structuring methods, such as embossing.
• ablative structuring methods such as etching or grinding
• deforming structuring methods such as embossing.
• Different recesses can be produced on one component or on both components by different methods.
• the electrically insulating connection layer such as a electrically insulating adhesive
• a structured manner such as a electrically insulating adhesive
• This can be done for example by printing processes such as inkjet printing or screen printing. It may be advantageous if a bonding layer with a thickness of at least about 10 microns by screen printing, a bonding layer of less than about 10 microns is applied by ink jet printing.
• stamping methods can be used, for example.
• the electrically insulating connection layer for example an electrically insulating adhesive
• the unstructured applied connecting layer is structured after application. Structuring may be possible, for example, in that at least partial regions of at least one surface or at least of regions thereof have different wetting properties with regard to the connecting layer. Different wetting properties can be achieved, for example, by modifying subregions of at least one surface or at least portions thereof.
• the connection layer can be patterned, for example, by light. Exposure can be done for example by a photomask.
• the bonding layer has a thickness between 10 after application nm and 100 ⁇ m. It may also be advantageous if the bonding layer has a thickness between 100 nm and 10 ⁇ m after application. It may be particularly advantageous if the bonding layer has a thickness between 500 nm and 5 ⁇ m after application.
• the thickness of the bonding layer after application may depend on the viscosity and / or the structuring of the bonding layer and / or the roughness of the first and / or the second surface.
• the thickness of the bonding layer is reduced by applying a force to at least one component or to both components such that, after being applied, the thickness of the bonding layer is of the order of roughness or roughness of the first and / or the first second surface is.
• the thickness of the connecting layer has reduced to such an extent that at least the roughness peaks of the surfaces to be joined touch.
• a force in a range of 1 to 40 kN is applied to an area of 20 to 78 cm 2 .
• FIGS. 1A to 1F show schematic sectional views of a device at various stages of the method according to the invention
• FIG. 2 a schematic sectional view of a section of a device according to a first exemplary embodiment
• FIG. 3 a schematic sectional view of a device according to a second exemplary embodiment
• Figure 5 a schematic sectional view of a device according to a fifth embodiment
• FIGS 6A to 6E schematic sectional views of further devices according to further embodiments.
• an epitaxial layer sequence 2 is grown epitaxially on a suitable growth substrate 1, for example an SiC substrate or a sapphire substrate.
• the epitaxial layer sequence comprises an active zone 3 in which radiation is generated in operation and further functional layers 4.
• the active zone 3 comprises, for example, a pn junction, a double heterostructure, a single quantum well or a multiple quantum well (MQW ) on .
• the term quantum well structure does not contain any information about the dimensionality of the quantization. It thus includes u.a. Quantum wells, quantum wires and quantum dots and any combination of these structures. Examples of MQW structures are described in the publications WO 01/39282, US 5,831,277, US 6,172,382 Bl and US 5,684,309, the disclosure content of which is hereby incorporated by reference.
• a reflective layer 5 is applied to the side of the epitaxial layer sequence 2 facing away from the growth substrate 1, the radiation generated in the active zone 3, which would emerge from the epitaxial layer sequence 2 on the side remote from the growth substrate 1, is reflected back into the epitaxial layer sequence 2.
• the reflective layer 5 has Au, Al or Ag or an alloy of these metals and can be used as a single layer or as a layer sequence with layers of other materials.
• the total thickness of an epitaxial layer sequence 2 of a conventional thin-film semiconductor chip is in the range of several micrometers to several tens of micrometers.
• a bonding layer 7 is applied on the side 6 facing away from the growth substrate 1 of the reflective layer 5, which in the present case serves as the first surface of the first component.
• a microprism structuring on the side facing away from the growth substrate 1 6 of the reflective layer 5, as described in the publication WO 02 / 13281A1, the disclosure of which is hereby incorporated herein by reference, can be advantageously used as pre-structuring.
• Recesses for microprisms can, for example, be etched into a semiconductor layer over which a reflective layer 5 can then be deposited.
• the reflective layer 5 is preferably formed from an electrically conductive material.
• a connecting medium which is solvent-resistant, vacuum-compatible, and / or temperature-stable, among other things, and which is compatible with all further process steps.
• a suitable material for the bonding layer 7 is, for example, BCB (Bisbenzocyclobuten, which is available, for example, under the trade name Cyclotene 3022-xx from Dow Corning, where "xx" indicates the proportion of prepolymerized BCB monomers in the solvent mesitylene), which advantageously Photoresist with well reproducible thicknesses in the range of 0.5 to ten microns is aufschleuderbar and on the zu Bonding surfaces usually adheres well.
• Cyclotene 3022-35 or Cyclotene 3022-46 can prove to be advantageous, with which, for example, coating thicknesses of about 1.0 to about 2.3 ⁇ m or of about 2.4 to about 5.5 ⁇ m can be achieved during application ,
• the BCB film may optionally be patterned by reactive ion etching using a titanium mask.
• the connecting layer 7 is also applied to a carrier substrate 8 to be connected to the epitaxial layer sequence 2.
• a carrier substrate 8 is positioned as a second component with a second surface 9 in a desired position relative to the epitaxial layer sequence 2 on the connection layer 7.
• Suitable materials for the carrier substrate 8 are electrically conductive, such as silicon or metal, or electrically insulating with an electrically conductive surface.
• a simple electrical contacting of the epitaxial layer sequence 2 by the carrier substrate 8 can take place in the further method steps.
• a force 10 is applied essentially perpendicularly to the surfaces 6, 9 of the epitaxial layer sequence 2 that terminate the reflective layer 5 and the carrier substrate 8.
• the thickness of the connecting layer 7 is reduced so much that, according to the exemplary embodiment in FIG. 2, an electrically conductive contact is produced by the contact of topographical surface structures of the surfaces 6, 9 of the reflective layer 5 terminating the epitaxial layer sequence 2 and of the carrier substrate 8.
• the topographical surface structures of the surfaces 6, 9 can advantageously be roughness peaks 20, 21, as shown in the embodiment of FIG.
• the thus reduced thickness connecting layer 7 according to FIG IE is cured under moderate pressure by a freely selectable within wide limits temperature range.
• a force of about 1 to about 40 kN can prove to be suitable on an area of about 20 to about 78 cm 2 .
• BCB may for example be cured at temperatures ranging from about 150 to about 200 0 C.
• hardening at a temperature of about 150 ° C. for about 12 hours or at a temperature of about 200 ° C. for about 0.5 hours can prove to be particularly advantageous.
• connection layer 7 Due to the good process compatibility in terms of mechanical strength and temperature resistance of Connection layer 7, the device can be further processed.
• a good process compatibility can be shown in particular by the fact that the process layer is not restricted or adversely affected by the connection layer further process steps. For example, it may be possible through the connection layer that the absence of outgassing, which may be detrimental to subsequent process steps in vacuum, by the resistance to etching processes and by the compatibility of the bonding layer with temperatures of subsequent process steps, no adverse effect on a process for manufacturing example a semiconductor chip with a connection layer according to the invention is formed.
• the growth substrate 1 is thinned, for example, by grinding or completely removed.
• a Bond Päd 12 for contacting the Epitaxie fürenide 2 is applied in a further process step (see Figure IF).
• An electrical contacting of the thus obtainable semiconductor chip 13 can be made possible by electrical leads which contact the carrier substrate 8 and the bonding pad 12.
• suitable carrier substrates such as lead frames, is shown in the embodiments of FIGS. 3 to 5.
• the illustrated method can be used with a carrier wafer for the large-area connection of a four-inch epitaxial wafer having the epitaxial layer sequence on a growth substrate.
• a carrier wafer for the large-area connection of a four-inch epitaxial wafer having the epitaxial layer sequence on a growth substrate.
• approximately 50,000 thin-film semiconductor chips can usually be produced on a four-inch carrier wafer, whose electrical contact can be checked and verified by the carrier wafer for each thin-film semiconductor chip.
• the electrical contact resistances between the carrier wafer and the thin-film semiconductor chips are not increased compared to the otherwise usual solder joints.
• electrical contacting of the semiconductor chip 13 does not take place via the carrier substrate 8 on the side 8 of the reflective layer 5 facing the carrier substrate 8 and via the bond pad 12 on the side 11 of the epitaxial layer sequence 2 facing away from the carrier substrate 8, as in the exemplary embodiment according to FIG. but via structured electrical contacts on only one side of the epitaxial layer sequence 2, electrical contacting of the structured electrical contacts with structured electrical leads takes place, for example, on a structured conductor strip by means of a connecting layer 7 of electrically insulating adhesive.
• flip-chip mounting is described in the document EP 0905797 A2, the disclosure content of which is hereby incorporated by reference. It is the to be mounted and closed contacting thin-film semiconductor chip 13 with reflective running contacts 5 on the electrical leads, for example, on the conductor strip, placed on, are provided by structuring the reflective contacts 5 suitable acting as receiving trenches 40 wells.
• Connecting layer 7 is used electrically insulating adhesive, which offers the advantage that short circuits are basically avoided by fluctuations in the assembly process. It may, for example, be possible that too much applied adhesive, which can cover the side surfaces of a semiconductor chip, ie the chip flanks, does not cause a short circuit of the epitaxial layer sequence.
• a section of a device according to the invention is shown.
• a first surface 6 of a first component 5 and a second surface 9 of a second component 8 each have topographical surface structures 22, 24, which can be determined in a measurement, for example by atomic force microscopy, as height profile.
• an average contour line 26 of the surface 22 and an average contour line 27 of the surface 24 can be indicated.
• the spacing of the mean contour lines 26 and 27 defines the thickness 28 of the bonding layer 7.
• the surface structures 22, 24 have elevations 20, 21, such as roughness peaks, between which depressions may be located in the exemplary embodiment shown.
• the bumps may be irregular, such as with an unstructured roughness profile.
• the elevations may also be regularly arranged at least in some areas.
• the first component 5 can be, for example, the epitaxial layer sequence with the reflective layer from the exemplary embodiment IA, wherein the first surface is the side of the reflective layer facing away from the epitaxial layer sequence, and the second component 8 can be the carrier substrate.
• the first component 5 may, for example, also be a semiconductor chip 13, such as a thin-film semiconductor chip according to one of the following embodiments, wherein the first surface 6 may be the side of the carrier substrate facing away from the epitaxial layer sequence, and the second component 8 may be the leadframe of a housing surface mount device or other suitable substrate for the semiconductor chip 13, as shown for example in the following figures.
• the components 5, 8 approached each other until the elevations 20, 21 of the topographic surface structures of the two surfaces 6, 9 touch.
• an electrically conductive contact between the surfaces 6, 9 of the two components 5, 8 is produced.
• the electrical contact resistance is the smaller, the more contact points are produced.
• the thickness 28 of the connecting layer can thereby correspond approximately to the height profile of the topographic surface structures 22, 24, for example, the roughness of the surfaces 6, 9.
• the connecting layer 7 may be formed with trained electrical contact between the components 5, 8 so that the electrically insulating connection medium forming the connection layer, between the elevations 20, 21st located. As a result, a cohesive contact between the components 5, 8 can be ensured.
• the embodiment according to FIG. 3 involves the mounting of a semiconductor chip 13, such as, for example, a thin-film semiconductor chip produced according to methods IA to IF, which is mounted in a surface-mountable component 30.
• the surface-mountable component 30 has a housing 31, for example made of plastic, and a leadframe 32, which allows mounting and electrical contacting of the surface-mountable component 30, for example, on a printed circuit board.
• the semiconductor chip 13 is provided with one side, in the case of the thin-film semiconductor chip according to FIG.
• Embodiment IF with the epitaxial layer sequence 2 side facing away from the carrier substrate 8 to the lead frame 32 within the housing 31 by means of a connecting layer 7 made of an electrically insulating adhesive and electrically and thermally coupled to the lead frame 32.
• the lead frame 32 serves not only as an electrical supply but also as a heat sink in order to dissipate the heat generated in the semiconductor chip 13.
• the heat can be dissipated particularly well.
• connection layers of BCB can be used, as in connection with the method according to the exemplary embodiment of FIGS. 1A to IF, with similar processing parameters.
• the attachment so for example, the placement of a semiconductor chip 13 on a lead frame 32, can take place temporally and spatially separated from the curing of the bonding layer 7.
• a semiconductor chip 13 is shown, which is mounted on a leadframe 32, wherein the leadframe 32, typically a metal strip, has been embossed such that it has depressions 40 for the electrically insulating adhesive of the bonding layer 7.
• the contact pressure exerts pressure on the adhesive applied as the bonding layer 7, so that the thickness of the bonding layer 7 is reduced.
• Excess adhesive from the bonding layer 7 is pressed into the depressions 40 serving as collecting reservoirs for adhesive.
• the adhesive thickness in the joining region 41 is reduced so far that an electrically conductive contact between the semiconductor chip 13 and the lead frame 32 is formed.
• the recesses 40 serving as collecting reservoirs, no displaced, excess adhesive is applied to the semiconductor chip 13 to be mounted, which enables a clean contacting and mounting of the semiconductor chip 13 on the conductor strip 32.
• the semiconductor chip 13 to be mounted according to the exemplary embodiment IF has recesses 40, which serve as collecting reservoirs for adhesive. These depressions 40 can either be provided by the structuring of the side of the carrier substrate 8 facing away from the epitaxial layer sequence 2 or given by the roughness that results from the interaction of a grinding process with a crystallographic etching attack.
• a contacting of the semiconductor chip 13 according to the exemplary embodiment of FIG. 4A or the semiconductor chip 13 according to the exemplary embodiment of FIG. 4B can take place for example on the side of the semiconductor chip facing away from the leadframe by a bonding pad 12.
• a radiation-emitting semiconductor chip 13 is mounted on a transparent substrate 50, which is coated with a layer 51 which comprises or consists of a transparent, electrically conductive oxide ("TCO").
• TCOs are transparent, electrically conductive materials, usually metal oxides, such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide or indium tin oxide (ITO)
• binary metal oxygen compounds such as ZnO, SnO 2 or In 2 O 3 also include ternary metal oxygen compounds, such as Zn 2 SnO 4 , CdSnO 3 , ZnSnO 3 , MgIn 2 O 4 , GaInO 3 , Zn 2 In 2 O 5 or In 4 Sn 3 Oi 2 or mixtures of different transparent conductive oxides to the group of TCOs not necessarily a stoichiometric composition and may also be p- or n-doped
• a bonding layer 7 made of an electrically insulating adhesive which can be
• the semiconductor chip 13 which according to the method of Embodiment of Figures IA to IF may be prepared so arranged on the substrate that the carrier substrate 8 faces the substrate 50.
• the carrier substrate is transparent and has or is made of glass or other transparent material.
• radiation emitted by the semiconductor chip 13 can be emitted through the carrier substrate 8 of the semiconductor chip 13, through the connection layer 7, the layer 51 and the transparent substrate 50.
• the distance between the semiconductor chip and the layer 51 is reduced to such an extent that an electrically conductive contact between the semiconductor chip 8 and the layer 51 as shown in the embodiment of FIG the formation of points of contact between surveys, such as
• the electrically insulating adhesive may be cured with, for example, UV light which can be irradiated from the side of the transparent substrate 50 to the bonding layer 7.
• An electrical contact can be made, for example, via a contact point which has one or more metals or is composed of one or more metals. Such a contact point may be arranged next to the semiconductor chip 13, in particular with a suitable distance from the semiconductor chip, on the layer 51 (not shown).
• the side of the semiconductor chip facing away from the substrate 50 which may for example have a microprism structuring, can be contacted in a similar manner.
• a further transparent substrate 52 be arranged, for example, has glass or glass.
• the transparent substrate 52 may be coated with an electrically conductive layer 53 having a TCO or being made of a TCO.
• An electrically conductive connection of the semiconductor chip 13 with the electrically conductive layer 53 can likewise take place via a connection layer 7.
• a bonding layer 7 of an electrically insulating material such as an electrically insulating adhesive, it may be possible for the regions 54 adjacent to the side surfaces 131, 132 of the semiconductor chip 13 to be filled with the bonding layer material.
• an electrically insulating connection layer material By using an electrically insulating connection layer material, a short circuit of the semiconductor chip can be avoided.
• the substrate 50 may not be transparent and the substrate 52 may be transparent.
• FIG. 6A shows an embodiment which has a first component 5 with two electrical contact regions 51, 52.
• the first component 5, which is shown only in a section, is embodied as an epitaxial layer sequence which can be electrically contacted on one side via the electrical contact regions 51, 52.
• the first component 5 has a continuous first surface 6, which can be electrically connected by the electrical contact regions 51, 52.
• the electrical contact regions 51, 52 have different polarities in the embodiment shown.
• the electrical contact regions 51, 52 can also have the same electrical polarity, so that the electrical connection of the first component only with respect to a Polarity can take place via the structured contact regions 51, 52 on the first surface 6.
• the first surface 6 may have more than two electrical contact areas with the same or different polarities.
• the first component 5 is arranged on a second component 8, which is a carrier with two electrical contact regions 81, 82.
• the carrier can be embodied as a carrier substrate or as a leadframe with a second surface 9 which has electrical contact regions 81, 82 corresponding to the number of electrical contact regions 51, 52 on the first surface 6.
• an electrical contact area on the second surface 9 may also contact more than one electrical contact area on the second surface or vice versa (not shown).
• connection layer 7 which is arranged between the surfaces 6 and 9.
• the connecting layer 7 is designed as in the previous embodiments and has an electrically insulating adhesive, such as BCB.
• connection layer 7 can be continuous and unstructured as in the exemplary embodiment shown and can be used as a continuous layer the electrical contact regions 51, 52, 81, 82 extend. Because the connecting layer is made of an electrically insulating adhesive, a large-area cohesive fastening of the first component 5 on the second component 8 can be achieved without a short circuit between the electrical contact regions 51 and 52 or 81 and 82 would arise.
• the first component 5 and the second component 8 each have raised electrical contact regions 51, 52 and 81, 82, respectively.
• the first component 5 may be, for example, a semiconductor chip for flip-chip mounting, which is applied to a carrier with lead frames 81, 82 as a second component 8.
• the cohesive fastening and the electrical connection of the first component 5 to the second component 8 takes place via connecting layers 7 in the manner described above, which are applied between the respective electrical Maisberiechen 51 and 81 or 52 and 82.
• FIG. 6C shows a further exemplary embodiment in which the connection layer 7 is also arranged between the electrical contact regions 51, 52, 81, 82, in order to enable a better materially bonded attachment of the first component 5 to the second component 8.
• FIG. 6D shows a second component 8 with an additional layer over the electrical contact regions 81, 82 which comprises an insulating material 801, such as an oxide such as SiO 2 , containing metal fillings 811, 812, 821, 822, respectively the electrical contact areas 81 and 82 of the second component 8 contact.
• an insulating material 801 such as an oxide such as SiO 2
• metal fillings 811, 812, 821, 822 respectively the electrical contact areas 81 and 82 of the second component 8 contact.
• the first component 5 such as an epitaxial layer sequence with structured electrical contact areas 51, 52, arranged in the manner described above by means of a connecting layer 7 are electrically connected to the metal fillings 811, 812 and 821, 822 and thus also to the electrical Contact areas 81, 82 of the second component 8.
• the second component 8 may be designed as a substrate with electrical leads 81, 82, over which the layer with the insulating material 801 and the metal fillings 811, 812, 821, 822 is arranged.
• the metal fillings 811, 812, 821, 822 may be surrounded at the interfaces to the material 801 by a layer of an insulating material, so that the material 801 may also be electrically conductive.
• the metal fillings 811, 812, 821, 822 are raised above the material 801, for example in a mushroom structure.
• the electrical contact between the second surface 9 of the metal fillings 811, 812, 821, 822 and the first surface 6 of the electrical contact regions 51 and 52 results in a sufficient reduction of the thickness of the connection layer 7.
• a non-contacting contact of the first component 5 with the second component 8 can thus be achieved.
• the number of metal fillings can differ from the number shown here.
• the first and / or the second component can adjustment elements such as guide parts or edges so that the restrictions on the dimensioning and the arrangement of the metal fillings can be omitted.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Led Device Packages (AREA)
• Wire Bonding (AREA)
• Manufacturing Of Printed Wiring (AREA)
• Combinations Of Printed Boards (AREA)

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• 2006
  • 2006-06-22 DE DE102006028692.8A patent/DE102006028692B4/de active Active
• 2007
  • 2007-05-16 JP JP2009510280A patent/JP5208922B2/ja not_active Expired - Fee Related
  • 2007-05-16 WO PCT/DE2007/000897 patent/WO2007134581A1/de not_active Ceased
  • 2007-05-16 KR KR1020087030710A patent/KR101367545B1/ko active Active
  • 2007-05-16 EP EP07722445A patent/EP2018664A1/de not_active Withdrawn
  • 2007-05-16 US US12/301,566 patent/US8102060B2/en active Active
  • 2007-05-17 TW TW096117569A patent/TWI357639B/zh not_active IP Right Cessation

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