WO2007098303A2 - Noise isolation between circuit blocks in an integrated circuit chip - Google Patents

Noise isolation between circuit blocks in an integrated circuit chip Download PDF

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Publication number
WO2007098303A2
WO2007098303A2 PCT/US2007/060655 US2007060655W WO2007098303A2 WO 2007098303 A2 WO2007098303 A2 WO 2007098303A2 US 2007060655 W US2007060655 W US 2007060655W WO 2007098303 A2 WO2007098303 A2 WO 2007098303A2
Authority
WO
WIPO (PCT)
Prior art keywords
region
block
circuit
circuit block
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/060655
Other languages
English (en)
French (fr)
Other versions
WO2007098303A3 (en
Inventor
Radu M. Secareanu
Suman K. Banerjee
Olin L. Hartin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to EP07756373.2A priority Critical patent/EP1989738B1/en
Priority to CN2007800064463A priority patent/CN101432881B/zh
Priority to JP2008556488A priority patent/JP5301290B2/ja
Publication of WO2007098303A2 publication Critical patent/WO2007098303A2/en
Priority to KR1020087020618A priority patent/KR101342877B1/ko
Anticipated expiration legal-status Critical
Publication of WO2007098303A3 publication Critical patent/WO2007098303A3/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/051—Manufacture or treatment of isolation region based on field-effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/50—Isolation regions based on field-effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • This invention relates in general to integrated circuits and more specifically to noise isolation between circuit blocks in an integrated circuit chip.
  • circuit blocks such as analog and digital circuit blocks. Without proper noise isolation, noise generated by digital circuit blocks can interfere with more sensitive circuit blocks, such as phase locked loops and low noise amplifier circuits. Conventional noise isolation between different types of circuit blocks requires bias. Bias, however, is prone to contamination and thus compromises noise isolation efficiency.
  • Figure 1 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention
  • Figure 2 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention
  • Figure 3 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention
  • Figure 4 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention
  • Figure 5 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention.
  • Figure 6 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention.
  • Figure 7 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention.
  • an integrated circuit including a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block.
  • the integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.
  • an integrated circuit including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block.
  • the integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.
  • the integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block.
  • the integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region.
  • an integrated circuit including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block.
  • the integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.
  • the integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block.
  • the integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region.
  • the integrated circuit further includes a trench formed surrounding the guard region.
  • FIG. 1 is a partial side view of one embodiment of an integrated circuit during a processing stage, consistent with one embodiment of the invention.
  • Integrated circuit 10 may include a substrate 12.
  • Using a mask 14 various circuit blocks may be formed in substrate 12.
  • Circuit blocks may be formed in different regions, such as 16, and 18.
  • Figure 1 shows only one mask layer, additional mask layers may be used as part of the formation of various circuit blocks in substrate 12.
  • Using a part 20 of mask 14 a region of substrate 12 may be processed such that it does not receive any dopants.
  • a first circuit block 22 and a second circuit block 24 may be formed in substrate 12 using various patterning and implanting steps (not shown).
  • a p-well block region 30 may be formed under part 20 of mask 14, for example.
  • P-well block region 30 may provide noise isolation between first circuit block 22 and second circuit block 24.
  • P-well block region 34 may have a high resistivity due to a low doping concentration.
  • p-well block region 30 may have a low doping concentration because insertion of any dopants may be blocked into this region.
  • the doping concentration of p-well block region may be lowered by counter-doping, for example.
  • Guard regions 32 and 34 may be formed surrounding p-well block region 30 for providing additional noise isolation between first circuit block 22 and second circuit block 24.
  • guard regions 32 and 34 may represent areas surrounding p-well block region with an intermediate amount of doping compared to the low-doped p-well block region 30.
  • Guard regions 32 and 34 may not be as highly doped as the p+ doped region, for example.
  • guard regions 32 and 34 may have the same depth as the depth of the p-well block region.
  • a first highly doped region 26 may be formed between guard region 32 and first circuit block 22.
  • a second highly doped region 28 may be formed between guard region 34 and second circuit block 24.
  • First highly doped region 26 and second highly doped region 28 may be grounded.
  • first highly doped region 26 and second highly doped region 28 may be doped using a p-type dopant, such as boron or indium, to achieve a p+ type of doping.
  • Figure 3 shows a top view of a p-well block region 30 formed as a wall between first circuit block 22 and second circuit block 24.
  • Guard regions 32 and 34 may be formed as a ring surrounding the wall shaped p- well block region.
  • First highly doped region 26 may be formed between guard region 32 and first circuit block 22.
  • Second highly doped region 28 may be formed between guard region 34 and second circuit block 24.
  • Figure 4 shows a top view of a p-well region formed 130 as ring formed between first circuit block 122 and second circuit block 124.
  • Guard regions 132 and 134 may be formed as rings surrounding the ring shaped p-well block region 130.
  • First highly doped region 126 may be formed between guard region 132 and first circuit block 122.
  • Second highly doped region 128 may be formed between guard region 134 and second circuit block 124.
  • Figures 3 and 4 show only two exemplary circuit blocks, integrated circuit 10 may include additional circuit blocks with additional noise isolation structures.
  • Figure 5 shows an integrated circuit 100 comprising the same elements as of Figure 2, and further including a dielectric layer 35 formed over at least p-well block region 30 and guard regions 32 and 34.
  • a conductive shield 36 may be formed over dielectric layer 35.
  • Conductive shield 36 may be grounded to provide additional noise isolation between first circuit block 22 and second circuit block 24.
  • Figure 5 shows only one dielectric layer between conductive shield 36 and p-well block region 30, additional layers may be formed between conductive shield 36 and p-well block region 30.
  • an interconnect (not shown) connecting first circuit block 22 to second circuit block 24 may be formed at a greater distance from a top surface of substrate 12 in a region directly above p-well block region 30 than other regions above substrate 12.
  • conductive shield 36 may be positioned such that an area occupied by conductive shield 36 over first circuit block 22 is different from an area occupied by the conductive shield 36 over second circuit block 24. This may be achieved for example, by altering one or both of the length and the width of conductive shield 36.
  • at least one interconnect may be positioned such that an area occupied by the at least one interconnect over first circuit block 22 is different from an area occupied by the at least one interconnect over second circuit block 24. This may be achieved for example, by altering one or both of length and width of the at least one interconnect.
  • Figure 6 shows an integrated device 110 having trenches 40 and 42, in addition to the elements of integrated circuit 10 of Figure 2. Trenches 40 and 42 may provide additional noise isolation between first circuit block 22 and second circuit block 24. Although Figure 6 shows trenches 40 and 42 extending beyond guard regions 32 and 34, trenches 40 and 42 may be only as deep as guard regions 32 and 34, respectively.
  • Figure 7 shows an integrated device 120 having a dielectric layer 35 and a conductive shield 36, in addition to elements of integrated circuit 110 of Figure 6.
  • Conductive shield 36 may be grounded to provide additional noise isolation between first circuit block 22 and second circuit block 24.
  • Figure 5 shows only one dielectric layer between conductive shield 36 and p-well block region 30, additional layers may be formed between conductive shield 36 and p-well block region 30.
  • an interconnect (not shown) connecting first circuit block 22 to second circuit block 24 may be formed at a greater distance from a top surface of substrate 12 in a region directly above p-well block region 30 than other regions above substrate 12.
  • conductive shield 36 may be positioned such that an area occupied by conductive shield 36 over first circuit block 22 is different from an area occupied by the conductive shield 36 over second circuit block 24. This may be achieved for example, by altering one or both of length and width of conductive shield 36.
  • at least one interconnect may be positioned such that an area occupied by the at least one interconnect over first circuit block 22 is different from an area occupied by the at least one interconnect over second circuit block 24. This may be achieved for example, by altering one or both of the length and the width of the at least one interconnect.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/US2007/060655 2006-02-23 2007-01-18 Noise isolation between circuit blocks in an integrated circuit chip Ceased WO2007098303A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07756373.2A EP1989738B1 (en) 2006-02-23 2007-01-18 Noise isolation between circuit blocks in an integrated circuit chip
CN2007800064463A CN101432881B (zh) 2006-02-23 2007-01-18 集成电路芯片中电路模块间的噪声隔离
JP2008556488A JP5301290B2 (ja) 2006-02-23 2007-01-18 集積回路チップにおける回路ブロック間のノイズ分離
KR1020087020618A KR101342877B1 (ko) 2006-02-23 2008-08-22 집적 회로 칩에서 회로 블록들간의 노이즈 고립

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/360,285 US7608913B2 (en) 2006-02-23 2006-02-23 Noise isolation between circuit blocks in an integrated circuit chip
US11/360,285 2006-02-23

Publications (2)

Publication Number Publication Date
WO2007098303A2 true WO2007098303A2 (en) 2007-08-30
WO2007098303A3 WO2007098303A3 (en) 2009-01-29

Family

ID=38427330

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/060655 Ceased WO2007098303A2 (en) 2006-02-23 2007-01-18 Noise isolation between circuit blocks in an integrated circuit chip

Country Status (7)

Country Link
US (3) US7608913B2 (https=)
EP (1) EP1989738B1 (https=)
JP (1) JP5301290B2 (https=)
KR (1) KR101342877B1 (https=)
CN (1) CN101432881B (https=)
TW (1) TWI427762B (https=)
WO (1) WO2007098303A2 (https=)

Cited By (1)

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JP2019197603A (ja) * 2018-05-08 2019-11-14 東芝メモリ株式会社 半導体記憶装置

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KR102442933B1 (ko) * 2017-08-21 2022-09-15 삼성전자주식회사 3차원 반도체 장치
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JP2022516495A (ja) * 2018-12-29 2022-02-28 華為技術有限公司 信号分離装置及び信号分離方法
US20240388309A1 (en) * 2022-10-26 2024-11-21 Radu Mircea Secareanu Binary Data Compression / Decompression Method

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Also Published As

Publication number Publication date
TW200802795A (en) 2008-01-01
EP1989738A2 (en) 2008-11-12
EP1989738A4 (en) 2012-07-25
EP1989738B1 (en) 2015-03-11
US20090302440A1 (en) 2009-12-10
US20070194394A1 (en) 2007-08-23
KR20080109731A (ko) 2008-12-17
US20130207229A1 (en) 2013-08-15
KR101342877B1 (ko) 2013-12-19
CN101432881A (zh) 2009-05-13
JP2009527927A (ja) 2009-07-30
US7608913B2 (en) 2009-10-27
JP5301290B2 (ja) 2013-09-25
TWI427762B (zh) 2014-02-21
CN101432881B (zh) 2010-12-08
US9048110B2 (en) 2015-06-02
WO2007098303A3 (en) 2009-01-29

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