US20090302440A1 - Noise isolation between circuit blocks in an integrated circuit chip - Google Patents
Noise isolation between circuit blocks in an integrated circuit chip Download PDFInfo
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- US20090302440A1 US20090302440A1 US12/512,616 US51261609A US2009302440A1 US 20090302440 A1 US20090302440 A1 US 20090302440A1 US 51261609 A US51261609 A US 51261609A US 2009302440 A1 US2009302440 A1 US 2009302440A1
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- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000002019 doping agent Substances 0.000 claims description 11
- 230000008901 benefit Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Definitions
- Embodiments relate in general to integrated circuits and more specifically to noise isolation between circuit blocks in an integrated circuit chip.
- circuit blocks such as analog and digital circuit blocks. Without proper noise isolation, noise generated by digital circuit blocks can interfere with more sensitive circuit blocks, such as phase locked loops and low noise amplifier circuits. Conventional noise isolation between different types of circuit blocks requires bias. Bias, however, is prone to contamination and thus compromises noise isolation efficiency.
- FIG. 1 is a partial side view of an embodiment of an integrated circuit during a processing stage
- FIG. 2 is a partial side view of an embodiment of an integrated circuit during a processing stage
- FIG. 3 is a partial side view of an embodiment of an integrated circuit during a processing stage
- FIG. 4 is a partial side view of an embodiment of an integrated circuit during a processing stage
- FIG. 5 is a partial side view of an embodiment of an integrated circuit during a processing stage
- FIG. 6 is a partial side view of an embodiment of an integrated circuit during a processing stage.
- FIG. 7 is a partial side view of an embodiment of an integrated circuit during a processing stage.
- an integrated circuit including a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block.
- the integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block.
- an integrated circuit including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block.
- the integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block.
- the integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block.
- the integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region.
- an integrated circuit including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block.
- the integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block.
- the integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block.
- the integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region.
- the integrated circuit further includes a trench formed between the p-well block region and the guard region.
- FIG. 1 is a partial side view of an embodiment of an integrated circuit during a processing stage.
- Integrated circuit 10 may include a substrate 12 .
- various circuit blocks may be formed in substrate 12 .
- Circuit blocks may be formed in different regions, such as 16 , and 18 .
- FIG. 1 shows only one mask layer, additional mask layers may be used as part of the formation of various circuit blocks in substrate 12 .
- Using a part 20 of mask 14 a region of substrate 12 may be processed such that it does not receive any dopants.
- a first circuit block 22 and a second circuit block 24 may be formed in substrate 12 using various patterning and implanting steps (not shown).
- a p-well block region 30 may be formed under part 20 of mask 14 , for example.
- P-well block region 30 may provide noise isolation between first circuit block 22 and second circuit block 24 .
- P-well block region 30 may have a high resistivity due to a low doping concentration.
- p-well block region 30 may have a low doping concentration because insertion of any dopants may be blocked into this region.
- the doping concentration of p-well block region 30 may be lowered by counter-doping, for example.
- Guard regions 32 and 34 may be formed surrounding p-well block region 30 for providing additional noise isolation between first circuit block 22 and second circuit block 24 .
- guard regions 32 and 34 may represent areas surrounding p-well block region 30 with an intermediate amount of doping compared to the low-doped p-well block region 30 .
- Guard regions 32 and 34 may not be as highly doped as the p+ doped regions 26 , 28 , for example.
- guard regions 32 and 34 may have the same depth as the depth of the p-well block region 30 .
- a first highly doped region 26 may be formed between guard region 32 and first circuit block 22 .
- a second highly doped region 28 may be formed between guard region 34 and second circuit block 24 .
- First highly doped region 26 and second highly doped region 28 may be grounded.
- first highly doped region 26 and second highly doped region 28 may be doped using a p-type dopant, such as boron or indium, to achieve a p+ type of doping.
- FIG. 3 shows a top view of a p-well block region 30 formed as a wall between first circuit block 22 and second circuit block 24 .
- Guard regions 32 and 34 may be formed as a ring surrounding the wall shaped p-well block region.
- First highly doped region 26 may be formed between guard region 32 and first circuit block 22 .
- Second highly doped region 28 may be formed between guard region 34 and second circuit block 24 .
- FIG. 4 shows a top view of a p-well region formed 130 as ring formed between first circuit block 122 and second circuit block 124 .
- Guard regions 132 and 134 may be formed as rings surrounding the ring shaped p-well block region 130 .
- First highly doped region 126 may be formed between guard region 132 and first circuit block 122 .
- Second highly doped region 128 may be formed between guard region 134 and second circuit block 124 .
- FIGS. 3 and 4 show only two exemplary circuit blocks, integrated circuit 10 may include additional circuit blocks with additional noise isolation structures.
- FIG. 5 shows an integrated circuit 100 comprising the same elements as of FIG. 2 , and further including a dielectric layer 35 formed over at least p-well block region 30 and guard regions 32 and 34 .
- a conductive shield 36 may be formed over dielectric layer 35 .
- Conductive shield 36 may be grounded to provide additional noise isolation between first circuit block 22 and second circuit block 24 .
- FIG. 5 shows only one dielectric layer between conductive shield 36 and p-well block region 30 , additional layers may be formed between conductive shield 36 and p-well block region 30 .
- an interconnect (not shown) connecting first circuit block 22 to second circuit block 24 may be formed at a greater distance from a top surface of substrate 12 in a region directly above p-well block region 30 than other regions above substrate 12 .
- conductive shield 36 may be positioned such that an area occupied by conductive shield 36 over first circuit block 22 is different from an area occupied by the conductive shield 36 over second circuit block 24 . This may be achieved for example, by altering one or both of the length and the width of conductive shield 36 .
- at least one interconnect may be positioned such that an area occupied by the at least one interconnect over first circuit block 22 is different from an area occupied by the at least one interconnect over second circuit block 24 . This may be achieved for example, by altering one or both of length and width of the at least one interconnect.
- FIG. 6 shows an integrated device 110 having trenches 40 and 42 , in addition to the elements of integrated circuit 10 of FIG. 2 .
- Trenches 40 and 42 may provide additional noise isolation between first circuit block 22 and second circuit block 24 .
- FIG. 6 shows trenches 40 and 42 extending beyond guard regions 32 and 34 , trenches 40 and 42 may be only as deep as guard regions 32 and 34 , respectively.
- FIG. 7 shows an integrated device 120 having a dielectric layer 35 and a conductive shield 36 , in addition to elements of integrated circuit 110 of FIG. 6 .
- Conductive shield 36 may be grounded to provide additional noise isolation between first circuit block 22 and second circuit block 24 .
- FIG. 5 shows only one dielectric layer between conductive shield 36 and p-well block region 30 , additional layers may be formed between conductive shield 36 and p-well block region 30 .
- an interconnect (not shown) connecting first circuit block 22 to second circuit block 24 may be formed at a greater distance from a top surface of substrate 12 in a region directly above p-well block region 30 than other regions above substrate 12 .
- conductive shield 36 may be positioned such that an area occupied by conductive shield 36 over first circuit block 22 is different from an area occupied by the conductive shield 36 over second circuit block 24 . This may be achieved for example, by altering one or both of length and width of conductive shield 36 .
- at least one interconnect may be positioned such that an area occupied by the at least one interconnect over first circuit block 22 is different from an area occupied by the at least one interconnect over second circuit block 24 . This may be achieved for example, by altering one or both of the length and the width of the at least one interconnect.
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Abstract
Description
- This application is a divisional of co-pending U.S. patent application Ser. No. 11/360,285, filed on Feb. 23, 2006.
- Embodiments relate in general to integrated circuits and more specifically to noise isolation between circuit blocks in an integrated circuit chip.
- Increasingly, integrated circuit chips have different types of circuit blocks, such as analog and digital circuit blocks. Without proper noise isolation, noise generated by digital circuit blocks can interfere with more sensitive circuit blocks, such as phase locked loops and low noise amplifier circuits. Conventional noise isolation between different types of circuit blocks requires bias. Bias, however, is prone to contamination and thus compromises noise isolation efficiency.
- Thus, there is a need for improved noise isolation between circuit blocks in an integrated circuit chip.
- Embodiments of the inventive subject matter may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
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FIG. 1 is a partial side view of an embodiment of an integrated circuit during a processing stage; -
FIG. 2 is a partial side view of an embodiment of an integrated circuit during a processing stage; -
FIG. 3 is a partial side view of an embodiment of an integrated circuit during a processing stage; -
FIG. 4 is a partial side view of an embodiment of an integrated circuit during a processing stage; -
FIG. 5 is a partial side view of an embodiment of an integrated circuit during a processing stage; -
FIG. 6 is a partial side view of an embodiment of an integrated circuit during a processing stage; and -
FIG. 7 is a partial side view of an embodiment of an integrated circuit during a processing stage. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments.
- The following sets forth a detailed description of a mode for carrying out the embodiments of the inventive subject matter. The description is intended to be illustrative of the embodiments and should not be taken to be limiting.
- In one aspect, an integrated circuit, including a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block, is provided. The integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block.
- In another aspect, an integrated circuit, including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block, is provided. The integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block. The integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block. The integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region.
- In yet another aspect, an integrated circuit including a p-well block region formed in a substrate by blocking insertion of any dopants in a region of the substrate for providing noise isolation between a first circuit block and a second circuit block, is provided. The integrated circuit further includes a guard region for providing noise isolation between the first circuit block and the second circuit block. The integrated circuit further includes a first grounded highly doped region formed between the guard region and the first circuit block and a second grounded highly doped region formed between the guard region and the second circuit block. The integrated circuit further includes a grounded conductive shield formed over a dielectric layer formed at least over the p-well block region and the guard region. The integrated circuit further includes a trench formed between the p-well block region and the guard region.
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FIG. 1 is a partial side view of an embodiment of an integrated circuit during a processing stage.Integrated circuit 10 may include asubstrate 12. Using amask 14 various circuit blocks may be formed insubstrate 12. Circuit blocks may be formed in different regions, such as 16, and 18. AlthoughFIG. 1 shows only one mask layer, additional mask layers may be used as part of the formation of various circuit blocks insubstrate 12. Using apart 20 of mask 14 a region ofsubstrate 12 may be processed such that it does not receive any dopants. - Referring now to
FIG. 2 , afirst circuit block 22 and asecond circuit block 24 may be formed insubstrate 12 using various patterning and implanting steps (not shown). A p-well block region 30 may be formed underpart 20 ofmask 14, for example. P-well block region 30 may provide noise isolation betweenfirst circuit block 22 andsecond circuit block 24. P-well block region 30 may have a high resistivity due to a low doping concentration. By way of example, p-wellblock region 30 may have a low doping concentration because insertion of any dopants may be blocked into this region. Alternatively, the doping concentration of p-well block region 30 may be lowered by counter-doping, for example.Guard regions well block region 30 for providing additional noise isolation betweenfirst circuit block 22 andsecond circuit block 24. By way of example,guard regions block region 30 with an intermediate amount of doping compared to the low-doped p-well block region 30.Guard regions regions guard regions well block region 30. To provide additional noise isolation a first highlydoped region 26 may be formed betweenguard region 32 andfirst circuit block 22. A second highlydoped region 28 may be formed betweenguard region 34 andsecond circuit block 24. First highly dopedregion 26 and second highlydoped region 28 may be grounded. By way of example, first highly dopedregion 26 and second highlydoped region 28 may be doped using a p-type dopant, such as boron or indium, to achieve a p+ type of doping. -
FIG. 3 , consistent with an embodiment, shows a top view of a p-well block region 30 formed as a wall betweenfirst circuit block 22 andsecond circuit block 24.Guard regions region 26 may be formed betweenguard region 32 andfirst circuit block 22. Second highlydoped region 28 may be formed betweenguard region 34 andsecond circuit block 24. -
FIG. 4 , consistent with another embodiment, shows a top view of a p-well region formed 130 as ring formed betweenfirst circuit block 122 andsecond circuit block 124.Guard regions well block region 130. First highlydoped region 126 may be formed betweenguard region 132 andfirst circuit block 122. Second highlydoped region 128 may be formed betweenguard region 134 andsecond circuit block 124. AlthoughFIGS. 3 and 4 show only two exemplary circuit blocks, integratedcircuit 10 may include additional circuit blocks with additional noise isolation structures. - Referring now to
FIG. 5 ,FIG. 5 shows anintegrated circuit 100 comprising the same elements as ofFIG. 2 , and further including adielectric layer 35 formed over at least p-well block region 30 andguard regions conductive shield 36 may be formed overdielectric layer 35.Conductive shield 36 may be grounded to provide additional noise isolation betweenfirst circuit block 22 andsecond circuit block 24. AlthoughFIG. 5 shows only one dielectric layer betweenconductive shield 36 and p-well block region 30, additional layers may be formed betweenconductive shield 36 and p-well block region 30. Further, an interconnect (not shown) connectingfirst circuit block 22 tosecond circuit block 24 may be formed at a greater distance from a top surface ofsubstrate 12 in a region directly above p-well block region 30 than other regions abovesubstrate 12. Additionally,conductive shield 36 may be positioned such that an area occupied byconductive shield 36 overfirst circuit block 22 is different from an area occupied by theconductive shield 36 oversecond circuit block 24. This may be achieved for example, by altering one or both of the length and the width ofconductive shield 36. Additionally and/or alternatively, at least one interconnect may be positioned such that an area occupied by the at least one interconnect overfirst circuit block 22 is different from an area occupied by the at least one interconnect oversecond circuit block 24. This may be achieved for example, by altering one or both of length and width of the at least one interconnect. - Referring now to
FIG. 6 ,FIG. 6 shows anintegrated device 110 havingtrenches integrated circuit 10 ofFIG. 2 .Trenches first circuit block 22 andsecond circuit block 24. AlthoughFIG. 6 showstrenches guard regions trenches guard regions -
FIG. 7 shows anintegrated device 120 having adielectric layer 35 and aconductive shield 36, in addition to elements ofintegrated circuit 110 ofFIG. 6 .Conductive shield 36 may be grounded to provide additional noise isolation betweenfirst circuit block 22 andsecond circuit block 24. AlthoughFIG. 5 shows only one dielectric layer betweenconductive shield 36 and p-well block region 30, additional layers may be formed betweenconductive shield 36 and p-well block region 30. Further, an interconnect (not shown) connectingfirst circuit block 22 tosecond circuit block 24 may be formed at a greater distance from a top surface ofsubstrate 12 in a region directly above p-well block region 30 than other regions abovesubstrate 12. Additionally,conductive shield 36 may be positioned such that an area occupied byconductive shield 36 overfirst circuit block 22 is different from an area occupied by theconductive shield 36 oversecond circuit block 24. This may be achieved for example, by altering one or both of length and width ofconductive shield 36. Additionally and/or alternatively, at least one interconnect may be positioned such that an area occupied by the at least one interconnect overfirst circuit block 22 is different from an area occupied by the at least one interconnect oversecond circuit block 24. This may be achieved for example, by altering one or both of the length and the width of the at least one interconnect. - In the foregoing specification, specific embodiments have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the inventive subject matter as set forth in the claims below. For example, although the p-well block region has been described as placed between two circuit blocks to provide noise isolation between the two circuit blocks, p-well block region may also be placed between ESD pads or digital pads. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the inventive subject matter.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims (20)
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Application Number | Priority Date | Filing Date | Title |
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US12/512,616 US20090302440A1 (en) | 2006-02-23 | 2009-07-30 | Noise isolation between circuit blocks in an integrated circuit chip |
US13/802,006 US9048110B2 (en) | 2006-02-23 | 2013-03-13 | Noise isolation between circuit blocks in an integrated circuit chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US11/360,285 US7608913B2 (en) | 2006-02-23 | 2006-02-23 | Noise isolation between circuit blocks in an integrated circuit chip |
US12/512,616 US20090302440A1 (en) | 2006-02-23 | 2009-07-30 | Noise isolation between circuit blocks in an integrated circuit chip |
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US11/360,285 Division US7608913B2 (en) | 2006-02-23 | 2006-02-23 | Noise isolation between circuit blocks in an integrated circuit chip |
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US13/802,006 Division US9048110B2 (en) | 2006-02-23 | 2013-03-13 | Noise isolation between circuit blocks in an integrated circuit chip |
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US11/360,285 Active 2027-04-04 US7608913B2 (en) | 2006-02-23 | 2006-02-23 | Noise isolation between circuit blocks in an integrated circuit chip |
US12/512,616 Abandoned US20090302440A1 (en) | 2006-02-23 | 2009-07-30 | Noise isolation between circuit blocks in an integrated circuit chip |
US13/802,006 Active 2026-05-22 US9048110B2 (en) | 2006-02-23 | 2013-03-13 | Noise isolation between circuit blocks in an integrated circuit chip |
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EP (1) | EP1989738B1 (en) |
JP (1) | JP5301290B2 (en) |
KR (1) | KR101342877B1 (en) |
CN (1) | CN101432881B (en) |
TW (1) | TWI427762B (en) |
WO (1) | WO2007098303A2 (en) |
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US20220028731A1 (en) * | 2017-08-21 | 2022-01-27 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor device |
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US7881679B1 (en) | 2007-03-14 | 2011-02-01 | Rf Micro Devices, Inc. | Method and apparatus for integrating power amplifiers with phase locked loop in a single chip transceiver |
US9202760B2 (en) * | 2012-06-26 | 2015-12-01 | Infineon Technologies Ag | Semiconductor devices and structures |
US8957496B2 (en) | 2013-04-17 | 2015-02-17 | Freescale Semiconductor, Inc. | Integrated circuit chip with discontinuous guard ring |
JP7091130B2 (en) * | 2018-05-08 | 2022-06-27 | キオクシア株式会社 | Semiconductor storage device |
US10615252B2 (en) | 2018-08-06 | 2020-04-07 | Nxp Usa, Inc. | Device isolation |
WO2020133530A1 (en) * | 2018-12-29 | 2020-07-02 | 华为技术有限公司 | Signal isolation apparatus and signal isolation method |
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TWI427762B (en) | 2014-02-21 |
EP1989738B1 (en) | 2015-03-11 |
JP5301290B2 (en) | 2013-09-25 |
KR101342877B1 (en) | 2013-12-19 |
EP1989738A4 (en) | 2012-07-25 |
JP2009527927A (en) | 2009-07-30 |
WO2007098303A3 (en) | 2009-01-29 |
US20070194394A1 (en) | 2007-08-23 |
TW200802795A (en) | 2008-01-01 |
US20130207229A1 (en) | 2013-08-15 |
US7608913B2 (en) | 2009-10-27 |
EP1989738A2 (en) | 2008-11-12 |
CN101432881A (en) | 2009-05-13 |
US9048110B2 (en) | 2015-06-02 |
WO2007098303A2 (en) | 2007-08-30 |
KR20080109731A (en) | 2008-12-17 |
CN101432881B (en) | 2010-12-08 |
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