TWI427762B - 積體電路晶片中電路區塊間之雜訊隔離 - Google Patents

積體電路晶片中電路區塊間之雜訊隔離 Download PDF

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Publication number
TWI427762B
TWI427762B TW096103125A TW96103125A TWI427762B TW I427762 B TWI427762 B TW I427762B TW 096103125 A TW096103125 A TW 096103125A TW 96103125 A TW96103125 A TW 96103125A TW I427762 B TWI427762 B TW I427762B
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TW
Taiwan
Prior art keywords
region
circuit block
block
circuit
integrated circuit
Prior art date
Application number
TW096103125A
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English (en)
Chinese (zh)
Other versions
TW200802795A (en
Inventor
席凱瑞努 拉杜M
班奈及 蘇曼K
哈汀 歐琳L
Original Assignee
飛思卡爾半導體公司
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Filing date
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Application filed by 飛思卡爾半導體公司 filed Critical 飛思卡爾半導體公司
Publication of TW200802795A publication Critical patent/TW200802795A/zh
Application granted granted Critical
Publication of TWI427762B publication Critical patent/TWI427762B/zh

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30Devices controlled by electric currents or voltages
    • H10D48/32Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36Unipolar devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/031Manufacture or treatment of isolation regions comprising PN junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/051Manufacture or treatment of isolation region based on field-effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30Isolation regions comprising PN junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/50Isolation regions based on field-effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151Manufacturing their isolation regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW096103125A 2006-02-23 2007-01-29 積體電路晶片中電路區塊間之雜訊隔離 TWI427762B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/360,285 US7608913B2 (en) 2006-02-23 2006-02-23 Noise isolation between circuit blocks in an integrated circuit chip

Publications (2)

Publication Number Publication Date
TW200802795A TW200802795A (en) 2008-01-01
TWI427762B true TWI427762B (zh) 2014-02-21

Family

ID=38427330

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096103125A TWI427762B (zh) 2006-02-23 2007-01-29 積體電路晶片中電路區塊間之雜訊隔離

Country Status (7)

Country Link
US (3) US7608913B2 (https=)
EP (1) EP1989738B1 (https=)
JP (1) JP5301290B2 (https=)
KR (1) KR101342877B1 (https=)
CN (1) CN101432881B (https=)
TW (1) TWI427762B (https=)
WO (1) WO2007098303A2 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7881679B1 (en) * 2007-03-14 2011-02-01 Rf Micro Devices, Inc. Method and apparatus for integrating power amplifiers with phase locked loop in a single chip transceiver
US9202760B2 (en) * 2012-06-26 2015-12-01 Infineon Technologies Ag Semiconductor devices and structures
US8957496B2 (en) 2013-04-17 2015-02-17 Freescale Semiconductor, Inc. Integrated circuit chip with discontinuous guard ring
KR102442933B1 (ko) * 2017-08-21 2022-09-15 삼성전자주식회사 3차원 반도체 장치
JP7091130B2 (ja) * 2018-05-08 2022-06-27 キオクシア株式会社 半導体記憶装置
US10615252B2 (en) 2018-08-06 2020-04-07 Nxp Usa, Inc. Device isolation
JP2022516495A (ja) * 2018-12-29 2022-02-28 華為技術有限公司 信号分離装置及び信号分離方法
US20240388309A1 (en) * 2022-10-26 2024-11-21 Radu Mircea Secareanu Binary Data Compression / Decompression Method

Citations (4)

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US5475255A (en) * 1994-06-30 1995-12-12 Motorola Inc. Circuit die having improved substrate noise isolation
US6424022B1 (en) * 2000-03-12 2002-07-23 Mobilink Telecom, Inc. Guard mesh for noise isolation in highly integrated circuits
US20040142528A1 (en) * 2001-08-30 2004-07-22 Micron Technology, Inc. Decoupling capacitor for high frequency noise immunity
US7071530B1 (en) * 2005-01-27 2006-07-04 International Business Machines Corporation Multiple layer structure for substrate noise isolation

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JPS5772376A (en) * 1980-10-24 1982-05-06 Hitachi Ltd Protective circuit device for semiconductor
JPS61214550A (ja) * 1985-03-20 1986-09-24 Hitachi Ltd 半導体装置
US4853759A (en) * 1986-09-29 1989-08-01 American Microsystems, Inc. Integrated circuit filter with reduced die area
JP3036752B2 (ja) * 1988-12-21 2000-04-24 九州日本電気株式会社 半導体装置
US5196920A (en) 1992-04-21 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks
JP3251735B2 (ja) * 1992-09-25 2002-01-28 株式会社東芝 半導体集積回路装置
US5623159A (en) * 1994-10-03 1997-04-22 Motorola, Inc. Integrated circuit isolation structure for suppressing high-frequency cross-talk
JP3077592B2 (ja) * 1996-06-27 2000-08-14 日本電気株式会社 デジタル回路とアナログ回路が混在する半導体集積回路装置およびその製造方法
GB2341272B (en) * 1998-09-03 2003-08-20 Ericsson Telefon Ab L M High voltage shield
US6479869B1 (en) * 1999-10-01 2002-11-12 Rohm Co., Ltd. Semiconductor device with enhanced protection from electrostatic breakdown
JP4424830B2 (ja) * 2000-06-30 2010-03-03 Okiセミコンダクタ株式会社 半導体装置
JP3834212B2 (ja) * 2001-05-22 2006-10-18 Necエレクトロニクス株式会社 半導体集積回路装置
WO2003005449A1 (en) 2001-07-03 2003-01-16 Tripath Technology, Inc. Substrate connection in an integrated power circuit
US6563181B1 (en) * 2001-11-02 2003-05-13 Motorola, Inc. High frequency signal isolation in a semiconductor device
US6747294B1 (en) * 2002-09-25 2004-06-08 Polarfab Llc Guard ring structure for reducing crosstalk and latch-up in integrated circuits
US6744112B2 (en) 2002-10-01 2004-06-01 International Business Machines Corporation Multiple chip guard rings for integrated circuit and chip guard ring interconnect
US7052939B2 (en) 2002-11-26 2006-05-30 Freescale Semiconductor, Inc. Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
US6787409B2 (en) 2002-11-26 2004-09-07 Mosel Vitelic, Inc. Method of forming trench isolation without grooving
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Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US5475255A (en) * 1994-06-30 1995-12-12 Motorola Inc. Circuit die having improved substrate noise isolation
US6424022B1 (en) * 2000-03-12 2002-07-23 Mobilink Telecom, Inc. Guard mesh for noise isolation in highly integrated circuits
US20040142528A1 (en) * 2001-08-30 2004-07-22 Micron Technology, Inc. Decoupling capacitor for high frequency noise immunity
US7071530B1 (en) * 2005-01-27 2006-07-04 International Business Machines Corporation Multiple layer structure for substrate noise isolation

Also Published As

Publication number Publication date
TW200802795A (en) 2008-01-01
EP1989738A2 (en) 2008-11-12
EP1989738A4 (en) 2012-07-25
EP1989738B1 (en) 2015-03-11
US20090302440A1 (en) 2009-12-10
US20070194394A1 (en) 2007-08-23
KR20080109731A (ko) 2008-12-17
US20130207229A1 (en) 2013-08-15
KR101342877B1 (ko) 2013-12-19
WO2007098303A2 (en) 2007-08-30
CN101432881A (zh) 2009-05-13
JP2009527927A (ja) 2009-07-30
US7608913B2 (en) 2009-10-27
JP5301290B2 (ja) 2013-09-25
CN101432881B (zh) 2010-12-08
US9048110B2 (en) 2015-06-02
WO2007098303A3 (en) 2009-01-29

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