KR101342877B1 - 집적 회로 칩에서 회로 블록들간의 노이즈 고립 - Google Patents

집적 회로 칩에서 회로 블록들간의 노이즈 고립 Download PDF

Info

Publication number
KR101342877B1
KR101342877B1 KR1020087020618A KR20087020618A KR101342877B1 KR 101342877 B1 KR101342877 B1 KR 101342877B1 KR 1020087020618 A KR1020087020618 A KR 1020087020618A KR 20087020618 A KR20087020618 A KR 20087020618A KR 101342877 B1 KR101342877 B1 KR 101342877B1
Authority
KR
South Korea
Prior art keywords
region
block
circuit block
circuit
delete delete
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020087020618A
Other languages
English (en)
Korean (ko)
Other versions
KR20080109731A (ko
Inventor
라두 엠. 시카리안
수만 케이. 바네르지
올린 엘. 하틴
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20080109731A publication Critical patent/KR20080109731A/ko
Application granted granted Critical
Publication of KR101342877B1 publication Critical patent/KR101342877B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/051—Manufacture or treatment of isolation region based on field-effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/50—Isolation regions based on field-effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020087020618A 2006-02-23 2008-08-22 집적 회로 칩에서 회로 블록들간의 노이즈 고립 Active KR101342877B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/360,285 US7608913B2 (en) 2006-02-23 2006-02-23 Noise isolation between circuit blocks in an integrated circuit chip
US11/360,285 2006-02-23
PCT/US2007/060655 WO2007098303A2 (en) 2006-02-23 2007-01-18 Noise isolation between circuit blocks in an integrated circuit chip

Publications (2)

Publication Number Publication Date
KR20080109731A KR20080109731A (ko) 2008-12-17
KR101342877B1 true KR101342877B1 (ko) 2013-12-19

Family

ID=38427330

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087020618A Active KR101342877B1 (ko) 2006-02-23 2008-08-22 집적 회로 칩에서 회로 블록들간의 노이즈 고립

Country Status (7)

Country Link
US (3) US7608913B2 (https=)
EP (1) EP1989738B1 (https=)
JP (1) JP5301290B2 (https=)
KR (1) KR101342877B1 (https=)
CN (1) CN101432881B (https=)
TW (1) TWI427762B (https=)
WO (1) WO2007098303A2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7881679B1 (en) * 2007-03-14 2011-02-01 Rf Micro Devices, Inc. Method and apparatus for integrating power amplifiers with phase locked loop in a single chip transceiver
US9202760B2 (en) * 2012-06-26 2015-12-01 Infineon Technologies Ag Semiconductor devices and structures
US8957496B2 (en) 2013-04-17 2015-02-17 Freescale Semiconductor, Inc. Integrated circuit chip with discontinuous guard ring
KR102442933B1 (ko) * 2017-08-21 2022-09-15 삼성전자주식회사 3차원 반도체 장치
JP7091130B2 (ja) * 2018-05-08 2022-06-27 キオクシア株式会社 半導体記憶装置
US10615252B2 (en) 2018-08-06 2020-04-07 Nxp Usa, Inc. Device isolation
JP2022516495A (ja) * 2018-12-29 2022-02-28 華為技術有限公司 信号分離装置及び信号分離方法
US20240388309A1 (en) * 2022-10-26 2024-11-21 Radu Mircea Secareanu Binary Data Compression / Decompression Method

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5772376A (en) * 1980-10-24 1982-05-06 Hitachi Ltd Protective circuit device for semiconductor
JPS61214550A (ja) * 1985-03-20 1986-09-24 Hitachi Ltd 半導体装置
US4853759A (en) * 1986-09-29 1989-08-01 American Microsystems, Inc. Integrated circuit filter with reduced die area
JP3036752B2 (ja) * 1988-12-21 2000-04-24 九州日本電気株式会社 半導体装置
US5196920A (en) 1992-04-21 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks
JP3251735B2 (ja) * 1992-09-25 2002-01-28 株式会社東芝 半導体集積回路装置
US5475255A (en) * 1994-06-30 1995-12-12 Motorola Inc. Circuit die having improved substrate noise isolation
US5623159A (en) * 1994-10-03 1997-04-22 Motorola, Inc. Integrated circuit isolation structure for suppressing high-frequency cross-talk
JP3077592B2 (ja) * 1996-06-27 2000-08-14 日本電気株式会社 デジタル回路とアナログ回路が混在する半導体集積回路装置およびその製造方法
GB2341272B (en) * 1998-09-03 2003-08-20 Ericsson Telefon Ab L M High voltage shield
US6424022B1 (en) * 2000-03-12 2002-07-23 Mobilink Telecom, Inc. Guard mesh for noise isolation in highly integrated circuits
US6479869B1 (en) * 1999-10-01 2002-11-12 Rohm Co., Ltd. Semiconductor device with enhanced protection from electrostatic breakdown
JP4424830B2 (ja) * 2000-06-30 2010-03-03 Ｏｋｉセミコンダクタ株式会社 半導体装置
JP3834212B2 (ja) * 2001-05-22 2006-10-18 Ｎｅｃエレクトロニクス株式会社 半導体集積回路装置
WO2003005449A1 (en) 2001-07-03 2003-01-16 Tripath Technology, Inc. Substrate connection in an integrated power circuit
US6700771B2 (en) 2001-08-30 2004-03-02 Micron Technology, Inc. Decoupling capacitor for high frequency noise immunity
US6563181B1 (en) * 2001-11-02 2003-05-13 Motorola, Inc. High frequency signal isolation in a semiconductor device
US6747294B1 (en) * 2002-09-25 2004-06-08 Polarfab Llc Guard ring structure for reducing crosstalk and latch-up in integrated circuits
US6744112B2 (en) 2002-10-01 2004-06-01 International Business Machines Corporation Multiple chip guard rings for integrated circuit and chip guard ring interconnect
US7052939B2 (en) 2002-11-26 2006-05-30 Freescale Semiconductor, Inc. Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
US6787409B2 (en) 2002-11-26 2004-09-07 Mosel Vitelic, Inc. Method of forming trench isolation without grooving
US6900969B2 (en) * 2002-12-11 2005-05-31 Texas Instruments Incorporated ESD protection with uniform substrate bias
JP3784382B2 (ja) * 2003-07-17 2006-06-07 株式会社半導体理工学研究センター 半導体集積回路
US7851860B2 (en) * 2004-03-26 2010-12-14 Honeywell International Inc. Techniques to reduce substrate cross talk on mixed signal and RF circuit design
US7541652B1 (en) * 2004-05-05 2009-06-02 Xilinx, Inc. Substrate coupled noise isolation for integrated circuits
US7492018B2 (en) * 2004-09-17 2009-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Isolating substrate noise by forming semi-insulating regions
US7071530B1 (en) * 2005-01-27 2006-07-04 International Business Machines Corporation Multiple layer structure for substrate noise isolation

Also Published As

Publication number Publication date
TW200802795A (en) 2008-01-01
EP1989738A2 (en) 2008-11-12
EP1989738A4 (en) 2012-07-25
EP1989738B1 (en) 2015-03-11
US20090302440A1 (en) 2009-12-10
US20070194394A1 (en) 2007-08-23
KR20080109731A (ko) 2008-12-17
US20130207229A1 (en) 2013-08-15
WO2007098303A2 (en) 2007-08-30
CN101432881A (zh) 2009-05-13
JP2009527927A (ja) 2009-07-30
US7608913B2 (en) 2009-10-27
JP5301290B2 (ja) 2013-09-25
TWI427762B (zh) 2014-02-21
CN101432881B (zh) 2010-12-08
US9048110B2 (en) 2015-06-02
WO2007098303A3 (en) 2009-01-29

Similar Documents

Publication Publication Date Title
KR101342877B1 (ko) 집적 회로 칩에서 회로 블록들간의 노이즈 고립
KR100579780B1 (ko) 반도제장치 및 그 제조방법
CN101847663B (zh) 一种瞬间电压抑制器及形成瞬间电压抑制器的方法
US6268639B1 (en) Electrostatic-discharge protection circuit
KR100909346B1 (ko) 반도체 장치에서의 고주파 신호 절연
US6459134B2 (en) Semiconductor devices which have analog and digital circuits integrated on a common substrate
US20020028522A1 (en) Electrostatic discharge protection device having a graded junction and method for forming the same
US7511346B2 (en) Design of high-frequency substrate noise isolation in BiCMOS technology
CN100492676C (zh) 制造集成pin型二极管的方法及其电路装置
US10269898B2 (en) Surrounded emitter bipolar device
CN110581126B (zh) 含静电放电保护电路的半导体集成电路器件及其制造方法
US9343555B2 (en) Methods and apparatus for ESD structures
US9431356B2 (en) Semiconductor device and method of forming the same
US7598575B1 (en) Semiconductor die with reduced RF attenuation
US7525172B2 (en) Semiconductor device
US8049282B2 (en) Bipolar device having buried contacts
KR100707594B1 (ko) 반도체 소자의 싸이리스터형 격리 구조
JP2004235475A (ja) 半導体装置
JP2006313861A (ja) 半導体装置
JP2005079557A (ja) 半導体装置及びその製造方法
KR100249180B1 (ko) 정전기 보호 회로의 구조
KR20010091035A (ko) 반도체 장치와 그의 제조 방법

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20080822

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20120118

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20130425

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20131007

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20131212

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20131213

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
FPAY Annual fee payment

Payment date: 20171211

Year of fee payment: 5

PR1001 Payment of annual fee

Payment date: 20171211

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20201201

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20211122

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20221123

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20231128

Start annual number: 11

End annual number: 11