Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes
  • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
  • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0175—Coupling arrangements; Interface arrangements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0404—Matrix technologies
  • G09G2300/0408—Integration of the drivers onto the display substrate
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0404—Matrix technologies
  • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

• the present invention relates to an active matrix display device such as a liquid crystal display device and an electronic apparatus using the same.
• liquid crystal display device installed as the output display unit. This is because the liquid crystal display device has a characteristic that does not require power for driving in principle and is a display device with low power consumption.
• the display area unit in which pixels are arranged in a matrix is digitally mounted on the same substrate.
• the interface drive circuit tends to be integrated.
• a horizontal drive system and a vertical drive system are arranged in the peripheral part (frame) of the effective display part, and these drive systems are formed on the same substrate together with the pixel area part using a low-temperature polysilicon TFT. It is integrally formed on the top.
• FIG. 1 is a diagram showing a schematic configuration of a general drive circuit integrated display device (see, for example, Patent Document 1).
• this liquid crystal display device has an effective display section 2 in which a plurality of pixels including liquid crystal cells are arranged in a matrix on a transparent insulating substrate, for example, a glass substrate 1 in FIG.
• a reference voltage generation circuit (RERDRV) 5 and a data processing circuit (DATAPRC) 6 etc. for generating the reference voltage are integrated.
• the drive circuit integrated display device of FIG. 1 has two horizontal drive circuits 3U and 3D.
• the force placed on both sides of the effective pixel unit 2 is to drive the data lines by dividing them into odd lines and even lines.
• FIG. 2 is a block diagram showing a configuration example of the horizontal drive circuits 3U and 3D in FIG. 1 that drive odd lines and even lines separately.
• the horizontal drive circuit 3U for driving odd lines and the horizontal drive circuit 3D for driving even lines have the same configuration.
• the shift register (HSR) group 3HSRU, 3HSR D which sequentially outputs shift pulses (sampling pulses) in synchronization with the horizontal transfer clock HCK (not shown), and the shift registers 31U, 31D Sampling latch circuit group 3SMPLU, 3SM PLD that sequentially samples and latches digital image data by given sampling pulse, and line sequential latch circuit group 3LTCU, 3LTCD, which serializes each latch data of sampling latch circuits 32U, 32D And digital Z analog conversion circuit (DAC) groups 3DACU and 3DACD for converting the digital image data line-sequentialed by the line-sequential latch circuits 33U and 33D into analog image signals.
• HCK horizontal transfer clock
• DAC digital Z analog conversion circuit
• a level shift circuit is arranged at the input stage of DACs 34U and 34D, and the level-up data is input to DAC 34.
• Patent Document 1 JP 2002-175033 A
• the liquid crystal display device shown in FIG. 1 or the like for example, externally transfers a master clock MCK or a horizontal synchronization signal Hsync at a predetermined level to the RGB interface circuit!
• a master clock MCK or a horizontal synchronization signal Hsync at a predetermined level
• the RGB interface circuit externally transfers a master clock MCK or a horizontal synchronization signal Hsync at a predetermined level to the RGB interface circuit!
• it is configured to supply a desired circuit formed on the insulating substrate.
• CMOS inverter to which a low power supply voltage (panel input voltage, set output voltage) is supplied to the input stage is arranged, and a high power supply voltage in the subsequent stage (in-panel logic drive) Force that is configured to shift the level at the level shift stage to which the voltage is supplied.
• the gate voltage drops to near the value voltage Vth at the threshold of the transistor Tr constituting the inverter. It becomes difficult to operate the circuit for signals.
• the present invention provides a display device capable of amplifying the same input voltage as the power supply voltage of an IC using low-temperature polysilicon having a high threshold voltage and large variation, and an electronic device using the same There is to do.
• a first aspect of the present invention is a display device integrated with a drive circuit to which at least a master clock is supplied, wherein the first level when the master clock is input is converted to a second level of an internal drive voltage level.
• Level conversion circuit that outputs to a predetermined circuit, and the level conversion circuit is based on L level shifters of a form that needs to be reset periodically and a level-shifted horizontal synchronization signal Hsync.
• a reset pulse for the above MCK level shifter with a horizontal period cycle is output to each level shifter for M horizontal periods (where M ⁇ N), and a logic circuit that outputs a signal to be input, and the final output signal is M And a function of selecting a circuit that is not performing a reset operation from the outputs of L level shifters every horizontal period and outputting a level-shifted master clock.
• the level shifter includes an inverter connected between the internal drive voltage level potential and a reference potential, a first node, and a second node connected to an input of the inverter, A third node connected to the output of the inverter, a capacitor connected between the first node and the second node, and the input of the master clock only during the reset period to prevent the first level potential from being input. And a circuit for supplying a reference voltage, which is an intermediate potential between the first node and the reference potential, to the first node and bringing the second node and the third node into a conductive state.
• the second node and the third node are connected by a switching transistor.
• the gate potential is held at a negative potential.
• the inverter is connected to a negative potential instead of a reference potential.
• a second aspect of the present invention is an electronic apparatus including a display device integrated with a drive circuit to which at least a master clock is supplied, wherein the display device has a first level when the master clock is input. It has a level conversion circuit that converts it to the second level of the internal drive voltage level and outputs it to a predetermined circuit.
• the level conversion circuit includes L level shifters of a type that requires periodic reset operation, and a level shifter. Based on the horizontal sync signal Hsync, the reset pulse for the above MCK level shifter having a period of N horizontal periods is output to each level shifter with an M horizontal period (M ⁇ N) phase shifted input signal.
• the module can be made thinner.
• FIG. 1 is a diagram showing a schematic configuration of a general drive circuit integrated display device.
• FIG. 2 is a block diagram showing a configuration example of the horizontal drive circuit of FIG. 1 that drives odd lines and even lines separately.
• FIG. 3 is a diagram showing an arrangement configuration of a drive circuit integrated display device according to an embodiment of the present invention.
• FIG. 4 is a system block diagram showing a circuit function of the drive circuit integrated display device according to the embodiment of the present invention.
• FIG. 5 is a circuit diagram showing a configuration example of an effective display unit of a liquid crystal display device.
• FIG. 6 shows a basic configuration example of the first and second horizontal drive circuits of the present embodiment.
• FIG. 7 is a diagram showing a configuration example of a master clock level conversion circuit in the interface circuit according to the present embodiment.
• FIG. 8 is a circuit diagram showing a specific configuration example of the level shifter of FIG.
• FIG. 9 is a circuit diagram showing a specific configuration example of the logic circuit of FIG.
• FIG. 10 is a circuit diagram showing a configuration example of the reference voltage generation circuit of FIG.
• FIG. 11 is a circuit diagram showing another configuration example of the reference voltage generation circuit of FIG.
• FIG. 12 is a diagram showing an overall timing chart of the level conversion circuit of FIG.
• FIG. 13 is a timing chart of the level shifter of FIG.
• FIG. 14A to FIG. 14C are diagrams for explaining the features of the interface circuit according to the present embodiment.
• FIG. 15 is a circuit diagram showing another configuration example of the MCK level shifter according to the present embodiment.
• FIG. 16 is a circuit diagram showing still another configuration example of the MCK level shifter according to the present embodiment.
• FIG. 17 is an external view schematically showing the configuration of a mobile phone that is a mobile terminal according to an embodiment of the present invention.
• FIG. 3 and 4 are schematic configuration diagrams showing a configuration example of the drive circuit integrated display device according to the embodiment of the present invention.
• FIG. 3 shows the drive circuit integrated display device according to the present embodiment.
• FIG. 4 is a system block diagram showing a circuit function of the drive circuit integrated display device according to the present embodiment.
• the liquid crystal display device 10 includes an effective display unit (ACDSP) 12 in which a plurality of pixels including liquid crystal cells are arranged in a matrix on a transparent insulating substrate, for example, a glass substrate 11,
• ACDSP effective display unit
• a pair of first and second horizontal drive circuits (H-Drino, HDRV) 13U and 13D arranged above and below the effective display unit 12 and in FIG.
• V-Dryno ⁇ VDRV Drive circuit
• DATAPRC Data processing circuit
• DC-DC Power supply circuit
• IGF Interface circuit
• TG Timing generator
• REFDRV reference voltage drive circuit
• an input pad 20 such as data is formed on the edge of the glass substrate 11 in the vicinity of the arrangement position of the second horizontal drive circuit 13D.
• the glass substrate 11 is disposed so as to face a first substrate on which a plurality of pixel circuits including active elements (for example, transistors) are arranged and formed in a matrix, and to face the first substrate with a predetermined gap. And a second substrate. A liquid crystal is sealed between the first and second substrates.
• active elements for example, transistors
• the circuit group formed on the insulating substrate is formed by a low-temperature polysilicon TFT process.
• a horizontal drive system and a vertical drive system are arranged around the effective display section 12 (frame), and these drive systems use polysilicon TFTs. It is integrally formed on the same substrate together with the pixel area portion.
• the driving circuit integrated liquid crystal display device 10 of the present embodiment has the force that two horizontal driving circuits 13U and 13 3D are arranged on both sides (up and down in FIG. 3) of the effective pixel unit 12. This is because the drive is divided into odd lines and even lines.
• each of the three digital data is stored in the sampling latch circuit, and during one horizontal period (H), conversion processing to analog data is performed three times by the shared digital-analog conversion circuit.
• the RGB selector method is adopted by selecting three analog data in a time division manner in the horizontal period and outputting them to the data line (signal line).
• the digital R data is described as the first digital data
• the digital B data is described as the second digital data
• the digital G data as the third digital data.
• a plurality of pixels including liquid crystal cells are arranged in a matrix.
• data lines and vertical scanning lines driven by the horizontal drive circuits 13U and 13D and the vertical drive circuit 14 are wired in a matrix.
• FIG. 5 is a diagram showing an example of a specific configuration of the effective display unit 12.
• a pixel arrangement of 3 rows (n ⁇ l rows to n + 1 rows) and 4 columns (m ⁇ 2 columns to m + 1 columns) is shown as an example.
• the unit pixel 123 has a configuration including a thin film transistor TFT which is a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs.
• the liquid crystal cell LC means a capacitance generated between a pixel electrode (one electrode) formed by a thin film transistor TFT and a counter electrode (the other electrode) formed facing the pixel electrode.
• the gate electrode has a vertical scanning line ..., 121 ⁇ -1, 121 ⁇ , 121 n + 1, connected to source electrode force S data line ..., 122m-2, 122m-1, 122m, 122m + 1, ...
• the pixel electrode is connected to the drain electrode of the thin film transistor TFT, and the counter electrode is connected to the common line 124.
• the storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 124.
• a predetermined AC voltage is applied to the common line 124 as a common voltage Vcom by the VCOM circuit 21 formed integrally with the drive circuit and the like on the glass substrate 11.
• One end of each of the vertical scanning lines ..., 121 ⁇ -1, 121 ⁇ , 121 ⁇ + 1, ... is connected to each output end of a corresponding row of the vertical drive circuit 14 shown in FIG.
• the vertical drive circuit 14 includes, for example, a shift register, and sequentially generates vertical selection pulses in synchronization with a vertical transfer clock V CK (not shown) to generate vertical scanning lines ..., 121 ⁇ -1, 121 ⁇ , 121 ⁇ + Perform vertical scanning by giving to 1,.
• V CK vertical transfer clock
• each of the data lines..., 122m-1, 122m + 1,... is connected to each output end of the corresponding column of the first horizontal drive circuit 13U shown in FIG.
• the other end is connected to each output end of the corresponding column of the second horizontal drive circuit 13D shown in FIG.
• the first horizontal drive circuit 13U stores three digital data of R data, B data, and G data in the sampling latch circuit, respectively, and converts it to analog data three times during one horizontal period (H). In this way, the three data are selected in a time-sharing manner within the horizontal period and output to the corresponding data line.
• the first horizontal drive circuit 13U uses the first latch circuit in the time division manner and the second data latched by the first and second sampling latch circuits in time division.
• the G data latched in the third sampling latch circuit during the time-sequential transfer processing of the R data and B data to the latch circuit is transferred to the third latch circuit, and then transferred to the second latch circuit.
• R, B, and G data latched by the latch circuit and the third latch circuit are selectively output within one horizontal period and converted to analog data, and three analog data are selected in a time-division manner within the horizontal period. To the corresponding data line.
• the RGB selector system is To achieve this, a first latch series for two digital R and B data and a second latch series for one digital G data are arranged in parallel, and a digital analog conversion circuit (DAC) after the selector By using an analog buffer and a line selector in common, the frame size and power consumption are reduced.
• DAC digital analog conversion circuit
• the second horizontal drive circuit 13D basically has the same configuration as the first horizontal drive circuit 13U.
• FIG. 6 is a block diagram showing a basic configuration example of the first horizontal drive circuit 13U and the second horizontal drive circuit 13D of the present embodiment.
• the horizontal drive circuit 13 will be described.
• This horizontal drive circuit shows a basic configuration corresponding to three digital data, and actually, a plurality of similar configurations are arranged in parallel.
• the horizontal drive circuit 13 includes a shift register (HSR) group 13HSR, a sampling latch circuit group 13SMPL, a latch output selection switch 130SEL, a digital-analog conversion circuit 13DAC, an analog buffer 13ABUF, and a line selector.
• HSR shift register
• SPL sampling latch circuit group
• SEL latch output selection switch
• DAC digital-analog conversion circuit
• AUF analog buffer
• LSEL line selector
• the shift register group 13HSR sequentially outputs shift pulses (sampling pulses) from each transfer stage corresponding to each column to the sampling latch circuit group 13 SMPL in synchronization with a horizontal transfer clock HCK (not shown). Shift register (HSR).
• the sampling latch circuit group 13SMPL sequentially samples and latches the first sampling latch circuit 131 that sequentially samples and latches the R data that is the first digital data, and the B data that is the second digital data.
• the second sampling latch circuit 132 that latches the R data latched in the first sampling latch circuit 131 at a predetermined timing
• the third sampling latch circuit that sequentially samples and latches the G data that is the third digital data 133
• the first latch circuit 134 for serially transferring the digital data R or B data latched in the second sampling latch circuit 132, and the higher digital R or B data latched in the first latch circuit 134
• a second latch circuit 135 having a level shift function for converting and latching into voltage amplitude
• a third sub And a third latch circuit 136 having a level shift function for latching the converted digital G data la Tutsi to pulling the latch circuit 133 to a higher voltage amplitude.
• a first latch series 137 is formed by the first sampling latch circuit 131, the second sampling latch circuit 132, the first latch circuit 134, and the second latch circuit 135.
• the third ramp ring latch circuit 133 and the third latch circuit 136 form a second latch series 138.
• data input from the data processing circuit 15 to the horizontal drive circuits 13U and 13D is supplied at a level of 0-3V (2.9V) system.
• the level is raised to, for example, ⁇ 2.3 V to 4.8 V system by the level shift function of the second and third latch circuits 135 and 136 which are output stages of the sampling latch circuit group 13SMPL.
• the latch output selection switch 130SEL selectively switches the output of the sampling latch circuit group 13SMPL and outputs it to the digital analog circuit 13DAC.
• Digital-to-analog converter circuit 13DAC performs digital-to-analog conversion three times during one horizontal period. That is, the digital-analog conversion circuit 13DAC converts three digital R, B, and G data into analog data during one horizontal period.
• the analog buffer 13ABUF buffers R, B, G data converted into analog signals by the digital-analog converter circuit 13DAC and outputs the data to the line selector 13LSEL.
• the line selector 13LSEL has three analog R, B, Select G data and output to corresponding data line DTL—R, DTL—B, DTL—G.
• the data in the second sampling latch circuit 132 is transferred during the horizontal blanking period.
• the data is transferred to the first latch circuit 134 and immediately transferred to the second latch circuit 135 for storage.
• the data in the first sampling latch circuit 131 is transferred to the second sampling latch 132, and immediately transferred to the first latch circuit 134 for storage.
• the third sampling Data in the latch circuit 133 is transferred to the third latch circuit 136.
• the data for the next horizontal line is sent to the first, second, and third sampling latch circuits 131, 132, 133.
• the latch output selection switch 130SEL switches the data stored in the second latch circuit 135 and the third latch circuit 136 to the digital-analog conversion circuit 13DAC Output to.
• the data stored in the first latch circuit 134 is transferred to and stored in the second latch circuit 135.
• the data is output to the digital analog conversion circuit 13DAC when the latch output selection switch 130SEL is switched.
• This sampling latch method outputs three pieces of digital data to the digital-to-analog converter circuit 13DAC, which makes it possible to achieve high definition and a narrow frame.
• the 3rd digital data is not accompanied by transfer work while storing data for one horizontal line.
• B (Blue) ⁇ G (Green) ⁇ R (Red) Because writing with a good power, such as the VT characteristics of the liquid crystal, color data that has the most influence on the human eye, that is, G data, makes it more resistant to variations in image quality.
• the data processing circuit 15 includes a level shifter 151 that shifts the level of parallel digital R, G, B data input from the outside from 0—3V (2.9V) system to 6V system, and level-shifted R , G, B data serial-parallel conversion circuit 152 that converts serial data to parallel data in order to adjust phase and reduce frequency, downshift parallel data from 6V system to 0—3 V (2.9 V) system And down-converter 153 that outputs odd data (odd-data) to horizontal drive circuit 13U and outputs even-data (even-data) to horizontal drive circuit 13D.
• a level shifter 151 that shifts the level of parallel digital R, G, B data input from the outside from 0—3V (2.9V) system to 6V system
• level-shifted R , G, B data serial-parallel conversion circuit 152 that converts serial data to parallel data in order to adjust phase and reduce frequency
• downshift parallel data from 6V system to 0—3 V (2.9 V) system
• the power supply circuit 16 includes a DC-DC converter.
• an external force liquid crystal voltage VDD1 eg, 2.9V
• VDD1 an external force liquid crystal voltage
• Hsync the horizontal synchronization signal supplied from the interface circuit 17.
• Synchronous or built-in oscillation circuit the frequency is low (slow), and the clock with a variation in the oscillation frequency is corrected by a predetermined correction system and the horizontal synchronization Hsync is doubled 6V system
• the internal panel voltage is boosted to VDD2 (for example, 5.8V) and supplied to each circuit inside the panel.
• the power supply circuit 16 generates negative voltages VSS2 (for example, 1.1.9 V) and VSS3 (for example, 1.3.8 V) as internal panel voltages and supplies them to predetermined circuits (interface circuit, etc.) inside the panel. To do.
• VSS2 for example, 1.1.9 V
• VSS3 for example, 1.3.8 V
• the interface circuit 17 shifts the level of the master clock MCK to which an external force is supplied, the horizontal synchronization signal H sync, and the vertical synchronization signal Vsync to the panel internal logic level (for example, VDD2 level).
• the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync are supplied to the timing generator 18, and the horizontal synchronization signal Hsync is supplied to the power supply circuit 16.
• the interface circuit 17 does not supply the master clock MCK to the power supply circuit 16. Don't do that!
• the master clock MCK supply line from the interface circuit 17 to the power supply circuit 16 may be left as it is, and the master clock MCK may not be used for boosting on the power supply circuit 16 side.
• the same input as the power supply voltage of the IC is used by using low-temperature polysilicon having a high threshold Vth and large variations.
• a level conversion circuit that can amplify the voltage is used.
• FIG. 7 is a diagram showing a configuration example of a master clock level conversion circuit in the interface circuit according to the present embodiment.
• the master clock level conversion circuit 17LSMCK of the interface circuit 17 is connected in parallel to the input line of the master clock MCK of the RGB parallel interface and requires a reset operation periodically.
• Level shifters (LSMCK1, LSMCK2) of type S (L 2 in this embodiment) 171—1, 171—2, and an asynchronous level shift circuit (LZS) connected to the input line of the horizontal sync signal Hsync 172 and the level-shifted horizontal sync signal Hsync, the MCK level with a period of N horizontal periods Outputs the input signal for the shifter 171—1, 171—2 with an M horizontal period (M ⁇ N) out of phase with respect to each leveler shifter 171—1, 171—2.
• a reference voltage generation circuit 174 that supplies a reference voltage VREF to the logic circuit 173 and level shifters 171—1, 171—2, and L MCK level shifters 171—1, 171 as the final output signal every M horizontal periods — It has switch circuits 175 and 176 and an inverter 177 for realizing the function of selecting a circuit that does not perform the reset operation from the outputs of 2 and outputting the level-shifted master clock LSMCK.
• FIG. 8 is a circuit diagram showing a specific configuration example of the level shifter 171 (—1, 2) of FIG.
• the level shifter 171 in FIG. 8 is configured as a level shifter of a so-called chopper-type comparator type that level shifts the external input MCK to the logic voltage in the panel! Specifically, the level shifter 171 n-channel transistors NT1711 to NT1715, p-channel transistors PT1711, PT1712, an inverter INV1711, and a capacitor C171. Further, in FIG. 8, NDA indicates the first node, NAB indicates the second node, and NDC indicates the third node! /.
• the source and drain of the transistor NT1711 are connected to the input terminal in of the master clock MCK and the node NDA, respectively, and the gate is connected to the output terminal of the inverter INV1711.
• the input terminal of the inverter INV1711 is connected to the input line of the reset signal rst.
• the source and drain of the transistor NT1712 are connected to the input terminal Vref of the reference voltage VREF and the node NDA, and the gate is connected to the input line of the reset signal rst.
• the source of transistor PT1711 is connected to the supply line of the panel drive voltage (second power supply voltage) VDD2, the drain is connected to the drain of transistor NT1713, and the source of transistor NT1713 is connected to the reference potential VSS (GND). ing.
• the gate of the transistor PT1711 and the gate of the transistor NT1713 are connected to form a node NDB. This transistor PT1711 and NT1713 make inverter INV1712 Is formed.
• the source of the transistor PT1712 is connected to the supply voltage of the panel drive voltage (second power supply voltage) VDD2, the drain is connected to the drain of the transistor NT1714, and the source of the transistor NT1714 is connected to the reference potential VSS (GND). ing. The connection point between the drains of the transistors PT1 712 and NT1714 is connected to the output terminal out.
• the gate of the transistor PT1712 and the gate of the transistor NT1715 are connected to each other, and the connection point between the gates and the connection point between the drains of the transistor PT1711 and the transistor NT1713 are connected to form a node NDC.
• the B and node are connected to NDC, and the gate is connected to the input line of reset signal rst.
• the first electrode of the capacitor C171 is connected to the node NDA, and the second electrode is connected to the node NDB.
• the logic circuit 173 uses the horizontal synchronization signal Hsync level-shifted by the asynchronous level shifter circuit 172 that can asynchronously level shift the external input Hsync to the in-panel logic voltage (VDD2). It has a logic circuit that generates reset signals rst-1 and rst-2 for 171-1 and 171-2.
• FIG. 9 is a circuit diagram showing a specific configuration example of the logic circuit 173 in FIG.
• the logic circuit 173 includes an inverter INV1731, INV1732, a T-type flip-flop FF173, and 2-input AND gates AG1731 and AG1732.
• the input terminal of the inverter INV1731 is connected to the input terminal in of the level-shifted horizontal synchronization signal Hsync, the output terminal is the input terminal in of the T-type flip-flop FF173, AND one input terminal of the AND gate AG1731, and AND Connected to one input terminal of gate AG1732.
• the other input terminal of the AND gate AG1731 is connected to the output terminal of the inverter INV1732.
• the input terminal of the inverter INV1732 and the other input terminal of the AND gate AG1732 are connected to the output terminal out of the T-type flip-flop FF173.
• a selection pulse SEL MCK for switching the switches 175 and 176 is output from the output terminal out of the T-type flip-flop FF173.
• the reference voltage generation circuit 174 generates a reference voltage VREF of VDDO / 2 that is half of the voltage VDDO (for example, 1.8 V), and supplies it to the reference voltage input terminal Vref of the level shifters 171—1, 171—2. .
• FIGS. 10 and 11 are circuit diagrams showing configuration examples of the reference voltage generation circuit 174 of FIG.
• the reference voltage generation circuit 174A in FIG. 10 includes resistance elements R1741 and R1742 connected in series between the supply line of the voltage VDDO and the reference potential V SS (GND), and from the connection midpoint of both resistance elements. It is configured to output the reference voltage VREF of VDD0Z2.
• the gate is connected to the supply line of the reset signal rst between one end of the ground side resistance element T1741 and the reference potential VSS in addition to the configuration in FIG.
• the n-channel transistor NT1741 has a configuration in which the drain and source are connected.
• the reference voltage generation circuit 174B in FIG. 11 is provided with a transistor NT1741 as a switch for allowing current to flow through the resistance element only during reset operation, realizing constant current and reducing current consumption in the panel.
• FIG. 12 shows an overall timing chart of the level conversion circuit of FIG. 7, and FIG. 13 shows a timing chart of the level shifter of FIG.
• a master clock MCK and a horizontal synchronization signal Hsync are input as RGB parallel interface signals.
• the horizontal sync signal Hsync is level-shifted by the level shifter 172 and converted from the input voltage level (VDDO amplitude) to the panel logic voltage (VDD2 amplitude).
• the level-converted horizontal synchronization signal Hsync is input to the logic circuit 173.
• reset pulses rst-l and rst-2 having a period of two horizontal periods and a selection pulse SEL-MCK for SW for final output switching are generated.
• the phases of the reset pulses rst-1 and rst-2 are output at a timing shifted by one horizontal period.
• Reset pulse signals rst-1 and rst-2 are sent to level shifters 171—1 and 171—2, respectively. Entered.
• the level shifters 171-1 and 171-2 are reset in a cycle of two horizontal periods.
• the final output signal LSMCK is output as one signal with the output signal power of the level shifters 171-1 and 171-2 selected.
• a reset operation is performed, and the phase of the selection pulse SEL-MCK is determined so that the other circuit is selected.
• the transistor NT1711 is turned off, the transistors NT1712 and NT 1715 are turned on, and the CMOS inverter INV1712 in FIG. 8 is bypassed (node NDB and NDC are short-circuited). This is the operating point voltage of INV1712.
• the transistor NT1711 is turned on, the transistors NT1712 and NT1 715 are turned off, and the node NDA becomes the potential of the external input pulse MCK.
• the node NDB is C-coupled by the capacitor C171, and swings with a voltage of VDD0 around the operating point of the inverter INV1712.
• the out output is a signal obtained by amplifying MCK from VDD0 to VDD2.
• the interface circuit 17 having such a configuration has the following characteristics.
• the asynchronous level shifter LZS is connected to the input pulse of the master clock MCK and horizontal sync signal H sync, and after boosting to the logic voltage in the panel, It is output to the timing generator 18.
• the level shifter 171 that needs to be reset is connected to the master clock MCK, and the reset signal is It is generated using the horizontal sync signal Hsync level-converted by the asynchronous level shifter 172.
• Horizontal sync signal Hsync is normal RGB Since it is an essential pulse for the interface, it is possible to obtain an output waveform with the same timing using any system. Even if the horizontal sync signal Hsync is used to reset the master clock MCK, it does not limit the system functions.
• MCK level shifter 171 is not limited to the configuration shown in FIG. 8, and may employ the circuit configurations shown in FIGS. 15 and 16, for example.
• the level shifter 171A in FIG. 15 includes a conversion unit 1711 that performs level conversion on the negative side of the voltage applied to the gate of the transistor NT1715 as a switch for selectively connecting the node NDB and the node NDC.
• a conversion unit 1711 that performs level conversion on the negative side of the voltage applied to the gate of the transistor NT1715 as a switch for selectively connecting the node NDB and the node NDC.
• the difference between the level shifter 171B of FIG. 16 and the circuit configuration of FIG. 15 is that the negative potential level VSS2 of the inverter INV1712 is lowered.
• This change improves the characteristics of the inverter INV1712 and increases the dynamic range of the level shifter.
• the timing generator 18 is synchronized with the master clock MCK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync supplied by the interface circuit 17, and the horizontal start pulse HST used as a clock for the horizontal drive circuits 13U and 13D.
• a master clock MCK and a horizontal synchronization signal Hsync are input to the interface circuit 17 as RGB parallel interface signals.
• the horizontal synchronization signal Hsync is level-converted by the level shifter 172 to the input voltage level (VDDO amplitude) force panel logic voltage (VDD2 amplitude).
• the level-converted horizontal synchronizing signal Hsync is input to the logic circuit 173.
• reset pulses rst-l and rst-2 having a period of two horizontal periods and a selection pulse SEL-MCK for SW for final output switching are generated.
• the phases of the reset pulses rst-1 and rst-2 are output at a timing shifted by one horizontal period.
• the signals of reset pulses rst-1 and rst-2 are input to level shifters 171-1 and 171-1, respectively.
• the level shifters 171-1 and 171-2 are reset in a cycle of two horizontal periods.
• the final output signal LSMCK is output as one signal selected from the output signals of the level shifters 171-1 and 171-2.
• Parallel digital data input from the outside is subjected to phase conversion and parallel conversion to lower the frequency in the data processing circuit 15 on the glass substrate 11, and the R data, B data, and G data are the first and It is output to the second horizontal drive circuits 13U and 13D.
• the digital G data input from the data processing circuit 15 is sequentially sampled and held by the third sampling latch circuit 133 over 1H. Thereafter, the data is transferred to the third latch circuit 136 in the horizontal blanking period.
• R data and B data are sampled separately over 1H and held in the first and second sampling latch circuits 131 and 132, and in the next horizontal blanking period, each first latch circuit is sampled. Forwarded to 134.
• the data in the second sampling latch circuit 132 is transferred during the horizontal blanking period.
• the data is transferred to the first latch circuit 134 and immediately transferred to the second latch circuit 135 and stored.
• the data in the first sampling latch circuit 131 is transferred to the second sampling latch 132 and immediately transferred to the first latch circuit 134 for storage.
• the data in the third sampling latch circuit 133 is transferred to the third latch circuit 136.
• the data force latch output selection switch 130SEL stored in the second latch circuit 135 and the third latch circuit 136 is switched. In this case, it is output to the digital-to-analog converter circuit 13DAC.
• the data stored in the first latch circuit 134 is transferred to the second latch circuit 135 and stored.
• the data is output to the digital-analog converter circuit 13DAC when the latch output selection switch 130SEL is switched.
• R, B, G data converted into analog data by the digital-analog converter circuit 13DAC is held in the analog buffer 13ABUF, and each analog R, B, G data is divided into 3 parts in the 1H period. It is selectively output to the corresponding data line. Note that the processing order of G, R, and B can be changed.
• the master clock level conversion circuit 17LSMCK of the interface circuit 17 is connected in parallel to the input line of the master clock MCK of the RGB parallel interface, and is periodically reset.
• a logic circuit 173 that outputs a signal that is input with a phase shift of M horizontal periods (where M is N), and a reference voltage generation circuit that supplies the reference voltage VREF to the level shifters 171-1 and 171-2 174 and L MCK level shifters for each M horizontal period as the final output signal
• the sampling latch circuits 131 and 132, the first latch circuit 134, and the second latch circuit 135 for the first digital data (R) and the second digital data (B) are provided. It has a first latch series 137 that is cascade-connected for serial transfer and a second latch series 138 that is a cascade connection of a sampling latch circuit 133 and a third latch circuit 136 for the third digital data.
• Conversion circuit 13DAC, analog buffer circuit 13ABUF, and line selector 13LSEL that outputs three analog data (R, B, G) selectively to the corresponding data line during one horizontal period (H) The following effects can be obtained.
• this system can realize a three-line selector system with high definition and a narrow frame on an insulating substrate, and a drive circuit integrated display device using the three-line selector system.
• an active matrix liquid crystal display device has been described as an example.
• the present invention is not limited to this, and an electro-luminescence (EL) element is not limited to the electro-optic of each pixel.
• EL electro-luminescence
• the active matrix display device represented by the active matrix liquid crystal display device according to the above embodiment is used as a display for OA equipment such as a personal computer and a word processor, and a television receiver, in particular.
• Display units of portable terminals such as mobile phones and PDAs that are becoming smaller and more compact It is suitable for use as.
• FIG. 17 is an external view schematically showing the configuration of a mobile terminal to which the present invention is applied, for example, a mobile phone.
• the mobile phone 200 has a configuration in which a speaker unit 220, a display unit 230, an operation unit 240, and a microphone unit 250 are arranged in the order of the upper side force on the front side of the device casing 210. .
• a liquid crystal display device is used as the display unit 230, and the active matrix liquid crystal display device according to the above-described embodiment is used as the liquid crystal display device.
• the pitch can be narrowed, the frame can be narrowed, and the power consumption of the display device can be reduced. Therefore, the power consumption of the terminal body can be reduced.
• the display device and the electronic device of the present invention can amplify the same input voltage as the power supply voltage of the IC by using low-temperature polysilicon having a high threshold voltage and large variations.
• a display for OA equipment such as personal computers and word processors and television receivers
• it is especially used as a display unit for portable terminals such as mobile phones and PDAs, which are becoming increasingly compact and compact. Applicable.

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