Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
  • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
  • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage

Definitions

• the output circuit of open-in type transistor is simple in its circuit configuration, but it has a point of resistance to electrostatic discharge. Therefore, in the conventional conductor product circuit arrangement, as a means to protect the transistor from damage, a current resistance is provided between the transistor and the drain output element of the transistor, or between the transistor and the gate terminal of the transistor.
• the configuration that suppresses the above large current was used by providing a clamp path such as a diode.
• a channel that operates when the output terminal and the power supply line exceed a predetermined value is provided, and the transistor operates when the channel operates.
• the applicant of the present application has disclosed and proposed a force circuit having a configuration in which a voltage is applied between the child and the output element (see).
• An anode is connected to the end of the transistor described above, and The diode end connected to the gate of the transistor is connected to the end, and is connected to ground, the source is connected to the gate of the transistor, and the gate is connected to the end of The bipolar transistor with the drain connected to the ground has a P-type transistor.
• the type bipolar transistor is connected between the two-transistor gate and the ground connected to the P-type transistor, and is connected to the two ends of the first stage. It is preferable that the configuration (3) includes a transistor.
• a semiconductor product circuit including a semiconductor product circuit according to the present invention, an open-in type transistor, and an electrostatic path that inputs a signal to the gate of the transistor and protects the interface transistor from damage.
• the above-mentioned path is provided with an electrostatic path consisting of the above-mentioned deviations of 2 (4).
• FIG. 10 is an outline diagram showing the formation of Tadley c according to Ming.
• 3 is a circuit diagram showing the two states of static electricity 4.
• 4 is a road map showing static electricity 4.
• 5A is a circuit diagram showing another variation of static electricity 4.
• 5B is a circuit diagram showing another variation of electrostatic 4.
• 018 is an outline diagram showing the formation of Tadrai C according to Ming.
• the TD drive C of this embodiment has the terminals (,, W, CC G G
• the Tadrai C of the present embodiment has, as its elements, a gadget, a driver 2, a driver 3, a Gf force circuit 4, a guitar 5, and a heater 6.
• W, and W are the partial terminals for supplying the drive signals to the three (3, Note that these terminals are designed with high pressure because they are marked with pressure.
• Control terminal (G) is a terminal for outputting to C section.
• the pressure generated by the guitar 5 is connected to the power supply line.
• 002 is a means for controlling the body operation of the device (G using the Gf force circuit 4, movement control and control of the motor based on the number of the heater 6, and various road protection). . More specifically, regarding the dynamic control and control of the data, is the control of the rotational speed and the phase of the data based on the number of the motor 6 and the taps are generated. Send the issue to Dry 2.
• the driver 2 is input from ,,,,
• 003 Drive 3 is a means to drive a data transistor () connected to it.
• the transistor is input to the gate of
• the 002 Gf force circuit 4 is provided with an open-in type net transistor as a power transistor, and by controlling the transistor according to these signals, it generates a Gf signal with a wave number proportional to Then, it is a means to send this from G child to C section.
• the G-force circuit 4 of this embodiment has the electrostatic 4 according to the present invention as a step for protecting the transistor from damage. 4 of A detailed explanation will be given later on the work.
• the 002 guitar is a voltage conversion means for generating a desired pressure from the input pressure printed on the CC element and sending it from the G element as a horn.
• 00322 is a circuit diagram showing the state of static electricity 4.
• FIG. 003, 4 in this embodiment has a diode, a resistor, a bipolar transistor QP, and a clamp C.
• the anode of the 003 diode is connected to the () of the transistor that constitutes the stage of the transistor.
• the diode socket is connected to the gate of the transistor.
• the transistor QP is connected to the gate of the transistor QP. It is connected to the end of the resistor of the transistor QP. The transistor of transistor QP is connected to ground.
• Clamp C is connected in parallel with G-transistor between G-element and ground, and when the over-voltage exceeding the pressure is applied to G-element, G-element and ground are short-circuited.
• the pressure is the clamp element.
• the clamp C is set lower than the transistor. For example, in the case of 4 in this embodiment, the pressure of the transistor is 5 while that of the clamp C is set to 42.
• the transistor QP when the G-element is marked with a stripe or the like, its position is lifted through the raw capacitance C d associated with the gate-in of the transistor. Becomes At this time, when the transistor pressure exceeds a predetermined on-state (.7), the transistor QP is turned on until then. In other words, the transistor QP comes before the transistor and leads the transistor to ground. As a result, the gate pressure of the transistor cannot exceed its on-pressure, and the transistor can be prevented from accidental accident.
• the Gf force circuit 4 including the static capacitor 4 can prevent the rise of the gate position via the parasitic capacitance C d without requiring the power supply. It is possible to protect the open-in type transistor from accidental use and to protect it from damage by the markings such as the power supply. That is, if the Tadrai C of this embodiment is
• the clamp C If an overvoltage exceeding ⁇ is applied, the clamp C will be released, and the pressure of the G pin can be released to the ground. As a result, it is possible to effectively prevent the breakdown of the transistor, as compared with the configuration that depends only on the pressure of the transistor.
• static electricity 4 does not interfere with the control of the transistor in the normal operation state of Tadrai C.
• 00493 is a circuit diagram showing two states of electrostatic charge 4.
• the resistor 2 to 3 and the type bipolar transistor Q to Q 2 are added. It will be done.
• the transistor Q transistor is connected to the gate of the transistor Q.
• the transistor Q transistor is connected to ground via resistor 3. It is connected to the end of resistor 2 of transistor Q.
• the transistor Q2 transistor is connected to the gate of the transistor Q2.
• the transistor Q2 transistor is connected to ground. It is connected to the end of resistor 3 of transistor Q 2.
• 4 is connected between the transistor 2 of the bipolar transistor QP and the ground of the transistor and the gate ground of the transistor Q.
• type bipolar transistors Q 1 to Q 2 connected to the two ends of the first stage.
• the transistors Q to Q 2 are also turned on in succession with the transistor QP. It is possible to quickly draw the current from the gate of the transistor. Therefore, even if a steep line or the like is printed, it is possible to prevent the gate level from rising via the parasitic capacitance C without delaying, so that it is possible to prevent the transistor from unintentionally. It is possible to protect it from damage.
• the Ming is applied to the Tadrai C as an example, but the Ming is not limited to this, and an open-in type transistor is provided. It can be widely used in semiconductor product circuits.
• the rise of the gate position of the transistor is As a means of doing so, the explanation has been given by taking the configuration using the type bipolar transistor QP as an example, but the present invention is not limited to this, and as shown in 4, instead of the transistor QP, Do not use the P-type transistor P, which has better pressure.
• the configuration connect the source of the transistor P to the gate of the MOS transistor, connect the drain to ground, and connect the gate to the end of.
• the transistor P comes earlier than the transistor P, and the on-state pressure of the transistor P becomes higher. Measure the device so that it is lower than that of the output transistor. For example, if the ounce of the transistor is -8 and the pressure of the transistor is -8, then the ounce of the transistor P should be set to O and lower than that.
• the explanation is given by exemplifying the configuration using the polar-connected transistors Q 1 to Q 2 as a means for quickly drawing the current from the gate of the transistor.
• the bipolar transistors Q 3 to Q 4 may be provided with a transistor path composed of the electric field transistors 2 to 3, respectively.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Semiconductor Integrated Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Logic Circuits (AREA)

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• 2005
  • 2005-12-07 JP JP2005353163A patent/JP4926468B2/ja not_active Expired - Fee Related
• 2006
  • 2006-12-05 KR KR1020077026346A patent/KR101236088B1/ko not_active Expired - Fee Related
  • 2006-12-05 CN CN2006800156757A patent/CN101171680B/zh not_active Expired - Fee Related
  • 2006-12-05 US US11/912,412 patent/US7859805B2/en active Active
  • 2006-12-05 WO PCT/JP2006/324193 patent/WO2007066626A1/ja not_active Ceased
  • 2006-12-07 TW TW095145688A patent/TW200746926A/zh not_active IP Right Cessation

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