TWI729538B - 一種整合箝制電壓箝位電路的碳化矽半導體元件 - Google Patents

一種整合箝制電壓箝位電路的碳化矽半導體元件 Download PDF

Info

Publication number
TWI729538B
TWI729538B TW108138440A TW108138440A TWI729538B TW I729538 B TWI729538 B TW I729538B TW 108138440 A TW108138440 A TW 108138440A TW 108138440 A TW108138440 A TW 108138440A TW I729538 B TWI729538 B TW I729538B
Authority
TW
Taiwan
Prior art keywords
silicon carbide
type
gate
region
metal oxide
Prior art date
Application number
TW108138440A
Other languages
English (en)
Other versions
TW202036903A (zh
Inventor
顏誠廷
洪建中
許甫任
朱國廷
Original Assignee
大陸商上海瀚薪科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大陸商上海瀚薪科技有限公司 filed Critical 大陸商上海瀚薪科技有限公司
Publication of TW202036903A publication Critical patent/TW202036903A/zh
Application granted granted Critical
Publication of TWI729538B publication Critical patent/TWI729538B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7302—Bipolar junction transistors structurally associated with other devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本發明提供一種整合金屬氧化物半導體場效電晶體(MOSFET)以及雙向電壓箝的碳化矽半導體元件，透過上述的簡單結構以達到保護元件目的，有效避免閘極與源極間的正向過電壓及負向過電壓可能造成的元件損壞情況發生。

Description

一種整合箝制電壓箝位電路的碳化矽半導體元件
本發明為有關一種半導體功率元件，尤指一種碳化矽半導體元件。
碳化矽因為具有寬能隙的緣故，在相同的汲極耐壓(VDS, drain to source voltage)規格下，碳化矽金屬氧化物半導體場效電晶體(下文中以SiC MOSFET稱之)的特徵導通電阻(ron,sp=導通電阻*主動區面積)會遠小於矽金屬氧化物半導體場效電晶體(下文中以Si MOSFET稱之)。當比較Si MOSFET與SiC MOSFET的ID-VGS轉移特性可以發現：Si MOSFET的汲極電流(ID)隨著閘極電壓(Vgs) 上升很快就達到飽和(圖1)，但在SiC MOSFET中的汲極電流(ID)仍隨著閘極電壓(Vgs)上升而持續上升(圖2)。
因此，SiC MOSFET一般被操作在相對較高的閘極電壓以換取更低的導通電阻和更高的汲極電流，也由於上述特性，如圖3所示，SiC MOSFET的建議操作電壓(Vgsop, 請參考圖3的V1曲線)和閘極氧化層的崩潰電壓(breakdown voltage, BVgs, 請參考圖3的V2曲線)之間的餘裕(margin)，M1，相對於Si MOSFET的建議操作之閘極電壓(Vgs op, 請參考圖3的V3曲線)和閘極氧化層的崩潰電壓(breakdown voltage, BVgs, 請參考圖3的V4曲線)之間的餘裕M2較小。
在一具體實例中，Si MOSFET的建議操作電壓通常在10V至12V，閘極氧化層的崩潰電壓在60V以上。而SiC MOSFET 的建議操作之閘極電壓通常在15V至20V，閘極氧化層的崩潰電壓則只有35V至50V。
但是SiC MOSFET由於輸出電容小、切換速度快，使得SiC MOSFET的閘極電壓在切換過程中容易因為電路中的雜散電容與電感及很高的di/dt、dv/dt而發生振鈴(rining)現象，當發生振鈴時的閘極過電壓(overvoltage)超過閘極氧化層的崩潰電壓時，可能導致SiC MOSFET的閘極氧化層產生損壞；除此之外，SiC MOSFET也會因為特徵導通電阻低、輸入電容小，對於發生在閘極與源極間的靜電放電(electrostatic discharge, ESD)的耐受能力也隨之下降。
在Si MOSFET中，通常藉由在閘極與源極間並聯單向或雙向齊納二極體，來保護閘極免於因過電壓而損害同時增強閘極對靜電放電的耐受能力。舉例來說，在先前技術美國專利公告號US 6,172,383及US 6,413,822中，藉由外加或整合多晶矽齊納二極體的方式來保護閘極及增強其靜電放電的耐受能力。但外加齊納二極體有增加封裝複雜度、佔用空間、反應速度及引入額外雜散電感等問題，整合多晶矽齊納二極體則有多晶矽齊納二極體在高溫下崩潰電壓變小、漏電流增加等等不穩定的問題產生，對於可能應用在高溫下的SiC MOSFET並不適合。且無論外加或整合多晶矽齊納二極體，其漏電流都約在μA等級，遠大於MOSFET本身約在nA等級的閘極漏電流，因而增加閘極驅動電路的負擔及損耗。
因此，譬如美國專利公告號US 9,627,383藉由整合額外的側向MOSFET來保護閘極，但有結構較複雜且只能針對閘/源極間的負向過電壓(negative overvoltage)進行保護的問題。 有鑑於此，相關領域的碳化矽半導體元件在目前仍有待改良之處。
本發明的目的，在於解決習知碳化矽半導體元件因為特徵導通電阻低、輸入電容小，降低其中的閘極在切換過程中容易因為產生閘極過電壓而發生損壞的風險。
本發明的另一目的，在於增強習知碳化矽半導體元件因特徵導通電阻低、輸入電容小，對於發生在閘極與源極間的靜電放電的耐受能力較低的缺點。
為了達到上述目的，本發明提供一種整合有箝制電壓箝位電路的碳化矽半導體元件，藉此達到保護元件的目的，有效避免閘極與源極間的正向過電壓及負向過電壓可能造成的元件損壞情況發生。
因此，在本發明一實施例的整合箝制電壓箝位電路的碳化矽半導體元件中，包括一碳化矽基板，該碳化矽基板包括一第一表面以及與該第一表面相對設置的一第二表面；一金屬氧化物半導體場效電晶體，包括一碳化矽n型飄移層、一閘極、一源極、以及一汲極，其中該碳化矽n型飄移層、該閘極與該源極靠近該第一表面設置、該汲極則鄰設於該第二表面；以及一雙向電壓箝(bidirectional voltage clamp)，設置在該第一表面並包括一連接到該閘極的第一端子以及一連接到該源極的第二端子。
於一實施例中，該金屬氧化物半導體場效電晶體可為一n通道型金屬氧化物半導體場效電晶體(MOSFET)，於該碳化矽n型飄移層間隔設置有複數個p型井、至少一設置於該p型井的p型區域、至少一設置於該p型井的n型區域、一設置於該碳化矽n型飄移層上的閘極絕緣層(gate insulator)以及一連接該閘極的閘極電極以及一透過一歐姆接觸以連接至部分該n型區域及該p型區域的源極電極。
於一實施例中，該雙向電壓箝包括至少一與該p型井間隔有一第一距離的p型浮接區，該p型浮接區上包括一第一n型區域以及一第二n型區域，該第一n型區域以及該第二n型區域藉由一間隔區域而彼此分開，且該第一端子經由該第一n型區域上的歐姆接觸連接該閘極電極，且該第二端子經由該第二n型區域上的歐姆接觸連接該源極電極。
於一實施例中，該第一端子與該間隔區域之間可具有一第二距離，該第二端子與該間隔區域之間可具有一第三距離，且該第二距離大於該第三距離。
於一實施例中，該p型浮接區可包括一逆行式摻雜外形(retrograde doping profile)，該p型浮接區具有一底部以及一摻雜濃度低於該底部的頂部。
於一實施例中，該金屬氧化物半導體場效電晶體可為一平面金屬氧化物半導體場效電晶體。
於一實施例中，該金屬氧化物半導體場效電晶體可為一溝槽金屬氧化物半導體場效電晶體。
於一實施例中，該雙向電壓箝可抑制(suppress)施加在該閘極與該源極之間的一正向過電壓以及一負向過電壓。
於一實施例中，該正向過電壓以及該負向過電壓的絕對值可小於該金屬氧化物半導體場效電晶體的正向及負向閘極對源極擊穿電壓的絕對值。
於一實施例中，該正向過電壓的一絕對值可大於該負向過電壓的一絕對值。
於一實施例中，該雙向電壓箝包括複數個並聯連接的p型浮接區。
本發明藉由整合有金屬氧化物半導體場效電晶體與雙向電壓箝的碳化矽半導體元件，有效避免閘極與源極間的正向過電壓以及負向過電壓可能造成的元件損壞情況發生，進而達到保護元件目的。
有關本發明的詳細說明及技術內容，現就配合圖式說明如下：
本發明為一種整合箝制電壓箝位電路的碳化矽半導體元件，請參閱『圖4』及『圖5』，『圖4』為本發明一實施例的整合箝制電壓箝位電路的碳化矽半導體元件示意圖，『圖5』為『圖4』的A-A剖面示意圖。本發明的整合箝制電壓箝位電路的碳化矽半導體元件1包括一碳化矽基板10、一金屬氧化物半導體場效電晶體20以及一雙向電壓箝30，其中，該金屬氧化物半導體場效電晶體20可為一平面金屬氧化物半導體場效電晶體或為一溝槽金屬氧化物半導體場效電晶體。
根據本發明一實施例，該金屬氧化物半導體場效電晶體20包括一碳化矽n型飄移層21、一閘極22、一源極23以及一汲極24。該碳化矽基板10具有相對設置的一第一表面11以及一第二表面12，該碳化矽n型飄移層21、該閘極22與該源極23靠近該第一表面11設置，而該汲極24則設置在該第二表面12。該碳化矽n型飄移層21設置於該第一表面11上，摻雜濃度可介於1E14 cm-3 至1E17 cm-3 之間，該閘極22包括一設置於該碳化矽n型飄移層21上的閘極電極221。
該金屬氧化物半導體場效電晶體20還包括複數個p型井25以及一閘極絕緣層26，該p型井25彼此間隔設置在該碳化矽n型飄移層21中，部分的該p型井25包括至少一p型區域251以及至少一n型區域252，如『圖5』右側的該p型井25，而部分的該p型井25未包括該p型區域251以及該n型區域252，如『圖5』左側的該p型井25。本實施例中，該p型區域251的摻雜濃度可介於1E18 cm-3 至1E20 cm-3 之間，而該n型區域252的摻雜濃度可介於1E19cm-3 至1E20 cm-3 之間，上述的該n型飄移層21或該n型區域252可各自獨立地摻雜磷或氮，而該p型井25以及/或該p型區域251可摻雜鋁或硼。該閘極絕緣層26設於該碳化矽n型飄移層21上，該閘極絕緣層26可藉由熱氧化或由一具有高介電常數的材料(譬如氧化鋁(Al2O3))以化學氣相沉積或原子層沉積等方式形成，並經過例如含氮之氣體(譬如N2、NO 或N2O)在大於1000oC以上的溫度進行氮化回火(nitridation by post oxide annealing)。該源極23的至少部分底端形成一歐姆接觸27而電性連接至部分的該n型區域252及部分或全部的該p型區域251。
請合併參閱『圖6』，為『圖5』的部分上視示意圖，該雙向電壓箝30形成於該碳化矽n型飄移層21中，包括一第一端子31、一第二端子32以及一p型浮接區33，該p型浮接區33與該p型井25間隔有一第一距離D1，該p型浮接區33可由摻雜鋁或硼形成，且該p型浮接區33包括有至少一由摻雜磷或氮所形成之第一n型區域331以及至少一第二n型區域332。該第一n型區域331以及該第二n型區域332藉由一間隔區域S而彼此分開。該第一端子31與該間隔區域S之間具有一第二距離D2，該第二端子32與該間隔區域S之間具有一第三距離D3，該第二距離D2大於該第三距離D3，從『圖5』觀之，在本實施例中，該間隔區域S的寬度沿該第二n型區域332的邊緣為一等距離，而於其他實施例中，該間隔區域S的寬度沿該第二n型區域332的邊緣可為一不等距離。於該p型浮接區33中，該第一端子31經由該第一n型區域331上的該歐姆接觸27連接該閘極電極221，該第二端子32則經由該第二n型區域332上的該歐姆接觸27連接該源極23。據此，該閘極22與該源極23之間的一正向過電壓以及一負向過電壓可被該雙向電壓箝30抑制(suppress)，且於本實施例中，該正向過電壓的一絕對值大於該負向過電壓的一絕對值。
再者，上述的正向過電壓及負向過電壓的絕對值均會小於該金屬氧化物半導體場效電晶體20的正向及負向閘極對源極擊穿電壓的絕對值。
該p型浮接區33可包括一逆行式摻雜外形(retrograde doping profile)，且在該逆行式摻雜外形中，頂部的一摻雜濃度低於底部的一摻雜濃度。由於該雙向電壓箝30從垂直方向觀之可視為一寄生雙極性電晶體(Parasitic BJT)，透過調整該p型浮接區33的濃度分布，可以調整該寄生雙極性電晶體的基極開路崩潰電壓(open base breakdown voltage)。
於本發明另一實施例中，該雙向電壓箝30可更包括複數個並聯連接的p型浮接區33。由於單一個該雙向電壓箝30可吸收的能量有限，故增加該p型浮接區33的數量或面積可以增加整體靜電放電(electrostatic discharge, ESD)的耐受能力。
請續參考『圖7』，當比較本實施例整合有箝制電壓箝位電路的碳化矽半導體元件(實線)與習知不具有箝制電壓箝位電路的碳化矽半導體元件(虛線)的閘極漏電流(Igs)-閘極/源極電壓(Vgs)曲線時，結果顯示：在建議的閘極/源極電壓(Vgs)範圍內(即，閘極/源極電壓(Vgs)為-10V及20V)，本實施例的碳化矽半導體元件的漏電流(Igs)很低，約為數nA；但在相似的情況下，整合有多晶矽齊納二極體的碳化矽半導體元件的漏電流(Igs)可達數μA。顯見本實施例的碳化矽半導體元件可同時針對閘極與源極間的正向過電壓以及負向過電壓進行保護。
『圖8』則為本發明一實施例的整合箝制電壓箝位電路的碳化矽半導體元件在不同溫度時的閘極漏電流(Igs)-閘極電壓(Vg)曲線，結果顯示：在30℃至175℃之間的各種不同溫度下，本實施例的碳化矽半導體元件的閘極漏電流(Igs)-閘極電壓(Vg)曲線沒有太大的改變，顯示其對於溫度的敏感性較低，故即使在高溫下使用也不會產生如美國專利公告號US 6,172,383及US 6,413,822所揭示的碳化矽半導體可能發生的在高溫下崩潰電壓變小、漏電增加等不穩定的問題。
綜上，本發明藉由整合有金屬氧化物半導體場效電晶體與雙向電壓箝的碳化矽半導體元件，相較於如美國專利公告號US 9,627,383僅可針對閘/源極間的負向過電壓(negative overvoltage)進行保護的習知技術而言，本發明的設計可同時避免閘極與源極間的正向過電壓以及負向過電壓可能造成的元件損壞情況發生，進而達到保護元件目的。
1:碳化矽半導體元件 10:碳化矽基板 11:第一表面 12:第二表面 20:金屬氧化物半導體場效電晶體 21:碳化矽n型飄移層 22:閘極 221:閘極電極 23:源極 24:汲極 25:p型井 251:p型區域 252:n型區域 26:閘極絕緣層 27:歐姆接觸 30:雙向電壓箝 31:第一端子 32:第二端子 33:p型浮接區 331:第一n型區域 332:第二n型區域 D1:第一距離 D2:第二距離 D3:第三距離 S:間隔區域 V1:SiC MOSFET的建議操作電壓(Vgs op) V2:SiC MOSFET的閘極氧化層的崩潰電壓(BVgs) V3:Si MOSFET的建議操作電壓(Vgs op) V4:Si MOSFET的閘極氧化層的崩潰電壓(BVgs) M1、M2:Vgs op與BVgs之間的餘裕
『圖1』，為習知Si MOSFET的汲極電流(ID)-閘極電壓(Vgs)轉移特性示意圖。 『圖2』，為習知SiC MOSFET的的汲極電流(ID)-閘極電壓(Vgs)轉移特性示意圖。 『圖3』，為Si MOSFET及SiC MOSFET的建議操作電壓和閘極氧化層的崩潰電壓之間的餘裕差異示意圖。 『圖4』，為本發明一實施例的整合箝制電壓箝位電路的碳化矽半導體元件的上視示意圖。 『圖5』，為『圖4』的A-A剖面示意圖。 『圖6』，為『圖5』的部分上視示意圖。 『圖7』，為本發明一實施例的整合箝制電壓箝位電路的碳化矽半導體元件以及習知不具有箝制電壓箝位電路的碳化矽半導體元件的閘極漏電流(Igs)-閘極/源極電壓(Vgs)曲線。 『圖8』，為本發明一實施例的整合箝制電壓箝位電路的碳化矽半導體元件在不同溫度時的閘極漏電流(Igs)-閘極電壓(Vg)曲線。
10:碳化矽基板
11:第一表面
12:第二表面
20:金屬氧化物半導體場效電晶體
21:碳化矽n型飄移層
22:閘極
221:閘極電極
23:源極
24:汲極
25:p型井
251:p型區域
252:n型區域
26:閘極絕緣層
27:歐姆接觸
30:雙向電壓箝
33:p型浮接區
331:第一n型區域
332:第二n型區域
D1:第一距離
D2:第二距離
D3:第三距離
S:間隔區域

Claims (10)

  1. 一種整合箝制電壓箝位電路的碳化矽半導體元件，包括：一碳化矽基板，該碳化矽基板包括一第一表面以及與該第一表面相對設置的一第二表面；一金屬氧化物半導體場效電晶體，包括一碳化矽n型飄移層、一閘極、一源極以及一汲極，其中該碳化矽n型飄移層、該閘極與該源極靠近該第一表面設置，該汲極則設置於該第二表面，其中該碳化矽n型飄移層間隔設置有複數個p型井、至少一設置於該p型井的p型區域、至少一設置於該p型井的n型區域、一設置於該碳化矽n型飄移層上的閘極絕緣層以及一連接該閘極的閘極電極；以及一雙向電壓箝，設置在該第一表面並包括一連接到該閘極的第一端子以及一連接到該源極的第二端子，其中該雙向電壓箝包括至少一與該p型井間隔有一第一距離的p型浮接區，該p型浮接區上包括一第一n型區域以及一第二n型區域，該第一n型區域以及該第二n型區域藉由一間隔區域而彼此分開，且該第一端子經由該第一n型區域上的歐姆接觸連接該閘極電極，且該第二端子經由該第二n型區域上的歐姆接觸連接該源極。
  2. 如請求項1所述之碳化矽半導體元件，其中，該金屬氧化物半導體場效電晶體為一n通道型金屬氧化物半導體場效電晶體。
  3. 如請求項1所述之碳化矽半導體元件，其中，該第一端子與該間隔區域之間具有一第二距離，該第二端子與該間隔區域之間具有一第三距離，且該第二距離大於該第三距離。
  4. 如請求項1所述之碳化矽半導體元件，其中，該p型浮接區包括一逆行式摻雜外形(retrograde doping profile)，且在該逆行式摻雜外形中，該p型浮接區具有一底部以及一摻雜濃度低於該底部的頂部。
  5. 如請求項1所述之碳化矽半導體元件，其中，該金屬氧化物半導體場效電晶體為一平面金屬氧化物半導體場效電晶體。
  6. 如請求項1所述之碳化矽半導體元件，其中，該金屬氧化物半導體場效電晶體為一溝槽金屬氧化物半導體場效電晶體。
  7. 如請求項1所述之碳化矽半導體元件，其中，該雙向電壓箝抑制施加在該閘極與該源極之間的一正向過電壓以及一負向過電壓。
  8. 如請求項7所述之碳化矽半導體元件，其中，該正向過電壓以及該負向過電壓的絕對值小於該金屬氧化物半導體場效電晶體的正向及負向閘極對源極擊穿電壓的絕對值。
  9. 如請求項7所述之碳化矽半導體元件，其中，該正向過電壓的一絕對值大於該負向過電壓的一絕對值。
  10. 如請求項1所述之碳化矽半導體元件，其中，該雙向電壓箝包括複數個並聯連接的p型浮接區。
TW108138440A 2018-11-21 2019-10-24 一種整合箝制電壓箝位電路的碳化矽半導體元件 TWI729538B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862770714P 2018-11-21 2018-11-21
US62/770,714 2018-11-21

Publications (2)

Publication Number Publication Date
TW202036903A TW202036903A (zh) 2020-10-01
TWI729538B true TWI729538B (zh) 2021-06-01

Family

ID=70726852

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108138440A TWI729538B (zh) 2018-11-21 2019-10-24 一種整合箝制電壓箝位電路的碳化矽半導體元件

Country Status (3)

Country Link
US (1) US11222971B2 (zh)
CN (1) CN111211120B (zh)
TW (1) TWI729538B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11410990B1 (en) 2020-08-25 2022-08-09 Semiq Incorporated Silicon carbide MOSFET with optional asymmetric gate clamp
EP3979331A1 (en) 2020-09-30 2022-04-06 Infineon Technologies AG Silicon carbide device with transistor cell and clamp region
EP3979330A1 (en) * 2020-09-30 2022-04-06 Infineon Technologies AG Silicon carbide device with transistor cell and clamp regions in a well region
US12002890B2 (en) * 2021-05-21 2024-06-04 Samsung Electronics Co., Ltd. Semiconductor protection device
WO2024091956A1 (en) * 2022-10-28 2024-05-02 Stable Laser Systems, Inc. Getter vacuum pump to maintain vacuum pressure within a housing of a fabry-perot cavity

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101872970A (zh) * 2010-07-26 2010-10-27 邯郸市凯立科技有限公司 宽频补偿装置
TW201222828A (en) * 2010-11-18 2012-06-01 Alpha & Omega Semiconductor ACCUFET with integrated clamping circuit and manufacturing method thereof
TW201635487A (zh) * 2015-03-16 2016-10-01 Toshiba Kk 半導體裝置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6172383B1 (en) 1997-12-31 2001-01-09 Siliconix Incorporated Power MOSFET having voltage-clamped gate
US6413822B2 (en) 1999-04-22 2002-07-02 Advanced Analogic Technologies, Inc. Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer
US6515345B2 (en) * 2001-02-21 2003-02-04 Semiconductor Components Industries Llc Transient voltage suppressor with diode overlaying another diode for conserving space
US7244970B2 (en) * 2004-12-22 2007-07-17 Tyco Electronics Corporation Low capacitance two-terminal barrier controlled TVS diodes
JP4926468B2 (ja) * 2005-12-07 2012-05-09 ローム株式会社 静電破壊保護回路及びこれを備えた半導体集積回路装置
US9748346B2 (en) * 2014-11-25 2017-08-29 Alpha And Omega Semiconductor Incorporated Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
US8445917B2 (en) * 2009-03-20 2013-05-21 Cree, Inc. Bidirectional silicon carbide transient voltage suppression devices
JP5884617B2 (ja) * 2012-04-19 2016-03-15 株式会社デンソー 炭化珪素半導体装置およびその製造方法
US8773826B2 (en) * 2012-08-29 2014-07-08 Amazing Microelectronic Corp. Power-rail electro-static discharge (ESD) clamp circuit
US9171833B2 (en) * 2013-07-17 2015-10-27 Intersil Americas LLC Semiconductor structure for enhanced ESD protection
JP5968548B2 (ja) 2013-09-17 2016-08-10 三菱電機株式会社 半導体装置
US10103540B2 (en) * 2014-04-24 2018-10-16 General Electric Company Method and system for transient voltage suppression devices with active control
DE112015004093B4 (de) * 2015-01-16 2023-09-28 Fuji Electric Co., Ltd. Siliciumcarbid-halbleitervorrichtung und verfahren zum herstellen einer siliciumcarbid-halbleitervorrichtung
US10714346B2 (en) * 2017-01-24 2020-07-14 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing semiconductor device
CN208580747U (zh) * 2018-09-06 2019-03-05 江苏中科君芯科技有限公司 栅极双箝位的igbt器件
CN110492439B (zh) * 2019-07-08 2021-04-13 中车永济电机有限公司 适用于大功率SiCMOSFET的保护电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101872970A (zh) * 2010-07-26 2010-10-27 邯郸市凯立科技有限公司 宽频补偿装置
TW201222828A (en) * 2010-11-18 2012-06-01 Alpha & Omega Semiconductor ACCUFET with integrated clamping circuit and manufacturing method thereof
TW201635487A (zh) * 2015-03-16 2016-10-01 Toshiba Kk 半導體裝置

Also Published As

Publication number Publication date
CN111211120A (zh) 2020-05-29
CN111211120B (zh) 2022-08-12
US11222971B2 (en) 2022-01-11
US20200161466A1 (en) 2020-05-21
TW202036903A (zh) 2020-10-01

Similar Documents

Publication Publication Date Title
TWI729538B (zh) 一種整合箝制電壓箝位電路的碳化矽半導體元件
US8901647B2 (en) Semiconductor device including first and second semiconductor elements
KR101261962B1 (ko) 고 이동도 전압 금속 산화물 반도체 전계-효과 트랜지스터
US9899512B2 (en) Silicon carbide device and method of making thereof
JP2019517150A (ja) ボディ領域拡張部を用いた炭化ケイ素金属酸化物半導体（ｍｏｓ）デバイスセルにおける電界シールド
US8530964B2 (en) Semiconductor device including first and second semiconductor elements
EP3089216A1 (en) Split-gate power semiconductor field-effect transistor
US20080014693A1 (en) Silicon carbide vertical mosfet design for fast switching applications
CN106463527B (zh) 半导体装置
JP2018137324A (ja) 半導体装置
US20220392887A1 (en) Semiconductor device
TWI717713B (zh) 寬頻隙半導體裝置
US20200176561A1 (en) Cellular structure of silicon carbide umosfet device having surge voltage self-suppression and self-overvoltage protection capabilities
TW201824538A (zh) 半導體元件
US10269955B2 (en) Vertical FET structure
US20160276474A1 (en) Semiconductor device
US20200294993A1 (en) Electrostatic discharge (esd) robust transistors and related methods
CN111129002B (zh) 静电保护电路
US11579645B2 (en) Device design for short-circuitry protection circuitry within transistors
JP2014216573A (ja) 半導体装置
US20220384625A1 (en) Mos devices with increased short circuit robustness
WO2019174495A1 (zh) 防静电金属氧化物半导体场效应管结构
US11088073B2 (en) Semiconductor device
KR101444080B1 (ko) 반도체장치
US20230418319A1 (en) Semiconductor transistors having minimum gate-to-source voltage clamp circuits