Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
  • H03B1/00—Details
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
  • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
  • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
  • H03K2005/00019—Variable delay
  • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
  • H03K2005/00019—Variable delay
  • H03K2005/00058—Variable delay controlled by a digital setting
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]

Definitions

• the present invention relates generally to electronic circuits, and more particularly, to voltage controlled oscillators (VCOs).
• VCOs voltage controlled oscillators
• VCOs Voltage controlled oscillators
• PLL phase locked loop
• FIG. 1 illustrates in partial isometric form one embodiment of a multiple independent gate field-effect transistor (MIGFET).
• FIG. 2 illustrates in schematic diagram form a VCO in accordance with one form of the present invention.
• MIGFET multiple independent gate field-effect transistor
• FIG. 3 illustrates in schematic diagram form a VCO in accordance with another form of the present invention
• FIG. 4 illustrates in schematic diagram form a VCO in accordance with yet another form of the present invention
• FIG. 5 illustrates in schematic diagram form a control signal generation circuit for use with the VCO of claim 4
• FIG. 6 illustrates in graphical form an exemplary control signal supplied by the control signal generation circuit of FIG. 5
• FIG. 7 illustrates in perspective form a layout of multiple transistors having independent gates that may be used to implement any of the VCOs of FIGs. 2-4.
• the present invention provides, in one form, a VCO having one or more inverters.
• the inverters are formed using a MIGFET (multiple independent gate field effect transistor) that has two independent gates or control electrodes.
• the VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. Each inverter has a first transistor connected to a second transistor, wherein the first transistor has a first gate connected to an output of a preceding inverter and a second gate for receiving a bias signal.
• the MIGFETs are biased by an analog voltage to provide a predetermined amount of drive current to adjust either phase or frequency of the VCO.
• the disclosed VCO requires relatively less surface area, is simple, and is easy to implement. Also, as compared to prior art phase correction circuits, the disclosed VCO requires fewer conductors and fewer contacts, thus reducing resistance and parasitic capacitances, simplifying the circuit, and improving operating frequency range.
• FIG. 1 is a partial isometric view of one embodiment of a multiple independent gate field-effect transistor (MIGFET) 10 that can be used with the VCO 40 illustrated in FIG. 2 and described below.
• the MIGFET 10 includes a fin structure 12 formed over a substrate, for example a bulk substrate or silicon-on-insulator (SOI).
• the fin structure has first and second sidewalls.
• the fin structure 12 is formed from a semiconductor material.
• a dielectric layer 13 is formed over the surface of the substrate and the fin structure and a layer of gate material is formed over the dielectric layer 13 as illustrated in FIG. 1 to form gate electrodes on opposite sides of the fin structure 12.
• the gate material is formed over the substrate, the first sidewall of the fin to form a first gate 18, and the second sidewall of the fin to form a second gate 20.
• the first and second gates 18 and 20 have a predetermined height on the sidewalls of the fin structure 12, and are electrically isolated from each other.
• the gate material may be deposited over the top of the fin structure, and then selectively removed to provide isolation between the first and second gates 18 and 20.
• Fin structure 12 includes current terminal regions 14 and 16 located in each end of fin structure 12. hi one embodiment where the resultant transistor structure is a field effect transistor
• nitride layer 30 is formed over a top surface of the fin structure 12. In other embodiments, nitride layer 30 may be made of other materials (e.g. other dielectrics).
• the channel regions may be undoped, doped to be N-type semiconductor, P-type semiconductor, or a combination of N-type and P-type semiconductor.
• the illustrated embodiment discloses a transistor structure having two independent gates.
• a transistor structure may have more than two gate structures.
• the MIGFET 10 may have an additional gate on top of the fin structure 12 in place of the nitride layer 30.
• a plurality of transistors like MIGFET 10 may be connected together in parallel if additional drive strength is required.
• FIG. 2 illustrates, in schematic diagram form, a VCO 40 in accordance with one form of the present invention.
• VCO 40 includes inverters 42, 44, and 46.
• Inverter 42 is formed by a P-channel MIGFET 48 and an N-channel MIGFET 50.
• Inverter 44 is formed by a P- channel MIGFET 54 and an N-channel MIGFET 56.
• Inverter 46 is formed by a P-channel MIGFET 66 and an N-channel MIGFET 62.
• the P-channel MIGFET 48 has a source connected to a supply voltage V DD and a drain connected to a drain of the N-channel MIGFET 50.
• a first control electrode or gate of MIGFET 48 is connected to a node 52 and to a first gate of MIGFET 50.
• a second gate of MIGFET 48 is connected to a first bias voltage labeled V GP I.
• a second gate of MIGFET 50 is connected to a bias voltage labeled VGN I -
• a source of MIGFET 50 is connected to a supply voltage terminal labeled Vss-
• the P-channel MIGFET 54 has a source connected to the supply voltage V DD and has a drain connected to a drain of N-channel MIGFET 56.
• a first gate of MIGFET 54 is connected to the gate of MIGFET 56 at a node 58.
• a second gate of MIGFET 54 is connected to a bias voltage labeled V GP2 .
• a second gate of MIGFET 56 is connected to a bias voltage labeled V GN2 -
• a source of P-channel MIGFET 66 is connected to the supply voltage V DD -
• a drain of MIGFET 66 is connected to a drain of N-channel transistor 62 at node 52. Therefore, the output of inverter 46 is connected to an input of inverter 42.
• a first gate of MIGFET 66 is connected to a first gate of MIGFET 62.
• a second gate of MIGFET 66 is connected to a bias voltage V GPM5 where M is an integer. It should be understood that any number of additional inverters may be coupled in series between inverter 44 and inverter 46 such that the total number of inverter states is odd.
• such additional inverters would have the same configuration as the illustrated inverters of FIG. 2. It should also be appreciated that as few as one series-connected inverter may be implemented to form a VCO circuit.
• a second gate of MIGFET 62 is connected to a bias signal V GN M- It should be noted that an output of VCO 40 may be taken at any of nodes 52, 58 or 64 as each inverter has a preceding inverter coupled to an input thereof as a result of the feedback connection from inverter 46 to inverter 42 via node 52.
• VCO 40 functions to provide an oscillating signal.
• Each inverter of inverters 42, 44 and 46 function to change the logic state of the signal and thus creates an unstable or oscillating signal. For example, at node 52 a logic high signal is converted to a logic low signal at node 58. Similarly, the logic low signal at node 58 is converted back to a logic high signal at node 64, assuming that there are no intervening inverter stages between inverter 44 and inverter 46.
• the bias signal V GP ⁇ which is applied to the second gate of MIGFET 48 changes the conductivity of the MIGFET 48. In one form the conductivity is changed by changing the transistor's threshold voltage with respect to the first gate of MIGFET 48.
• the speed at which the transistor switches is modified.
• the frequency of operation of a circuit using the transistor varies.
• the MIGFET 48 As the voltage that is applied to the second gate is lowered, the MIGFET will switch when higher voltage is applied to the first gate.
• the switching speed of the MIGFET 48 is therefore increased because the transistor switches at a sooner point as the bias voltage applied to the first gate transitions from a logic high to a logic low.
• the N-channel MIGFETs such as MIGFET 50.
• the MIGFET 50 will switch when a lower voltage is applied to the first gate, and therefore the MIGFET 50 will have a higher conductivity for a given bias applied to the first gate.
• the switching speed of the MIGFET 50 is therefore increased because the transistor switches at a sooner point as the bias voltage applied to the first gate transitions from a logic low to a logic high. Therefore, the switch point for each of inverters 42, 44 and 46 may be individually modified with a separate second gate bias voltage.
• the modification of the switching speeds of the inverters functions to modify the phase relationships between the oscillating signals present at nodes 52, 58 and 64 and to change the frequency of operation of the VCO 40. Illustrated in FIG. 3 is a VCO 40' which is an alternate form of VCO 40 of FIG. 2.
• VCO 40' is a simplified form of VCO 40 since there are only two control or bias signals that modify the frequency of the circuit. It should be noted that while VCO 40' has simplified control, there are fewer frequency change settings. However, because the bias signals Vgp and Vgn are analog control signals that can have numerous values, the amount of frequency adjustment possible in VCO 40' is quite flexible.
• FIG. 4 Illustrated in FIG. 4 is yet another form of a VCO.
• the VCO of FIG. 4 has transistors which permit the control of instantaneous phase of the signal.
• the VCO may be used to change the instantaneous phase in response to a sensed or measured phase difference between a reference signal and a feedback signal of a phase locked loop (not shown).
• a first oscillator stage 43 has a first inverter formed by a P-channel MIGFET 48 and an N-channel MIGFET 50 and a second inverter formed by a P-channel MIGFET 66 and an N-channel MIGFET 68.
• MIGFET 48 has a source connected to a terminal for receiving a supply voltage labeled V D D, a first gate connected to a node 52 and to a first gate of MIGFET 50, a drain connected to a drain of MIGFET 50 at a node 58 and a second gate.
• the second gate of MIGFET 48 is connected to an analog control bias signal labeled Up P .
• a second gate of MIGFET 50 is connected to an analog control bias signal labeled U PN
• a source of MIGFET 50 is connected to a terminal for receiving a ground reference voltage labeled Vss-
• the first oscillator stage 43 also has a second inverter formed by a P-channel MIGFET 66 and an N-channel MIGFET 68.
• MIGFET 66 has a source connected to the terminal for receiving V DD , a first gate connected to the first gate of MIGFET 48 at node 52, a second gate connected to an analog control bias signal labeled DN P and a drain connected to a node 58.
• the drain of MIGFET 66 is connected to a drain of MIGFET 68.
• a first gate of MIGFET 68 is connected to the first gate of MIGFET 50 at node 52, and a second gate of MIGFET 68 is connected to a control bias signal labeled D NN .
• a source of MIGFET 68 is connected to the terminal for receiving Vss-
• the first oscillator stage 43 therefore has two parallel-connected inverters formed of series-connected MIGFET transistors that have separately controlled second gates.
• a second stage 45 has a first inverter formed of a P-channel MIGFET 60 and an N- channel MIGFET 62.
• MIGFET 60 has a source connected to the voltage terminal for receiving VD D , a first gate connected to a node 64, a second gate connected to a control bias signal labeled U PP , and a drain.
• MIGFET 62 has a drain connected to the drain of MIGFET 60, a first gate connected to the first gate of MIGFET 60 at a node 64, a second gate connected to a control bias signal labeled UP N , and a source connected to the terminal for receiving the voltage Vss-
• a second inverter formed of a P-channel MIGFET 70 and an N- channel MIGFET 72 is connected in parallel with the first inverter of second stage 45.
• a source of MIGFET 70 is connected to the voltage terminal for receiving V DD - MIGFET 70 has a first gate connected to the node 64, a second gate connected to a control bias signal labeled D NP , and a drain.
• a drain of MIGFET 70 is connected to a drain of MIGFET 72.
• a first gate of MIGFET 72 is connected to the first gate of MIGFETs 60, 62 and 70 at node 64.
• a second gate of MIGFET 72 is connected to a bias control voltage labeled DN N -
• a source of MIGFET 72 is connected to the terminal for receiving the voltage Vss-
• any additional number from one onward of stages may be provided as indicated by the dots between the first stage and the second stage, as long as the total number of stages is odd.
• the number of stages is dependent, in part, on the frequency range of operation that is desired. The fewer the number of stages results in a higher frequency of operation.
• a signal that is processed by the inverters of the VCO of FIG. 4 changes logic state between an input and an output of each inverter. Because node 52 connects the output of the inverter formed of MIGFETs 70 and 72 to the input of the inverter formed of MIGFETs 48 and 50, a continuous path is provided for a signal to continually change states.
• An output of the VCO may be taken at either node 52 or node 64. This output may be connected to other circuitry (not shown) such as a delay locked loop (DLL) or a phase locked loop (PLL).
• DLL delay locked loop
• PLL phase locked loop
• the phase of the signal may be compared with the phase of a reference signal. If the phase of the signal from the VCO of FIG.
• the phase may be changed through the use of the up and down bias signals Up and DN- Depending upon whether the bias signals are applied to a P-channel transistor or an N-channel transistor determines whether the Upp or the U P N signal is used for an up signal. Initially assume that the bias voltages Upp and U PN are set so that MIGFETs 48 and 50 are not conductive and that the bias voltages D NP and D NN are set so that MIGFETs 66 and 68 are conductive. If there is a phase difference between the signal and a reference signal, the analog bias signals can be modified to make MIGFETs 48 and 50 become slightly conductive and add drive strength to the collective inverter function of the first stage.
• the phase of the signal conducted by the first oscillator stage 43 is adjusted as needed.
• the Upp and U PN signals are used to increase the frequency of the signal. The increase in frequency shifts the phase of the signal in a positive direction.
• the DN P and D NN signals are used to decrease the frequency of the signal. The decrease in frequency shifts the phase of the signal in a negative direction. It should be appreciated that with the use of the Upp, U P N, D NP and D N N signals of the VCO of FIG. 4 both phase and frequency shifting of the signal may be implemented.
• the signals Upp and DN P may be kept constant and signals U PN and D NN may be varied to primarily modify the frequency of the signal. Additionally, variation of all four or combinations of all four of these signals may be made to change both the frequency and the phase of the VCO's signal. Illustrated in FIG. 5 is an exemplary implementation of a control signal circuit 80 to provide the control signal U P N O which is the UP N signal of a first stage in a VCO.
• the control signal circuit 80 has a voltage divider portion 82 and a drive output portion 84.
• a voltage divider is formed by a plurality of diode-connected P-channel transistors 86, 88, 90, 92, 94 and 96 that are connected between a supply voltage V DD and a reference voltage terminal Vss- At the drain of each of the transistors 86, 88, 90, 92, 94 and 96 is a tap in which a switch is connected.
• a switch 100 is connected to the drain of transistor 86.
• a switch 102 is connected to the drain of transistor 88.
• a switch 104 is connected to the drain of transistor 90.
• a switch 106 is connected to the drain of transistor 92.
• a switch 108 is connected to the drain of transistor 94.
• switches 100, 102, 104, 106 and 108 are implemented as CMOS transmission gates having a true and complementary control signal which is designated in FIG. 5 by an asterisk.
• Select voltages Vs 0 , Vsi, Vs 2 , Vs 3 and Vs 4 are respectively used to make the switches 100, 102, 104, 106 and 108 conductive.
• Each of switches 100, 102, 104, 106 and 108 has a terminal connected together to a node 110 and to a gate of an N-channel transistor 112.
• Transistor 112 has drain connected to the supply voltage terminal for receiving V DD - A source of transistor 112 is connected to a source of a P-channel transistor 114.
• a drain of transistor 114 is connected to a drain of an N-channel transistor 116 and provides the control signal Upp 0 for the first stage.
• a source of transistor 116 is connected to the Vss reference voltage terminal.
• Transistors 114 and 116 each has a gate connected together for receiving an enable signal labeled "Phase Detect" from a phase detector of a phase locked loop (not shown).
• a P-channel transistor 118 has a source connected to the V DD supply voltage terminal, a gate for receiving a full supply voltage control signal V S F and a drain connected to the source of transistor 114.
• a phase detector provides a logic low enable signal to the gates of transistors 114 and 116 when a phase error is detected in the signal of the VCO.
• the phase detector also functions to determine what analog voltage value the signal Upp 0 should assume. Should a full supply voltage V D D value be needed, the signal V SF is asserted as a logic low. Should a lower value of voltage be needed to correct the detected phase error, one of the signals from Vs 0 to Vs 4 is asserted and a predetermined fraction of V DD is used to drive transistor 112. The drive strength of the bias voltage for transistor 112 determines the value of voltage of the control signal Upp 0 .
• the signal value of U PPO may be changed readily by the phase detector by changing the control signals Vso to Vs 4 and V SF - Similar circuits (not shown) maybe used to generate the control signals U P N O , D NPO , DNN O , etc. of the VCO of FIG. 4.
• FIG. 6 Illustrated in FIG. 6 is a graph illustrating an embodiment of the signals UP PO and UPN O .
• a phase correction operation is implemented.
• an analog voltage control signal Uppo may assume any value between 0 volt to supply voltage V D D-
• a voltage of Vi, V 2 or Vz which are less than VD D may be connected to the second gate of MIGFET 48 of FIG. 4.
• an analog voltage control signal U P N O is selected having a value between 0 volt and VDD- A voltage of Vi, V 2 or Vz may be provided by control signal circuit 80 for biasing the second gate of MIGFET 50. Because an analog voltage is used fine tuning of phase and frequency errors may be accomplished.
• FIG. 7 Illustrated in FIG. 7 is a layout of an integrated circuit having three MIGFET transistors that may be used to implement a variety of circuits such as the VCO 40' of FIG. 3.
• a MIGFET 120 is placed adjacent to a MIGFET 122.
• a MIGFET 124 is placed adjacent the MIGFET 122 but any number of intervening MIGFET devices may be inserted as indicated by a broken line in FIG. 7.
• the MIGFET 120 has a first gate Gl which is gate 130.
• Gate 130 is common with MIGFET 122 and MIGFET 124 and is a continuous piece of conductive material.
• MIGFET 120 also has a second gate G2 which is gate 132.
• MIGFET 120 Between the gate 132 and gate 130 within MIGFET 120 is a source (S) and a drain (D) separated by a channel.
• MIGFET 122 has a second gate G3 which is gate 134. Between the gate 134 and gate 130 is a source (S) and a drain (D) separated by a channel.
• MIGFET 124 has a second gate G4 which is gate 136. Between the gate 136 and gate 130 is a drain (D) and a source (S) separated by a channel. It should be noted that the drains of MIGFETs 122 and 124 are positioned adjacent each other whereas the adjacent MIGFETs
• each of the MIGFETs 120, 122 and 124 have a drain positioned adjacent a source.
• the source, drain and channel of each of the MIGFETs 120, 122 and 124 form an elevated fin structure having a height extending above a plane in which the gates 130, 132, 134 and 136 lie.
• a single continuous gate material is used at the level in which the gate is formed rather than making a connection to the second gate of each MIGFET at a different level of the integrated circuit or laterally extended from the portion of the layout that is illustrated in FIG. 7.
• the layout is therefore compact and yet permits the first gate of each MIGFET to be physically separate and distinct.
• the illustrated source (S) and drain (D) electrodes of FIG. 7 are analogous to regions 14 and 16 of FIG.
• a fin structure is formed from a plurality of current electrodes (i.e. sources and drains) that, in one form, are arranged in a line.
• the line in FIG. 7 is a line (not expressly shown) that intersects each of the illustrated sources (S) and drains (D).
• S illustrated sources
• D drains
• a channel region is formed in the connecting material between each source and drain and adjacent each illustrated gate.
• a plurality of channel regions is formed between the sources and drains with one channel region between each source and drain. In one form the plurality of channel regions is formed parallel to the surface of the integrated circuit. In other forms the channel regions may be in different planes.
• a voltage controlled oscillator having a plurality of series-connected inverters.
• Each inverter of the plurality of series-connected inverters has a first transistor and a second transistor.
• the first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of a preceding inverter of the plurality of series- connected inverters, and a second control electrode for receiving a first bias signal.
• the second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor.
• the first bias signal is for adjusting a threshold voltage, the threshold voltage being a voltage required to form a channel in the first transistor in response to an input signal at the first control gate of the first transistor.
• the second control electrode of each of the first transistors is coupled together to receive the first bias signal.
• the second control electrode of each of the first transistors receives a different bias signal.
• the first bias signal is variable within a predetermined voltage range to adjust an oscillation frequency of the voltage controlled oscillator.
• the first bias signal is variable to change a conductivity of the first transistor, hi another form the second transistor is a second control electrode for receiving a second bias signal.
• the voltage controlled oscillator further has a third transistor, the third transistor having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to the second current electrode of the first transistor, a first control electrode coupled to the first control electrode of the first transistor, and a second control electrode for receiving a second bias signal, wherein the second bias signal is provided separately from the first bias signal.
• the second bias signal is variable within a predetermined voltage range for adjusting a phase of an output signal of the voltage controlled oscillator.
• a plurality of inverters is coupled together in series, each of the plurality of inverters having a first transistor and a second transistor coupled together in series between a first power supply terminal and a second power supply terminal, the first transistor and the second transistor both having a first control electrode coupled to an output terminal of another one of the plurality of inverters, and the first transistor having a second control electrode for receiving a first bias signal.
• a voltage of the first bias signal is varied to adjust an oscillation frequency of the voltage controlled oscillator, hi one form a different bias signal is provided to the second control electrode of each first transistor of the plurality of inverters, hi yet another form a second control electrode is provided for the second transistor of each of the plurality of inverters, the second control electrode receiving a second bias signal.
• a third transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the second current electrode of the first transistor, a first control electrode coupled to the first control electrode of the first transistor, and a second control electrode for receiving a second bias signal, wherein the second bias signal is provided separately from the first bias signal.
• the second bias signal is variable within a predetermined voltage range for adjusting a phase of an output signal of the voltage controlled oscillator.
• a fourth transistor having a first current electrode coupled to the second current electrode of the first transistor, a first control electrode coupled to the first control electrode of the second transistor, and a second control electrode for receiving a third bias signal, wherein the third bias signal is provided separately from the first bias signal.
• the third bias signal is variable within a predetermined voltage range for adjusting a phase of an output signal of the voltage controlled oscillator.
• an integrated circuit having a fin structure formed on a surface of the integrated circuit and having a height above the surface.
• the fin structure has a plurality of current electrodes and a plurality of channel regions wherein a single channel region is between any two of predetermined ones of the plurality of current electrodes.
• a first control electrode structure is formed adjacent to a first side of the fin structure and has a first strip of continuous conductive material that controls the plurality of channel regions.
• a second control electrode structure is formed adjacent to a second side of the fin structure opposite the first side of the fin structure.
• the second control electrode structure has multiple strips of the conductive material that are physically separate. Each of the multiple strips of the conductive material controls a separate, single one of the plurality of channel regions.
• the plurality of current electrodes has a plurality of sources and a plurality of drains
• the fin structure has a first drain positioned adjacent a physically unconnected first source and has a second drain positioned adjacent a physically unconnected third drain.
• the fin structure and the first and second control electrode structures form a plurality of multiple gate transistors.
• each of the multiple strips of the conductive material of the second control electrode structure is configured to receive a distinct separate voltage signal.
• plurality is defined as two or more than two.
• another is defined as at least a second or more.
• including and/or having, as used herein, are defined as comprising (i.e., open language).
• coupled is defined as connected, although not necessarily directly, and not necessarily mechanically.

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• 2005
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• 2006
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  • 2006-10-04 KR KR1020087008876A patent/KR101291522B1/ko not_active Expired - Fee Related
  • 2006-10-04 JP JP2008535582A patent/JP2009512344A/ja active Pending
  • 2006-10-04 WO PCT/US2006/039177 patent/WO2007047164A2/en not_active Ceased
  • 2006-10-11 TW TW095137372A patent/TW200721691A/zh unknown

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