JP2009512344A - マルチプル・ゲート・トランジスタを有する電圧制御発振器及びそのための方法 - Google Patents

マルチプル・ゲート・トランジスタを有する電圧制御発振器及びそのための方法 Download PDF

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Publication number
JP2009512344A
JP2009512344A JP2008535582A JP2008535582A JP2009512344A JP 2009512344 A JP2009512344 A JP 2009512344A JP 2008535582 A JP2008535582 A JP 2008535582A JP 2008535582 A JP2008535582 A JP 2008535582A JP 2009512344 A JP2009512344 A JP 2009512344A
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Japan
Prior art keywords
transistor
control electrode
bias signal
controlled oscillator
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2008535582A
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English (en)
Japanese (ja)
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JP2009512344A5 (enExample
Inventor
カルパット,スリラム・エス
マシュー,レオ
モーサ,モハメド
サッド,マイケル・エイ
サンチェズ,ヘクター
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NXP USA Inc
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NXP USA Inc
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Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2009512344A publication Critical patent/JP2009512344A/ja
Publication of JP2009512344A5 publication Critical patent/JP2009512344A5/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B1/00Details
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019Variable delay
    • H03K2005/00026Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019Variable delay
    • H03K2005/00058Variable delay controlled by a digital setting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2008535582A 2005-10-14 2006-10-04 マルチプル・ゲート・トランジスタを有する電圧制御発振器及びそのための方法 Pending JP2009512344A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/250,994 US7279997B2 (en) 2005-10-14 2005-10-14 Voltage controlled oscillator with a multiple gate transistor and method therefor
PCT/US2006/039177 WO2007047164A2 (en) 2005-10-14 2006-10-04 Voltage controlled oscillator with a multiple gate transistor and method therefor

Publications (2)

Publication Number Publication Date
JP2009512344A true JP2009512344A (ja) 2009-03-19
JP2009512344A5 JP2009512344A5 (enExample) 2009-09-17

Family

ID=37947377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008535582A Pending JP2009512344A (ja) 2005-10-14 2006-10-04 マルチプル・ゲート・トランジスタを有する電圧制御発振器及びそのための方法

Country Status (6)

Country Link
US (1) US7279997B2 (enExample)
JP (1) JP2009512344A (enExample)
KR (1) KR101291522B1 (enExample)
CN (1) CN101288223B (enExample)
TW (1) TW200721691A (enExample)
WO (1) WO2007047164A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013251892A (ja) * 2012-05-02 2013-12-12 Semiconductor Energy Lab Co Ltd 半導体装置
JP2018207281A (ja) * 2017-06-02 2018-12-27 三重富士通セミコンダクター株式会社 発振回路及び電圧制御装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612619B2 (en) * 2006-03-23 2009-11-03 Freescale Semiconductor, Inc Phase detector device and method thereof
US20090321834A1 (en) * 2008-06-30 2009-12-31 Willy Rachmady Substrate fins with different heights
KR101064129B1 (ko) 2009-07-13 2011-09-15 이화여자대학교 산학협력단 피드포워드 링 오실레이터
JP4945650B2 (ja) * 2010-03-10 2012-06-06 株式会社東芝 半導体装置
CN105026309B (zh) * 2013-03-28 2017-04-12 英特尔公司 多栅极谐振沟道晶体管
US9269711B2 (en) * 2013-07-01 2016-02-23 Infineon Technologies Austria Ag Semiconductor device
JP6561138B2 (ja) * 2015-05-20 2019-08-14 シーラス ロジック インターナショナル セミコンダクター リミテッド リング周波数分割器

Citations (3)

* Cited by examiner, † Cited by third party
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JPH10229166A (ja) * 1997-02-14 1998-08-25 Nec Corp 発振回路および遅延回路
US6756826B1 (en) * 2003-06-12 2004-06-29 Fairchild Semiconductor Corporation Method of reducing the propagation delay and process and temperature effects on a buffer
JP2008153786A (ja) * 2006-12-14 2008-07-03 Toshiba Corp トランスコンダクタ

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US4872010A (en) 1988-02-08 1989-10-03 Hughes Aircraft Company Analog-to-digital converter made with focused ion beam technology
US5144170A (en) * 1991-06-28 1992-09-01 Motorola, Inc. Circuit and method of aligning clock signals
US5463353A (en) * 1994-09-06 1995-10-31 Motorola, Inc. Resistorless VCO including current source and sink controlling a current controlled oscillator
US5675341A (en) 1995-06-02 1997-10-07 Lucent Technologies Inc. Current-mode parallel analog-to-digital converter
US6720812B2 (en) 1995-06-02 2004-04-13 Nova R&D, Inc. Multi-channel integrated circuit
US5604700A (en) 1995-07-28 1997-02-18 Motorola, Inc. Non-volatile memory cell having a single polysilicon gate
CA2286332A1 (en) 1997-04-11 1998-10-22 Wilex Biotechnology Gmbh Inhibitors for urokinase receptor
US5936433A (en) 1998-01-23 1999-08-10 National Semiconductor Corporation Comparator including a transconducting inverter biased to operate in subthreshold
US6222395B1 (en) 1999-01-04 2001-04-24 International Business Machines Corporation Single-ended semiconductor receiver with built in threshold voltage difference
US6133799A (en) * 1999-02-25 2000-10-17 International Business Machines Corporation Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS
JP2002111449A (ja) * 2000-09-29 2002-04-12 Mitsubishi Electric Corp 電圧制御発振回路およびそれを備える位相同期ループ回路
WO2002059706A2 (en) 2001-01-26 2002-08-01 True Circuits, Inc. Programmable current mirror
JP4794067B2 (ja) * 2001-05-24 2011-10-12 ルネサスエレクトロニクス株式会社 内部クロック発生回路
US6657502B2 (en) * 2001-10-01 2003-12-02 Motorola, Inc. Multiphase voltage controlled oscillator
US6677569B2 (en) 2001-10-12 2004-01-13 Massachusetts Institute Of Technology Methods and apparatus for performing signal processing functions in an electronic imager
JP2003163579A (ja) * 2001-11-26 2003-06-06 Eng Kk 周波数可変発振回路
US7214991B2 (en) * 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US6842136B1 (en) 2003-11-28 2005-01-11 Texas Instruments Incorporated Low-jitter clock distribution circuit
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10229166A (ja) * 1997-02-14 1998-08-25 Nec Corp 発振回路および遅延回路
US6756826B1 (en) * 2003-06-12 2004-06-29 Fairchild Semiconductor Corporation Method of reducing the propagation delay and process and temperature effects on a buffer
JP2008153786A (ja) * 2006-12-14 2008-07-03 Toshiba Corp トランスコンダクタ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013251892A (ja) * 2012-05-02 2013-12-12 Semiconductor Energy Lab Co Ltd 半導体装置
JP2018207281A (ja) * 2017-06-02 2018-12-27 三重富士通セミコンダクター株式会社 発振回路及び電圧制御装置

Also Published As

Publication number Publication date
CN101288223A (zh) 2008-10-15
TW200721691A (en) 2007-06-01
CN101288223B (zh) 2011-10-05
US7279997B2 (en) 2007-10-09
KR20080046260A (ko) 2008-05-26
WO2007047164A3 (en) 2007-09-27
US20070085153A1 (en) 2007-04-19
WO2007047164A2 (en) 2007-04-26
KR101291522B1 (ko) 2013-08-16

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