WO2007023911A1 - 半導体基板製造方法 - Google Patents
半導体基板製造方法 Download PDFInfo
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- WO2007023911A1 WO2007023911A1 PCT/JP2006/316635 JP2006316635W WO2007023911A1 WO 2007023911 A1 WO2007023911 A1 WO 2007023911A1 JP 2006316635 W JP2006316635 W JP 2006316635W WO 2007023911 A1 WO2007023911 A1 WO 2007023911A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 141
- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 claims description 70
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 150000001875 compounds Chemical class 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000005121 nitriding Methods 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 4
- 238000003475 lamination Methods 0.000 abstract 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 18
- 238000006243 chemical reaction Methods 0.000 description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 11
- 229910052594 sapphire Inorganic materials 0.000 description 11
- 239000010980 sapphire Substances 0.000 description 11
- 239000000243 solution Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 6
- -1 InN Chemical class 0.000 description 5
- 229910021529 ammonia Inorganic materials 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 229910052742 iron Inorganic materials 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 229910052758 niobium Inorganic materials 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 230000035882 stress Effects 0.000 description 4
- XOYLJNJLGBYDTH-UHFFFAOYSA-M chlorogallium Chemical compound [Ga]Cl XOYLJNJLGBYDTH-UHFFFAOYSA-M 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910003363 ZnMgO Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- VLTRZXGMWDSKGL-UHFFFAOYSA-N perchloric acid Chemical compound OCl(=O)(=O)=O VLTRZXGMWDSKGL-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000011345 viscous material Substances 0.000 description 2
- 229910000705 Fe2N Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- HKVFISRIUUGTIB-UHFFFAOYSA-O azanium;cerium;nitrate Chemical compound [NH4+].[Ce].[O-][N+]([O-])=O HKVFISRIUUGTIB-UHFFFAOYSA-O 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 230000001603 reducing effect Effects 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/38—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02389—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02491—Conductive materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
- H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP
Definitions
- the present invention relates to a method for manufacturing a semiconductor substrate.
- FIGS. 1 to 3 are process sectional views showing a method of manufacturing a GaN substrate.
- a sapphire base substrate 110 is prepared as a base substrate.
- a release layer (one layer of low-temperature GaN buffer) 120 is grown on the sapphire base substrate 110 at a temperature lower than 1000 ° C. (at a low temperature).
- the release layer 120 can be composed of, for example, a GaN single crystal, polycrystal, or amorphous body.
- the GaN layer 130 is grown at a temperature of about 1000 ° C. (at a high temperature).
- the GaN layer 130 can be composed of, for example, a single crystal of GaN.
- the structure 100 including the release layer 120 and the GaN layer 130 is formed on the sapphire base substrate 110.
- the release layer 120 also has a function of a buffer (buffer).
- the temperature of the sapphire base substrate 110 and the structure 100 (in the reaction chamber containing the sapphire) is lowered from about 1000 ° C. to room temperature.
- the thermal expansion coefficient of the sapphire base substrate 110 is larger than the thermal expansion coefficient of the GaN layer 130.
- thermal stress due to the difference in thermal expansion coefficient acts on the sapphire base substrate 110 and the GaN layer 130 and warpage occurs.
- the release layer 120 is melted by a laser lift-off method or the like.
- the GaN layer 130 is separated from the sapphire base substrate 110. That is, a GaN substrate is manufactured by making the GaN layer 130 stand alone from the sapphire base substrate 110.
- a portion where the internal stress is relaxed and a portion where the internal stress remains are generated. This may cause cracks in the GaN layer 130.
- the separated GaN layer 130 is warped because the strain distribution changes along the crystal growth direction. Therefore, the GaN layer is flattened by a mechanical polishing process. However, as shown in FIG. 3, the crystal orientation is shifted.
- Patent Document 1 In order to reduce such warpage, a method of forming a gap between the sapphire base substrate 110 and the release layer 120 has been proposed (for example, Patent Document 1).
- Patent Document 1 JP 2004-39810 A
- An object of the present invention is to provide a semiconductor substrate manufacturing method capable of improving throughput.
- the method for manufacturing a semiconductor substrate according to the first aspect of the present invention includes a preparation step of preparing a base substrate, and a stack in which at least two multilayer layers including a release layer and a semiconductor layer are stacked on the base substrate. And a separation step of separating the semiconductor layer.
- the separation layer is selected using a chemical solution in the separation step. Etching is performed to make each of the at least two semiconductor layers self-supporting.
- the semiconductor substrate manufacturing method according to the third aspect of the present invention is a continuous process without opening to the atmosphere in the stacking step. It is characterized by being laminated on.
- the semiconductor substrate manufacturing method according to the fourth aspect of the present invention includes a stacking process within the same apparatus in the stacking step. It is characterized by doing.
- the semiconductor substrate manufacturing method according to the fifth aspect of the present invention is characterized in that, in addition to the features of the semiconductor substrate manufacturing method according to any of the first to fourth aspects of the present invention, the base substrate and the half substrate
- the conductor layer is a compound semiconductor single crystal.
- a semiconductor substrate manufacturing method is characterized in that, in addition to the features of the semiconductor substrate manufacturing method according to the first aspect to the fifth aspect of the present invention, the base substrate and the half substrate The conductor layer is a compound of a group III element and nitrogen.
- a semiconductor substrate manufacturing method is characterized in that, in addition to the features of the semiconductor substrate manufacturing method according to any of the first to sixth aspects of the present invention, the base substrate and the half substrate The conductor layer is formed of the same material.
- the release layer includes a metal layer and a metal layer. And at least one of a metal nitride layer.
- the semiconductor substrate manufacturing method according to the ninth aspect of the present invention includes, in the stacking step, in a growth reactor of the semiconductor layer, The metal nitride layer is formed by nitriding the metal layer.
- a semiconductor substrate manufacturing method is characterized in that, in addition to the characteristics of the semiconductor substrate manufacturing method according to any one of the first to ninth aspects of the present invention, the multiple layer is formed of the peeling layer.
- a buffer layer is included between the separation layer and the semiconductor layer.
- the buffer layer is a single crystal of a compound semiconductor.
- a semiconductor substrate manufacturing method is characterized in that, in addition to the characteristics of the semiconductor substrate manufacturing method according to the tenth aspect or the eleventh aspect of the present invention, the buffer layer includes a group III element. It is a compound with nitrogen.
- the semiconductor substrate manufacturing method according to the thirteenth aspect of the present invention includes the buffer layer and the semiconductor in addition to the characteristics of the semiconductor substrate manufacturing method according to whether the tenth side force of the present invention is a deviation of the twelfth side surface.
- the layers are formed of the same material, and are characterized in that
- FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a conventional GaN substrate.
- FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a GaN substrate.
- FIG. 3 is a process cross-sectional view showing a conventional method for manufacturing a GaN substrate.
- FIG. 5 is a process cross-sectional view illustrating a problem of the present invention.
- FIG. 6 is a process cross-sectional view illustrating the problem of the present invention.
- FIG. 7 is a process cross-sectional view illustrating the semiconductor substrate manufacturing method according to the embodiment of the present invention.
- FIG. 8 is a process cross-sectional view illustrating a semiconductor substrate manufacturing method according to an embodiment of the present invention.
- FIG. 9 is a process cross-sectional view illustrating the semiconductor substrate manufacturing method according to the embodiment of the present invention.
- FIG. 10 is a process cross-sectional view illustrating the semiconductor substrate manufacturing method according to the embodiment of the present invention.
- FIG. 11 is a process cross-sectional view illustrating the semiconductor substrate manufacturing method according to the embodiment of the present invention.
- FIG. 12 is a cross-sectional SEM photograph of the sample obtained by the steps shown in FIGS.
- FIG. 13 is a process cross-sectional view illustrating the semiconductor substrate manufacturing method according to the embodiment of the present invention.
- FIG. 14 is a process cross-sectional view illustrating the semiconductor substrate manufacturing method according to the embodiment of the present invention.
- FIG. 15 is a process cross-sectional view illustrating the semiconductor substrate manufacturing method according to the embodiment of the present invention.
- FIGS. 4 to 6 are process sectional views showing the problems of the present invention.
- a method of manufacturing a GaN substrate (semiconductor substrate) using a GaN base substrate (base substrate) will be described as an example.
- the present invention manufactures another semiconductor substrate using another base substrate. It is applicable also to the method of doing.
- other base substrates include, for example, nitrides such as InN, A1N, InGaN, AlGaN, ⁇ 1 ⁇ , AlInGaN, group IV materials such as SiC and Si, oxides such as A1203, MgA1204, LiGa204, and ZnO, Alternatively, it can be composed of a nitridable metal such as Fe, Cr, Mo, Ta, Nb, Ti, or Cu.
- the other semiconductor substrate can be made of, for example, a nitride such as A1N, InN, and AlGalnN, or an oxide such as ZnO, ZnMgO, Zn CdO, and ZnMgCdO.
- a GaN base substrate 210 is prepared as a base substrate.
- a release layer (single metal buffer layer) 220 is formed on the GaN base substrate 210.
- the release layer 220 can be made of a nitridable metal such as Fe, Cr, Mo, Ta, Nb, Ti, or Cu.
- a GaN layer (semiconductor layer) 230 is grown on the release layer 220 at about 1000 ° C.
- the GaN layer 230 can be composed of, for example, a single crystal of GaN.
- the structure 200 including the release layer 220 and the GaN layer 230 is formed on the GaN base substrate 210.
- the release layer 220 also has a buffer function.
- the temperature of the GaN base substrate 210 and the structure 200 (in the reaction chamber in which the GaN substrate is placed) is lowered from about 1000 ° C. to room temperature.
- the thermal expansion coefficient of the GaN base substrate 210 is substantially equal to the thermal expansion coefficient of the GaN layer 230.
- the thermal stress due to the difference in thermal expansion coefficient hardly acts on the GaN base substrate 210 and the GaN layer 230, and warpage hardly occurs.
- the peeling layer 220 is selectively etched using a chemical solution.
- the GaN layer 230 is separated from the GaN base substrate 210. That is, the GaN substrate is manufactured by allowing the GaN layer 230 to stand up from the GaN base substrate 210.
- the internal stress is in a substantially uniform state. This reduces the risk of cracking in the GaN layer 130.
- FIGS. 7 to 11 and FIGS. 13 to 15 are process cross-sectional views illustrating a method for manufacturing a semiconductor substrate according to an embodiment of the present invention.
- FIG. 12 is a cross-sectional SEM photograph of the sample obtained by the steps shown in FIGS.
- a method of manufacturing a GaN substrate (semiconductor substrate) using a GaN base substrate (base substrate) will be described as an example, but a method of manufacturing another semiconductor substrate using another base substrate is also described. Applicable.
- other base substrates include, for example, InN, A1N, InGaN, AlGaN, Al ⁇ 1 ⁇ , nitrides such as AlInGaN, Group IV materials such as SiC and Si, oxides such as A1203, MgA1204, LiGa204, and ZnO, Alternatively, it can be made of a nitridable metal such as Fe, Cr, Mo, Ta, Nb, Ti, or Cu.
- the other semiconductor substrate can be made of, for example, a nitride such as A1N, InN, or AlGalnN, or an oxide such as ZnO, ZnMgO, ZnCdO, or Zn MgCdO.
- a GaN base substrate 310 is prepared as a base substrate.
- the thickness of the GaN base substrate 310 is preferably 100 ⁇ m to 500 ⁇ m.
- multilayer means a layer including two or more layers.
- a release layer (one metal buffer layer) 320 a is deposited on the GaN base substrate 310 by a sputtering method.
- the release layer 320a is a nitridable metal layer.
- the release layer 320a can be made of a nitridable metal such as Fe, Cr, Mo, Ta, Nb, Ti, or Cu.
- the thickness of the release layer 320a is preferably in the range of 15 nm to 75 nm.
- the release layer 320a is formed by an electron beam evaporation method (E-beam eva porator), a thermal evaporation method (Thermal evaporator), or a crystal growth method such as CVD, MOCVD, or MBE instead of the sputtering method. May be.
- E-beam eva porator electron beam evaporation method
- Thermal evaporation method Thermal evaporator
- crystal growth method such as CVD, MOCVD, or MBE instead of the sputtering method. May be.
- a part (upper layer) of the release layer 320a is nitrided in an atmosphere such as hydrogen gas containing ammonia at a substrate temperature in the range of 500 to 1000 ° C. Due to the strong reducing action of ammonia, even if there is a natural oxide film on the surface of the release layer 320a, the natural oxide film is reduced and nitrided. Then, the release layer 320a becomes the first release layer 320 and the second release layer 322.
- the first release layer (one metal buffer layer) 320 is a non-nitrided layer of the release layer 320a.
- the first release layer 320a is made of a nitridable metal such as Fe, Cr, Mo, Ta, Nb, Ti, or Cu. Can be configured.
- the second release layer (metal nitride layer) 322 is a nitrided layer of the release layer 320a, and may be composed of a metal nitride such as Fe2N, CrN, MoN, TaN, NbN, TiN, or CuN.
- the first release layer 320 is preferably Cr.
- the second release layer 322 is preferably CrN.
- the first release layer 320 also has a buffer function.
- the second release layer 322 also has a noffer (buffer) function.
- the release layer 320a may be entirely nitrided to form the second release layer 322.
- the thickness of the second release layer 322 is preferably in the range of 15 to 75 nm when the entire release layer 320a is formed by nitriding. However, the thickness of the second release layer 322 may be thinner than the thickness of the release layer 320a depending on the nitrogen condition.
- Process conditions for forming uniform second release layer 322 on the surface of release layer 320a Is mainly determined by the flow rate of ammonia, the nitriding temperature, and the nitriding time.
- the process conditions for this are preferably an ammonia flow rate l (lZmin), a nitriding temperature of 1000 ° C. or higher, and a nitriding time of 5 minutes or longer.
- the second release layer 322 functions as a nucleus for forming the GaN layer (the buffer layer 332 and the GaN layer 330) in the step shown in FIG. 9 described later. Accordingly, it is preferable that the process shown in FIG. 8 and the process shown in FIG. 9 are continuously performed without opening to the atmosphere as described later.
- a buffer layer 332 is grown on the second release layer 322 at a temperature of about 600 to 1000 ° C. (at a low temperature).
- HC1 gas is supplied to a Ga metal source box installed upstream of the reaction chamber via a reaction tube.
- HC1 gas and Ga undergo a chemical reaction to produce GaCl gas.
- the GaCl gas is supplied from the Ga metal source box to the reaction chamber via the reaction tube.
- hydrogen gas containing ammonia used in the process of FIG. 8 remains near the surface of the second release layer 322.
- GaCl gas and ammonia gas cause a chemical reaction, and a buffer layer 332 is formed on the second release layer 322.
- the buffer layer (GaN buffer layer) 332 can be composed of, for example, a single crystal body, a polycrystalline body, or an amorphous body of GaN.
- the thickness of the notfer layer 332 is preferably several tens A to several tens / zm.
- the temperature at which the buffer layer 332 is grown is preferably from 800 to: L 100 ° C, particularly preferably around 900 ° C.
- the buffer layer 332 is formed of the same material (GaN) as a GaN layer (semiconductor layer) 330 described later, the GaN layer (semiconductor layer) 330 is easily grown.
- the nother layer 332 may be formed of a material different from a GaN layer (semiconductor layer) 330 described later.
- the buffer layer 332 is formed of nitrides of A1N, AlxGayN, InxGayN, AlxGaynzN (0 ⁇ ⁇ 1, 0 ⁇ y ⁇ l, 0 ⁇ ⁇ 1, respectively), or an oxide such as ZnO. It ’s okay to go.
- a GaN layer (semiconductor layer) 330 is grown on the buffer layer 332 at a temperature of 1000 ° C. or higher (at a high temperature).
- the GaN layer (GaN thick film) 330 can be composed of, for example, a single crystal of GaN.
- the specific conditions are basically the same as in the process shown in FIG. 9 except that the flow rate of supplying HC1 gas to the strong Ga metal source box is large and the temperature in the reaction chamber is high. This makes it faster than the process shown in Figure 9 (eg, about 100 / z mZh or higher)
- the thickness of the GaN layer 330 is preferably 100 m to 500 m.
- the temperature at which the GaN layer 330 is grown is preferably 1000 ° C. or higher.
- a multilayer ML1 including the first release layer 320, the second release layer 322, the buffer layer 332, and the GaN layer 330 is formed on the GaN base substrate 310.
- the GaN layer 330 may be controlled to have a conductivity type such as n-type or p-type by doping a small amount of impurities such as Si and Mg during or after the growth.
- the temperature of the GaN base substrate 310 and the multilayer ML1 (inside the reaction chamber in which the GaN substrate is placed) is lowered from about 1000 ° C. to room temperature.
- the thermal expansion coefficient of the GaN base substrate 310 is substantially equal to the thermal expansion coefficient of the GaN layer 330.
- the GaN base substrate 310 and the GaN layer 330 are hardly subjected to thermal stress due to the difference in thermal expansion coefficient, and hardly warp.
- the multilayer ML1 as shown in the cross-sectional SEM photograph of FIG. 12 is obtained by the same process as that shown in FIGS.
- the GaN base substrate 310 and the GaN layer 330 have a flat shape. Accordingly, it can be estimated that almost no warpage occurs in the GaN base substrate 310 and the GaN layer 330.
- a plurality of multilayers ML1 to ML3 are formed on the Ga N base substrate 310 as shown in FIG.
- a structure 300 including a plurality of multilayers ML1 to ML3 is formed on the GaN base substrate 310.
- the steps of FIGS. 7 to 11 may be performed in the same apparatus or in different apparatuses.
- the reaction chambers When performed in different devices, the reaction chambers must be connected by a mechanism that can be transported without being exposed to the atmosphere.
- the plurality of first release layers 320 and the plurality of second release layers 322 are selectively etched simultaneously using a chemical solution. That is, as shown in FIG. 13, the plurality of first release layers 320 and the plurality of second release layers 322 are respectively etched from the side.
- the etchant is a mixed aqueous solution of perchloric acid (HC104) and second cerium nitrate ammonium.
- HC104 perchloric acid
- second cerium nitrate ammonium is preferred.
- an etchant chemical The solution is preferably an aqueous nitric acid (HN03) solution.
- Etchant chemical solution etch rate can be controlled by temperature and concentration.
- a plurality of units of the GaN layer 330 and the buffer layer 332 are respectively formed on the GaN foundation substrate. Separate from 310. That is, a plurality of GaN substrates SB1 to SB3 are simultaneously manufactured by independently supporting a plurality of units of the GaN layer 330 and the buffer layer 332 from the GaN base substrate 310, respectively. At this time, in each GaN layer 330, the internal stress is in a substantially uniform state. As a result, the risk of cracking in each GaN layer 330 is reduced.
- the buffer layer 332 is not etched by the etchant (chemical solution) and becomes a part of the Ga N substrates SB1 to SB3.
- the multiple multilayers ML1 to ML3 and the GaN base substrate 310 may be held by a viscous substance. Then, after the plurality of first release layers 320 and the plurality of second release layers 322 are etched, the viscous substance is melted, so that the plurality of GaN substrates SB1 to SB3 can be manufactured simultaneously. Good. In this case, a plurality of GaN substrates SB1 to SB3 can be manufactured stably.
- a plurality of GaN substrates SB1 to SB3 are manufactured at the same time, so that the throughput when manufacturing the GaN substrates SB1 to SB3 can be improved.
- the processes in FIGS. 7 to 11 are continuously repeated without opening to the atmosphere, it is possible to save time for evacuation and opening to the atmosphere (purging), and further increase the throughput when manufacturing a GaN substrate. It can be improved.
- the manufacturing conditions of the GaN substrates SB1 to SB3 can be made uniform, and variations in quality of the GaN substrates SB1 to SB3 can be reduced.
- steps of FIGS. 7 to 11 and the steps shown in FIGS. 14 and 15 may be performed continuously without opening to the atmosphere. In this case, the time for transferring the sample (lot) can be saved, and the throughput when manufacturing the GaN substrate can be further improved.
- the number of multiple layers included in the structure is not limited to three, and may be a number other than two or more. If the number of multiple layers included in the structure is large, the throughput in manufacturing the GaN substrate can be further improved. (Experimental example)
- the single first release layer 320 and the single second release layer 322 as shown in FIG. 11 are formed under the same conditions as in FIG. Etching was performed to make the single unit of the GaN layer 330 and the buffer layer 332 self-supporting from the GaN base substrate 310, and separately manufactured the GaN substrates S B1 to SB3.
- the time from loading the sample and unloading it as the GaN substrates SB1 to SB3 was 52 hours.
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Abstract
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JP2007532177A JPWO2007023911A1 (ja) | 2005-08-25 | 2006-08-24 | 半導体基板製造方法 |
US12/064,584 US8119499B2 (en) | 2005-08-25 | 2006-08-24 | Semiconductor substrate fabrication by etching of a peeling layer |
EP06796748.9A EP1930486A4 (en) | 2005-08-25 | 2006-08-24 | METHOD FOR PRODUCING A SEMICONDUCTOR SUBSTRATE |
KR1020087006102A KR101060289B1 (ko) | 2005-08-25 | 2006-08-24 | 반도체 기판의 제조 방법 |
CN2006800308730A CN101248221B (zh) | 2005-08-25 | 2006-08-24 | 半导体基板制造方法 |
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Cited By (4)
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JP2008308349A (ja) * | 2007-06-12 | 2008-12-25 | Tohoku Techno Arch:Kk | Iii族窒化物単結晶の製造方法、金属窒化物層を有する下地結晶基板、および多層構造ウエハ |
EP2031642A2 (en) * | 2007-08-28 | 2009-03-04 | Tohoku Techno Arch Co., Ltd. | Group III nitride semiconductor and a manufacturing method thereof |
JP2009184838A (ja) * | 2008-02-01 | 2009-08-20 | Toyoda Gosei Co Ltd | Iii族窒化物系化合物半導体基板の製造方法 |
KR20140057249A (ko) * | 2011-06-28 | 2014-05-12 | 쌩-고벵 크리스톡스 에 드테끄퇴르 | 반도체 기판 및 그 형성 방법 |
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JP2008308349A (ja) * | 2007-06-12 | 2008-12-25 | Tohoku Techno Arch:Kk | Iii族窒化物単結晶の製造方法、金属窒化物層を有する下地結晶基板、および多層構造ウエハ |
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JP2009184838A (ja) * | 2008-02-01 | 2009-08-20 | Toyoda Gosei Co Ltd | Iii族窒化物系化合物半導体基板の製造方法 |
KR20140057249A (ko) * | 2011-06-28 | 2014-05-12 | 쌩-고벵 크리스톡스 에 드테끄퇴르 | 반도체 기판 및 그 형성 방법 |
JP2014521212A (ja) * | 2011-06-28 | 2014-08-25 | サン‐ゴバン、クリストー、エ、デテクトゥール | 半導体基板及び形成する方法 |
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Also Published As
Publication number | Publication date |
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CN101248221B (zh) | 2012-06-06 |
CN101248221A (zh) | 2008-08-20 |
EP1930486A4 (en) | 2014-01-01 |
KR101060289B1 (ko) | 2011-08-29 |
US8119499B2 (en) | 2012-02-21 |
US20080299746A1 (en) | 2008-12-04 |
KR20080043833A (ko) | 2008-05-19 |
EP1930486A1 (en) | 2008-06-11 |
JPWO2007023911A1 (ja) | 2009-03-26 |
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