Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/04—Coating on selected surface areas, e.g. using masks
  • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
  • C23C14/34—Sputtering
  • C23C14/3435—Applying energy to the substrate during sputtering
  • C23C14/345—Applying energy to the substrate during sputtering using substrate bias
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
  • C23C14/34—Sputtering
  • C23C14/3471—Introduction of auxiliary energy into the plasma
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32082—Radio frequency generated discharge
  • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76844—Bottomless liners

Definitions

• the present invention relates to a film forming method and a film forming apparatus for effectively forming a metal film on the surface of a concave portion formed on the surface of an object to be processed such as a semiconductor wafer.
• a tantalum nitride film hereinafter also referred to as “TaN film” or a tantalum film (hereinafter referred to as “TaN film”) is used not only on the wafer surface but also in the plasma sputtering apparatus. (Also referred to as “Ta film”).
• a further tantalum film (the film formation conditions can be changed when the underlayer is a Ta film) is formed. As a result, a Norya layer is formed.
• a thin seed film made of a copper film is formed on the surface of the NORA layer, and then the entire surface of the wafer is subjected to a copper plating process to fill the recess.
• the bottom of the communication hole is formed to be “embedded” to a predetermined depth in the thickness direction of the lower wiring layer, and the bottom of the communication hole is embedded to “embed”
• a structure that reduces the contact resistance between the material and the underlying wiring layer is adopted.
• Such a structure is called a so-called punch-through structure.
• the method of creating the structure is called a so-called punch-through process.
• FIGS. 12A to 12C are views showing a state before filling the communication hole formed on the semiconductor wafer.
• 12A is a plan view of the semiconductor wafer before the communication holes are embedded
• FIG. 12B is a cross-sectional view taken along the line AA of the semiconductor wafer in FIG. 12A
• FIG. 12C is a perspective view of the semiconductor wafer in FIG. .
• FIGS. 13A to 13E are diagrams for explaining the process of filling the communication hole.
• the semiconductor wafer W also has a silicon substrate force, for example.
• a lower wiring layer 102 made of copper and an insulating layer 104 made of a silicon oxide film or the like are laminated in this order.
• a recess 105 is formed on the surface of the insulating layer 104.
• the recess 105 has a wiring groove having a predetermined width, that is, a trench 106 for forming an upper wiring layer.
• a communication hole 108 that partially penetrates the insulating layer 104 and reaches the lower wiring layer 102 is formed at the bottom of the trench 106.
• the communication hole 108 becomes a via hole or a through hole.
• the diameter L1 of the communication hole 108 is very small, for example, about 60 to 200 nm.
• the width L2 of the trench 106 is, for example, about 60 to lOOOnm.
• a barrier layer 110 made of a metal film is formed by, for example, plasma sputtering or the like for the purpose of improving adhesion with the underlayer, preventing diffusion of copper into the insulating layer 108, or preventing migration.
• the NOR layer 110 for example, a two-layer structure of a tantalum nitride film (TaN film) and a tantalum film (Ta film), or the same tantalum film formed with different film formation conditions. A two-layer structure is mainly adopted.
• the seed film 114 of electro plating is formed on the entire surface including the inner surfaces of the recess IJ recess 112, the communication hole 108, and the trench 106. Is formed very thin.
• the seed film 114 for example, a copper (Cu) film is used because copper plating is performed in a later process.
• the upper wiring layer 116 electrically connected to the lower wiring layer 102 is formed by scraping off unnecessary metal material on the upper surface by polishing or the like. To be done.
• a communication hole 108 such as a through hole or a via hole is provided at the bottom of the trench 106, and the shape of the recess 105 having a two-step section is the so-called dual damascen structure. It is called.
• the seed film 114 is formed on the shadow 120 of the deposited protrusion 118. Will not adhere. If a portion where the seed film 114 does not adhere is generated in this manner, as shown in FIG. 13D, a cavity, that is, a void 122 is generated in the portion, which is not preferable.
• FIG. 14A and FIG. 14B are diagrams for comparing the recesses 105 (trench 106) having different widths L2.
• FIGS. 14A and 14B there are many kinds of recesses 5 having different widths L2 on the surface of the semiconductor wafer W.
• the aspect ratio of the communication hole 108 this diameter L1 is the same
• the aspect ratio of the trench 106 is different
• the angles ⁇ 1 and ⁇ 2 for seeing upward from the bottom of the communication hole 108 are shown in the figure.
• they are different (0 1 ⁇ 2) 0.
• the thicknesses Hl and H2 of the barrier layer 110 deposited on the bottom of the communication hole 108 which is the lowermost layer of the recess are different.
• the depth of the cut recess 112 formed by scraping the NOR layer is varied.
• An object of the present invention is to provide a film forming method and a film forming apparatus for forming a metal film on the surface of a recess formed on the surface of an object to be processed, so that the bottom of the recess is formed by the same depth without depending on the width of the recess.
• To provide a film forming method and a film forming apparatus capable of forming a metal film in a suitable state in the concave portion and the cut concave portion by forming a cut concave portion having the same depth by cutting. is there.
• the inventors of the present invention appropriately adjust process conditions such as a noise voltage, DC power applied to a metal target, and power for plasma generation when forming a metal film by plasma sputtering.
• process conditions such as a noise voltage, DC power applied to a metal target, and power for plasma generation when forming a metal film by plasma sputtering.
• the knowledge that controlling the ratio between neutral atoms and metal particle ions generated from metal targets is effective for forming a good metal film over the entire surface of a semiconductor wafer.
• the present invention has been achieved.
• the present invention provides a process of placing a target object having a concave portion formed on a surface of a mounting table in a processing container, a process of evacuating the processing container, and a vacuumed processing container. Then, a process of generating metal particles containing metal ions by ionizing the metal target with plasma formed by converting the inert gas into plasma, and before being placed on the mounting table A bias power is applied to the object to be processed, and the plasma and the metal particles are drawn into the object to be processed, so that the bottom of the recess is scraped to form a recess, and the recess and the scraping are formed. And a step of forming a metal film on the entire surface of the object to be processed including the surface in the recess.
• a metal film such as a NORA film
• only the bottom of the recess is selectively scraped to form a scraped recess, and the inside of the recess and the surface in the scraped recess are formed.
• the amount of the metal film formed on the surface of the object to be processed other than the recess is substantially the same as the etching amount by the plasma of the inert gas.
• the first film forming step set as described above and the film forming amount of the metal film on the surface of the object to be processed other than the recess are set so that the amount of etching is slightly larger than the etching amount of the inert gas plasma.
• a second film formation step that has been performed.
• the amount of the metal film formed on the surface of the object to be processed other than the concave portion is substantially the same as the etching amount of the inert gas plasma.
• the etching is not caused by inert gas plasma so that the metal particles are drawn to the maximum extent in the range. It is preferable to have an auxiliary film-forming process with conditions set.
• the amount of the metal film formed on the surface of the object to be processed other than the recess is slightly larger than the etching amount by the plasma of the inert gas. It is preferable to have a second film formation step that is conditioned.
• the step of forming the metal film may be performed by controlling at least a part of the power for plasma generation, the direct current power applied to the metal target, and the bias power. Is set.
• the electric power for the plasmatization is within a range of 500 to 6000 watts.
• the DC power is controlled within a range of 100 to 12000 watts, and the bias power is controlled within a range of 100 to 2000 watts.
• a base film forming step of forming a base film is performed before the step of forming the metal film.
• a barrier layer having a two-layer structure is preferably formed by the base film and the metal film.
• the base film is a TaN film
• the metal film is a Ta film
• the base film is a Ta film
• the metal film is a Ta film formed under film formation conditions different from those of the base film.
• the concave portion is provided with a communication hole serving as a via hole or a through hole, and has a two-step shape.
• the recess is a communication hole serving as a via hole or a through hole.
• the present invention provides a processing container in which the inside can be evacuated, a mounting table provided in the processing container for mounting a target object having a recess formed on the surface, A gas introduction means for introducing a predetermined gas including at least an inert gas into the processing container, and a plasma generation source for generating plasma of the inert gas in the processing container using power for plasma generation And a metal target ionized by the plasma, and a bias power source for supplying a predetermined bias power to the mounting table.
• the film forming apparatus includes at least an apparatus control unit that controls the bias power source.
• a metal film such as a Norya film
• only the bottom of the recess is selectively scraped to form a recess, and the inside of the recess and the surface of the recess are
• a metal film is formed over the entire surface of the object to be processed. It is possible to always form a cut recess having the same depth without depending on the width of the recess.
• a good metal film for example, remarkably excellent in electric resistance characteristics, is formed over the entire surface of the object to be processed. It can be done.
• the apparatus control unit is set in such a manner that the amount of the metal film formed on the surface of the object to be processed other than the recess is substantially the same as the etching amount of the inert gas plasma.
• the first film formation step and the second film formation conditions are set such that the film formation amount of the metal film on the surface of the object other than the recess is slightly larger than the etching amount by the plasma of the inert gas. At least the bias power is controlled so that a film process is performed.
• the apparatus control unit sets conditions so that the amount of metal film formed on the surface of the object to be processed other than the concave portion is substantially the same as the etching amount of the inert gas plasma.
• the auxiliary particles are conditioned so that the metal particles are drawn to the maximum extent in a range where etching by inert gas plasma does not occur.
• At least the bias power supply is controlled so that the film process is performed.
• the apparatus control unit is set in such a manner that the amount of metal film formed on the surface of the object to be processed other than the concave portion is slightly larger than the etching amount of the inert gas plasma.
• at least the bias power source is controlled so that the second film forming step is performed.
• the apparatus control unit controls at least a part of power for plasmatization, direct-current power applied to a metal target, and bias power.
• the present invention provides a processing container in which the inside can be evacuated, a mounting table provided in the processing container for mounting an object to be processed having a recess formed on the surface, A gas introduction means for introducing a predetermined gas including at least an inert gas into the processing container, and a plasma generation source for generating plasma of the inert gas in the processing container using power for plasma generation And a metal target ionized by the plasma, and a bias power source for supplying a predetermined bias power to the mounting table.
• a control method for controlling a film forming apparatus comprising: cutting at least a bottom of a recess of the object to be processed; And at least a control method for controlling the bias power supply so that the metal film is formed on the entire surface of the object to be processed including the surfaces in the recesses and the cut recesses. It is a storage medium for storing a computer program for the purpose.
• FIG. 1 is a schematic cross-sectional view showing one embodiment of a film forming apparatus according to the present invention.
• FIG. 2 is a graph showing the angular dependence of sputter etching.
• FIG. 3 is a graph showing the relationship between the bias power and the amount of film formation on the upper surface of the wafer.
• FIGS. 4A to 4G are flowcharts for explaining a first embodiment of the method of the present invention.
• FIG. 5A to FIG. 5F are flowcharts for explaining a second embodiment of the method of the present invention.
• FIG. 6A is an electron micrograph showing a shaved recess formed by the method of the present invention
• FIG. 6B is an electron micrograph showing a shaved recess formed by a conventional method.
• FIG. 7 is a graph showing the relationship between the aspect ratio of the recess (including the communication hole) and the copper etching rate at the bottom of the recess.
• Fig. 8 is an enlarged cross-sectional view showing a concave ij recess.
• FIG. 9 is a graph showing an example of the dependency of the etching rate of the Ta film and Cu material on the bias power.
• FIG. 10A to FIG. 10F are flow charts for explaining a third embodiment of the method of the present invention.
• FIG. 11A to FIG. 11G are flowcharts for explaining a fourth embodiment of the method of the present invention.
• FIGS. 12 to 12C are views showing a state before the communication holes formed on the semiconductor wafer are embedded.
• FIG. 13A to FIG. 13E are views for explaining a process of filling a communication hole.
• FIG. 14A and FIG. 14B are diagrams for comparing recesses (trench) having different widths.
• FIG. 1 is a schematic sectional view showing an embodiment of a film forming apparatus according to the present invention.
• the film forming apparatus of the present embodiment is an ICP (Inductively Coupled Plasma) type plasma sputtering apparatus.
• the film forming apparatus 32 includes a processing container 34 formed into a cylindrical shape with, for example, aluminum.
• the processing vessel 34 is grounded, and an exhaust port 38 is provided at the bottom 36 of the processing vessel 34.
• the exhaust port 38 is connected to a vacuum pump 42 via a throttle valve 40, whereby the inside of the processing vessel 34 can be evacuated.
• a disk-shaped mounting table 44 made of, for example, aluminum is provided inside the processing vessel 34.
• An electrostatic chuck 46 is installed on the upper surface of the mounting table 44.
• a DC voltage for suction is applied to the electrostatic chuck 46 as required.
• the semiconductor wafer W as the object to be processed is attracted and held on the electrostatic chuck 46.
• the mounting table 44 is supported by a column 48 extending downward from the center of the lower surface of the mounting table 44.
• the lower part of the column 48 passes through the bottom 36 of the processing vessel 34 and can be moved up and down by an elevating mechanism (not shown). Thereby, the mounting table 44 itself can be moved up and down.
• An expandable bellows-shaped metal bellows 50 is provided so as to surround the support column 48.
• the upper end of the metal bellows 50 is airtightly joined to the lower surface of the mounting table 44, and the lower end of the metal bellows 50 is airtightly joined to the upper surface of the bottom portion 36.
• the mounting table 44 can be raised and lowered while maintaining the airtightness in the processing container 34.
• the mounting table 44 is formed with a refrigerant circulation path 52 through which a refrigerant for cooling the wafer W flows. The refrigerant is supplied and discharged through a flow path (not shown) in the column 48.
• three support pins 54 are provided upright on the container bottom 36 upward.
• a pin insertion hole 56 is formed in the mounting table 44.
• a gate valve 58 that can be opened and closed is provided on the lower side wall of the processing vessel 34 to allow the transfer arm to enter.
• the electrostatic chuck 46 provided on the mounting table 44 is connected to a noise power source 62 composed of a high frequency power source generating a high frequency of 13.56 MHz, for example, via a wiring 60.
• a noise power source 62 can control the bias power as its output as needed.
• a transmission plate 64 having a dielectric force such as aluminum nitride and being permeable to high frequencies is hermetically sealed via a seal member 66 such as an O-ring.
• a plasma generation source 70 in the processing space 68i ⁇ i ⁇ in the processing vessel 34 of the transmission plate 64 is provided.
• the plasma generation source 70 includes an induction coil unit 72 provided with a transmission plate 64 ⁇ i ⁇ , a high frequency power source 74 of 13.56 MHz for generating plasma connected to the induction coil unit 72, and the like. have.
• the plasma power output from the high-frequency power source 74 can be controlled as necessary.
• the plasma gas other inert gas such as He or Ne may be used instead of Ar.
• a baffle plate 76 made of, for example, aluminum is provided immediately below the transmission plate 64 for diffusing a high frequency introduced into the processing space 68.
• a variable DC power source 80 is connected to the metal target 78. The DC power from which the variable DC power supply 80 is also output can be controlled as necessary.
• tantalum metal or copper is used as the metal target 78. While these metals are sputtered as metal atoms or metal atomic groups by Arions in the plasma, many of them are ionized as they pass through the plasma.
• a cylindrical protective cover 82 made of, for example, aluminum is provided below the metal target 78 so as to surround the processing space 68.
• Protective cover 82 is grounded ing.
• the lower part of the protective cover 82 is bent inward and is positioned in the vicinity of the side part of the mounting table 44.
• a gas introduction port 84 is provided at the bottom 36 of the processing vessel 34 as a gas introduction means for introducing a predetermined gas required into the processing vessel 34.
• the gas inlets 8 4 and others are exposed to gas such as Ar gas or other necessary gases such as N gas.
• the gas is supplied through a gas control unit 86 including a flow rate controller and a valve.
• each component of the film forming apparatus 32 is connected to an apparatus control unit 88 made of, for example, a computer, and is controlled by the apparatus control unit 88.
• the device control unit 88 controls operations of the bias power source 62, the high frequency power source 74 for generating plasma, the variable DC power source 80, the gas control unit 86, the throttle valve 40, the vacuum pump 42, and the like. Yes.
• the following control is implemented.
• the processing vessel 34 is evacuated by operating the vacuum pump 42 under the control of the apparatus control unit 88.
• Ar gas is supplied into the evacuated processing container 34 while the gas control unit 86 is operated.
• the throttle valve 40 is controlled, and the inside of the processing container 34 is maintained at a predetermined degree of vacuum.
• DC power is applied to the metal target 78 via the variable DC power supply 80, and further, high frequency power (plasma power) is applied to the induction coil unit 72 via the high frequency power supply 74.
• the device control unit 88 also issues a command to the bias power source 62 to apply a predetermined bias power to the mounting table 44.
• argon plasma is formed by the plasma power applied to the induction coil section 72, and argon ions are generated.
• the argon ions collide with the metal target 78, and the metal target 78 78 is sputtered to release metal particles.
• the metal atoms and Z or metal atom groups that are metal particles from the sputtered metal target 78 are ionized as they pass through the plasma.
• the metal particles (metal atoms and Z or metal atomic groups) are scattered in a downward state in a state where ionized metal ions and electrically neutral metal atoms are mixed.
• the metal ion force is attracted by the bias power applied to the mounting table 44 and is highly directed to the wafer W, and is deposited on the wafer W as metal ions.
• the apparatus control unit 88 can also attract Ar ions in the plasma to the mounting table 44 side by giving, for example, an instruction to output a large output to the bias power source 62. Thus, it is possible to perform both film formation and sputter etching at the same time.
• each component of the apparatus is controlled by the apparatus control unit 88 based on a program created in advance so that the metal film forming process is performed under a predetermined condition. It has become.
• a program including various instructions for performing the control is stored in a storage medium 90 such as a floppy disk (registered trademark) (FD), a compact disk (registered trademark) (CD), or a flash memory. Based on the program, each component is controlled so that the metal film forming process is performed under predetermined conditions.
• FIG. 2 is a graph showing the angle dependency of sputter etching.
• FIG. 3 is a graph showing the relationship between the bias power and the amount of film formation on the wafer top surface.
• 4A to 4G are flowcharts for explaining the first embodiment of the method of the present invention.
• the method of the present invention is characterized by bias power, direct current power, plasma power, etc., when a metal film is formed by sputtering film formation by plasma in a specific step in a series of film formation processes.
• bias power direct current power
• plasma power etc.
• film formation by metal ion bow I and sputter etching by plasma gas (Ar ions) occur simultaneously, and the force is also reduced by the recess formed in the semiconductor wafer.
• the bottom of the lowermost layer of the recess is set to be scraped off, and the bottom of the lowermost layer of the recess is scraped to form a scraped recess, and a metal film is deposited on the surface of the recess and the scraped recess.
• the bias power at this time depends on the etching rate and force of the sputter etching by the plasma gas (Ar +) on the surface facing the metal target 78, that is, the upper surface of the wafer in FIG.
• the size is set to be approximately balanced.
• the etching rate of sputter etching with plasma gas is used.
• the angle of the sputter surface refers to the angle formed by the normal of the sputter surface and the incident direction (downward direction in FIG. 1) of the sputtering gas (Ar ion: Ar +).
• Ar ion: Ar + the sputtering gas
• the upper surface of the wafer and the bottom of the recess 5 are both “0 degree” and “90 degrees” on the side wall of the recess.
• the bias power applied to the wafer W side and the amount of film deposited on the upper surface of the wafer (not the side wall of the recess) are formed.
• the general operating condition in this type of sputtering apparatus is the region A1.
• a region where film formation by drawn metal ions and neutral metal atoms and sputter etching by plasma gas occur simultaneously is selected. More specifically, a region A2 on the upper surface of the wafer is selected such that the film formation rate by the drawn metal ions and neutral metal atoms and the etching rate of the sputter etching by the plasma gas are approximately balanced.
• substantially balanced means not only when the film deposition force on the upper surface of the wafer is “zero”, but also when the film deposition amount is as small as 3Z10 compared to the film deposition amount in the area A1. Is also included.
• the wafer W is loaded into the processing container 34 that can be evacuated through the gate valve 58 of the processing container 34. Wafer W is supported on support pins 54. When the mounting table 44 is also lifted by this state force, the wafer W is delivered to the upper surface of the mounting table 44. The wafer W is attracted to the upper surface of the mounting table 44 by the electrostatic chuck 46.
• the concave portion 5 (see FIG. 4A) is formed in advance in the previous process on the upper surface of the wafer W before carrying in. That is, the insulating layer 4 is formed on the lower wiring layer 2 made of Cu, and the recess 5 is formed in the insulating layer 4.
• the recess 5 has a wiring groove having a predetermined width for forming an upper wiring layer, that is, a trench 6.
• a communication hole 8 that partially penetrates the insulating layer 4 and reaches 2 layers of the lower wiring layer is formed at the bottom of the trench 6. Accordingly, the concave portion 5 has a two-step shape as a whole.
• the communication hole 8 becomes a via hole or a through hole.
• a base film forming process for forming the base film 10A is performed.
• N gas as a nitriding gas is supplied into the processing vessel 34 from the gas inlet 84 in addition to, for example, Ar gas which is a plasma gas.
• a TaN film is formed as the base film 10A substantially uniformly not only on the upper surface of the wafer W but also on the side wall and the bottom surface in the recess 5.
• the bias power at this time is the area A1 in FIG. 3 and is the same as the conventional general film formation conditions. Specifically, it is about 100W (Watt).
• a metal film forming step which is a feature of the present invention, is then performed in order to form a Ta film as the metal film. That is, in this metal film forming process, the bias power is increased and the conditions in the region A2 in FIG. 3 are used.
• the metal film forming process of the present embodiment conditions were set so that the film formation amount by the metal particles and the etching amount by the plasma of the inert gas were substantially the same on the surface of the wafer W other than the recess 5.
• the force is composed.
• the noisy power is set to point XI in FIG. 3 in order to set the film formation amount on the wafer upper surface to “zero”.
• the bias power at this time is 350W.
• the supply of N gas from the gas inlet 84 is stopped and only Ar gas is supplied.
• Ta represents a neutral metal atom
• Ta + represents a metal ion
• Ar + is an Ar ion and contributes to etching. Since Ta and Ta + reach sufficiently on the upper surface of the wafer, and Ar + also reaches sufficiently, the film formation becomes “zero” (cancelled) as a result.
• the process proceeds to the second film formation step.
• a point other than the point XI in the bias power force area A2, for example, A3 is set, and the film formation rate is much smaller than the film formation rate in the area A1, and slightly.
• a thick metal film is formed.
• a Ta film 10B is formed as a metal film on the entire wafer surface excluding the bottom of the communication hole 8, that is, on the surface in the recess 5 (including the side surface of the communication hole 8). Is done.
• the etching rate is higher than the film formation rate for the reason described above, so that the Ta film is further scraped off without adhering. For this reason, the hollow shape of the shroud recess 12 is further increased. That is, “ ⁇ Ta + ⁇ Ta + > ⁇ Ar +” is formed on the upper surface of the wafer, and “ ⁇ Ta + ⁇ Ar +” is formed at the bottom of the communication hole 8.
• the etching rate at the bottom is the wafer
• the amount of metal particles that contribute to film formation is set to be larger than that of sputter ions so that a film is deposited slightly on the upper surface, which is smaller than in the case of the first film formation process.
• the film formation amount on the wafer surface and the sputter etching amount are balanced in the first film formation step, so that after the process of FIG. 4C is completed.
• the thickness of the base film 10A in FIG. 4B does not change.
• the base film 10A in FIG. 4B has a thickness of, for example, 3.5 nm on the wafer surface and, for example, 1. Onm at the bottom of the communication hole 8, regardless of the depth of the hole in the recess. is there .
• These values are preferably lOnm or less, and more preferably 5 nm or less.
• the thickness of the NOR layer 110 in FIG. 13A depends on the depth of the hole of the shaving recess. If the depth of the IJ recess is about 50 nm, a barrier layer thickness of about 60 nm on the wafer surface is required. This is because the wafer surface is simultaneously etched by the Ar etching process of FIG. 13B. Here, if a 60 nm barrier layer is formed on the wafer surface, it is inevitable that a barrier layer having a thickness of about lOnm to 20 nm is formed at the bottom of the communication hole.
• conditions are set so that the film formation amount on the wafer surface is substantially zero through the first film formation process and the second film formation process, so refer to FIG. 13B.
• the deposition protrusion 18 does not occur on the side surface of the recess.
• the depth of the cut-out recess 12 formed in this embodiment is not dependent on the width L2 of the recess, and can be substantially reduced within the wafer surface, because the underlying film at the bottom of the communication hole can be made extremely thin. Can be homogenized
• the metal film 10B made of the Ta film by forming the metal film 10B made of the Ta film, the barrier layer 10 made of the stacked structure of the TaN film and the Ta film is formed. Thereafter, the wafer W is loaded into a film forming apparatus having the same configuration as that shown in FIG. 1 in which the metal target is formed of copper instead of tantalum. In this case, the plasma power is set in the region A1 in FIG. 3, and under the same condition setting as in the conventional method, as shown in FIG. However, the seed film 14 made of copper is formed thin.
• the film forming apparatus mounted with the copper metal target as described above is connected to the film forming apparatus mounted with the tantalum metal target through a transfer chamber that can be evacuated. It is preferred that As a result, the semiconductor wafer W can be transferred between both film forming apparatuses in a vacuum atmosphere without exposing it to the air.
• the wafer W is taken out from the film forming apparatus and subjected to a normal plating process.
• the recess 5 is completely filled with the material of the wiring layer 16 made of copper.
• only the bottom of the bottom layer of the recess 5 is selectively selected by appropriately selecting the process conditions when forming a metal film such as a NORA film.
• a metal film can be formed on the entire surface of the object to be processed (wafer W) including the surface in the recess 5 while being scraped.
• wafer W the entire surface of the object to be processed
• the setting conditions of the metal film forming process that is, the setting conditions that can realize the state in the region A2 in FIG. 3 are as follows.
• Plasma power 500 ⁇ 6000W
• condition (operating point) in the area A 2 is realized by appropriately setting the above three conditions. If conditions are set in a portion other than the region A2, the ridge IJ recessed portion 12 is not sufficiently formed, and a so-called punch-through structure cannot be formed.
• the flow rate of Ar gas is in the range of about 50 to 1000 sccm, and the process pressure is in the range of about 0.001 Torr (0. lPa) to about 0.1 lTorr (13.3 Pa). is there
• the TaN film is formed as the base film 10A for the base film formation step. It was revealed. Instead, a Ta film may be formed as the base film 1 OA. In this case, since the Ta film 10B is formed on the Ta film serving as the base film 10A, the NOR layer 10 is formed in a two-layer structure of Ta films having different film forming conditions.
• the operating point is set to the point XI in FIG. 3, and the cut recess 12 is formed without depositing the Ta film.
• the process shown in FIG. 4C in the flowcharts shown in FIGS. 4A to 4G is not performed, and the process force shown in FIG. 4B is directly shifted to the process shown in FIG. 4D.
• the Ta film 10B may be deposited simultaneously with the formation of the recess IJ recess 12. That is, in the second embodiment, when the process shown in FIG. 4B is performed, the second film forming process shown in FIG. 4D is immediately performed without performing the first film forming process shown in FIG. 4C.
• FIG. 5A to FIG. 5F are flowcharts for explaining the second embodiment of the method of the present invention as described above.
• 5A to 5F the same components as those shown in FIGS. 4A to 4G are denoted by the same reference numerals.
• FIGS. 5A and 5B correspond to FIGS. 4A and 4B, respectively
• FIGS. 5C to 5F correspond to FIGS. 4D to 4G, respectively.
• the TaN film forming process shown in FIG. 5B is directly shifted to the second film forming process shown in FIG. 5C without performing the first film forming process.
• the depth of the concave recess 12 is reduced by that amount, but conversely, the processing time is shortened by the amount not performing the first film forming step. can do.
• FIG. 6A is an electron micrograph showing a shaved recess formed by a conventional method
• FIG. 6B is an electron micrograph showing a shaved recess formed by the method of the present invention.
• Each photograph is accompanied by a schematic diagram for easy understanding.
• FIG. 7 is a graph showing the relationship between the aspect ratio of the recess (including the communication hole) and the copper etching rate at the bottom of the recess.
• characteristic A shows the case of the conventional method
• characteristic B shows the case of the method of the present invention.
• a barrier layer of approximately 60 nm is plasma sputtered on the wafer surface with respect to a plurality of recesses having various aspect ratios, and thereafter Ar etching is performed for a predetermined time. It was done. The depth of the cut recess formed at this time was measured to obtain the copper etching rate.
• a base film of about 4 nm is plasma-sputtered on the wafer surface with respect to a plurality of recesses having various aspect ratios.
• the characteristic first film forming step (see FIG. 4C) of the present invention was performed for the same predetermined time. The depth of the cut recess formed at this time was measured to obtain the copper etching rate.
• the aspect ratio when the aspect ratio is small in both the characteristics A and B, the amount of film formation on the bottom of the recess is increased as compared with the case where the aspect ratio is large. This reduces the copper etch rate.
• the copper etching rate changes as the aspect ratio increases. Therefore, the depth of the recess 12 due to the difference in the aspect ratio. You can see that it changes. This is not preferred.
• the aspect ratio when the aspect ratio is 2 or less, the copper etching rate changes greatly. When the aspect ratio is 2 or more, the copper etching rate is substantially constant. You can see that
• the aspect ratio is often 2 or more. Therefore, according to the method of the present invention, it was confirmed that the depth of the recessed recesses 12 related to the aspect ratio can be made substantially uniform, and good results can be obtained. In this way, the depth force of the ridge IJ recess 12 is not affected by the shape of the recess 5, so that the same depth of cutting is always achieved without depending on the width of the recess. A recess can be formed.
• the force for forming the seed film 14 in the step shown in FIG. 4E after forming the Ta film 10B in the step shown in FIG. 4D is not limited to this.
• an etching process using an inert gas such as Ar gas may be performed between the above two processes to improve the cross-sectional shape of the concave recess 12.
• An example of the results of this cross-sectional area improvement is shown in Figure 8.
• FIG. 8 is an enlarged sectional view showing the ridge ij recess 12.
• the Ta film 10B forming process shown in FIG. 4D is followed by a plasma etching process using, for example, Ar gas, and the bottom of the ridge IJ recess 12 is further enlarged to reverse the cross section.
• the contact resistance is further reduced by improving the contact area and the degree of adhesion with the embedding material of the recess 12.
• the Ta film 10B is not cut, and only the Cu material that is the wiring layer 2 needs to be cut. This can be achieved by adjusting the bias power.
• FIG. 9 is a graph showing an example of the dependence of the etching rate of the Ta film and Cu material on the bias power.
• Cu material begins to etch when the bias power is 40 watts or more
• Ta film begins to be etched when the bias power is 100 watts or more. Therefore, in the case shown in Fig. 9, it is confirmed that by setting the bias power to the region Y within the range of 40-: LOO watts, it is possible to selectively etch only the Cu material without removing the Ta film. it can.
• the characteristic line shown in FIG. 9 moves in the left-right direction depending on the magnitude of other plasma power, etc., and the region Y also fluctuates in the left-right direction accordingly.
• the following aspect may be adopted as the third embodiment. That is, in the first embodiment, the first film formation step shown in FIG. 4C and the second film formation step shown in FIG. 4D are performed together. In the third embodiment, the first film formation step shown in FIG. 4C is performed. After performing the first film formation step, the step shown in FIG. 4E is performed immediately without performing the second film formation step shown in FIG. 4D.
• FIGS. 10A to 10F are flowcharts for explaining the third embodiment of the method of the present invention as described above. 10A to 10F, the same reference numerals are given to the same components as those shown in FIGS. 4A to 4G.
• FIGS. 10A to 10C correspond to FIGS. 4A to 4C, respectively
• FIGS. 10D to 10F correspond to FIGS. 4E to 4G, respectively.
• the first film forming process force shown in FIG. 10C is also used as the seed film 1 shown in FIG. 10D. Since it shifts directly to the formation process of No. 4, it seems that the Norya layer 10 becomes a single underlayer 10A made of TaN film. In reality, however, a very small amount of Ta film (not shown) is deposited on the sidewalls of the trench 6 and the communication holes 8 in the step shown in FIG. 10C. The reason for this is that, as shown in FIG. 2, almost no sputter etching is performed on the side wall, while Ta-Ta + is deposited on the side wall although a trace amount is present.
• the NORA layer 10 includes a base film 10 made of a TaN film and a Ta film (not shown) partially formed on the base film 10 as described above. And a two-layer structure. Therefore, when the sheet film 14 made of Cu is formed on the NOR layer 10 in a later step, the adhesion between the barrier layer 10 and the seed film 14 can be maintained high.
• the processing time can be shortened by the amount by which the second film forming step shown in FIG. 4D is omitted.
• the force using a TaN film as the base film 10A is not limited to this.
• a Ta film may be used as the base film 10A, and this may be used as the barrier layer 10.
• the Norya layer 10 is a Ta film single layer. Then, when the seed film 14 made of Cu is formed on the NOR layer 10 made of Ta film in a later step, the adhesion between the barrier layer 10 and the seed film 14 can be kept high.
• the bias power is set to the area A3 in FIG.
• the bias power is set to the area A1
• the etching by the inert gas plasma is not substantially performed in the fourth embodiment.
• An auxiliary film formation process is performed with conditions set so as to draw the maximum amount.
• FIG. 11A to 11G are flowcharts for explaining the fourth embodiment of the method of the present invention as described above.
• the auxiliary film formation step is performed only for a very short time, and the thickness of the deposited Ta film is very small.
• the Ta film is deposited under the conditions of area A1, so that A small amount of Ta film 10B is deposited not only on the surface and the side surface of the recess, but also on the bottom of the recess 12.
• the processing time of the process is set so that the film thickness H2 deposited on the bottom of the embossed recess 12 is usually about 1 nm, and at most 3 nm. This is because the thickness of the Ta film, which has a higher resistance than copper, is reduced to promote high resistance while maintaining high adhesion to the lower layer.
• the thickness H2 of the Ta film at the bottom of the recess 12 is about lnm (at most about 3nm), there is little adverse effect on the electrical resistance in this portion, and the lower layer This can be maintained at a high level without almost deteriorating the adhesion to the Cu layer.
• the thickness H2 of the Ta film is very thin, the adhesion to the underlying copper wiring layer 2 is good, and the electrical resistance of this portion can be suppressed to a small level.
• the communication hole 8 is formed in a part of the recess 5, that is, the recess 5 formed in a so-called two-stage step is described.
• the present invention is not limited to this mode.
• the present invention can also be applied to a so-called one-step concave portion in which the concave portion 5 itself is a through hole 8 of a through hole or a via hole.
• each numerical value in each of the above embodiments is merely an example, and it is needless to say that the numerical value is not limited thereto.
• the laminated structure of the NORA film Z seed film as a whole and the laminated structure of TaN / Ta / Cu, TaZTaZCu are described, but the laminated structure is not limited to this kind.
• the method of the present invention can be applied to a TiNZTiZCu laminated structure, a TaNZRuZCu laminated structure, a TiZCu laminated structure, and a TiN / Ti / Ru, Ti ZRu, TaN / Ru, and TaNZTaZRu laminated structure. is there.
• each high-frequency power supply is not limited to 13.56 MHz, but may be other frequencies such as 27. OMHz.
• the inert gas is not limited to Ar gas, and other inert gas such as He or Ne may be used.
• the present invention is not limited to this, and the present invention can be applied to an LCD substrate, a glass substrate, a ceramic substrate, and the like.

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