WO2008016004A1 - Procédé et appareil de formation de film, programme informatique et support de stockage - Google Patents

Procédé et appareil de formation de film, programme informatique et support de stockage Download PDF

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Publication number
WO2008016004A1
WO2008016004A1 PCT/JP2007/064891 JP2007064891W WO2008016004A1 WO 2008016004 A1 WO2008016004 A1 WO 2008016004A1 JP 2007064891 W JP2007064891 W JP 2007064891W WO 2008016004 A1 WO2008016004 A1 WO 2008016004A1
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Prior art keywords
film
metal
recess
processed
film forming
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PCT/JP2007/064891
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English (en)
Japanese (ja)
Inventor
Taro Ikeda
Yasushi Mizusawa
Takashi Sakuma
Osamu Yokoyama
Tatsuo Hatano
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Tokyo Electron Limited
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Publication of WO2008016004A1 publication Critical patent/WO2008016004A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/021—Cleaning or etching treatments
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C23C14/025—Metallic sublayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Definitions

  • the present invention relates to a film forming method, a film forming apparatus, a computer program, and a memory for effectively forming a thin film such as a metal film on the surface of a recess formed on the surface of an object to be processed such as a semiconductor wafer. It relates to the medium.
  • a semiconductor device In order to manufacture a semiconductor device, a semiconductor device is repeatedly subjected to various processes such as a film forming process and a pattern etching process to manufacture a desired device. Line widths and hole diameters are becoming increasingly finer due to the demand for higher miniaturization.
  • wiring materials and embedding materials there is a tendency to use copper, which has a very low electric resistance and is inexpensive, because it is necessary to reduce the electric resistance by miniaturizing various dimensions (Japanese Patent Laid-Open No. 2000-77365). Publication).
  • the tantalum metal (Ta) or tantalum nitride (TaN) isostatic S barrier layer is generally considered in consideration of adhesion to the lower layer. Used as
  • NOR layer In order to form this NOR layer, a tantalum nitride film (hereinafter also referred to as “TaN film”) or a tantalum film (hereinafter referred to as “Ta film”) is used as a base layer on the wafer surface in a plasma sputtering apparatus.
  • a barrier layer is formed by forming a tantalum film (changing film forming conditions when the underlayer is a Ta film) in the same plasma sputtering apparatus.
  • a thin seed film made of a copper film is formed on the surface of this NOR layer, and then the entire surface of the wafer is subjected to a copper plating process so as to fill the recess.
  • the insulating layer is formed on the lower wiring layer and then the insulating layer is formed.
  • a communication hole such as a via hole or a through hole is formed in the layer so that the lower wiring layer is exposed at the bottom of the communication hole, and then the communication hole is embedded with the material of the upper wiring layer and at the same time, the upper wiring layer It is designed to deposit.
  • the line width and hole diameter are further reduced due to the demand for miniaturization.
  • the connection structure between the lower wiring layers has also been devised to lower its electrical resistance.
  • the bottom of the communication hole is shaved to a predetermined depth in the thickness direction of the lower wiring layer so that the contact resistance between the embedding material for embedding the communication hole and the lower wiring layer is made smaller.
  • Structure is adopted. Such a structure is called a so-called punch-through structure, and this production method is called a so-called punch-through process.
  • the present invention has been devised to pay attention to the above problems and to effectively solve them.
  • the object of the present invention is to appropriately treat the process conditions during film formation such as the seed layer and the seed layer so that only the bottom of the bottom layer of the recess is selectively scraped and the surface to be processed includes the surface in the recess.
  • a thin film can be formed on the entire surface of the body, and the bottom can be scraped off to the same depth without depending on the width of the recess to form a recess with the same depth.
  • the present inventors When forming a metal film by plasma sputtering, the present inventors have appropriately adjusted process conditions such as bias voltage, direct current power to the metal target, and plasma power to neutral atoms of metal particles.
  • the present invention has been achieved by obtaining the knowledge that a metal film can be formed over the entire surface of the wafer including the surface of the semiconductor wafer by controlling the ratio of the metal particle ions to the metal wafer.
  • the inventors of the present invention can increase the number of neutral atoms of metal particles compared to ions during plasma sputtering processing, particularly by setting the process pressure larger than that in the conventional processing, thereby flattening the wafer surface.
  • Cu neutral atoms predominate on the surface and side walls, and a Cu film can be actively deposited, while metal ions and gas ions that are drawn deeply by bias power become dominant at the bottom of the deep recess. The bottom can be further scraped off.
  • the present invention includes a step of placing an object to be processed having a recess formed on a surface of a mounting table provided in a processing vessel that can be evacuated, and an inert gas in the processing vessel.
  • the metal target is ionized by the plasma formed by plasma generation to generate metal particles containing metal ions, and the metal particles are drawn into the target object mounted on the mounting table in the processing container by bias power.
  • forming a thin film containing the metal on the surface of the object to be processed, and the step of forming a thin film on the surface of the object to be processed is formed by shaving the bottom of the recess of the object to be processed.
  • the present invention by appropriately selecting the process conditions at the time of film formation of the barrier layer, the auxiliary seed film, etc., only the bottom of the bottom layer of the recess is selectively scraped, and the surface in the recess is removed.
  • a thin film can be formed over the entire surface of the object to be processed. It is possible to cut the bottom part by the same depth without depending on the force and the width of the concave part to form a cut-in hollow part of the same depth, and further increase the electrical resistance at the bottom of the cut-out hollow part.
  • a thin film can be formed on the side surface and the upper surface of the recess while removing the Ta ′ Cu mixed layer.
  • the present invention is a film forming method characterized in that after the auxiliary seed film forming step, a main seed film forming step of forming a main seed film for plating is performed.
  • the present invention is a film forming method, wherein a plating step of applying plating with the second metal is performed after the seed film forming step.
  • the barrier layer forming step includes a base film forming step of forming a base film made of the first metal nitride film on the entire surface of the object to be processed including the surface in the recess.
  • a film forming method comprising: forming a main nano film made of the first metal alone on at least a side wall in the recess while forming the cut recess. is there.
  • the first metal is made of Ta and the second metal is made of Cu. This is a characteristic film forming method.
  • the barrier layer forming step includes forming a base film made of the first metal nitride film on the entire surface of the object to be processed including the surface in the recess, and A main barrier film forming step of forming a main nora film made of the first metal alone on at least a side wall in the recess while forming the cut-in depression, and an auxiliary barrier film containing a third metal And an auxiliary barrier film forming step for forming the film.
  • the present invention is a film forming method characterized in that after the auxiliary barrier film forming step, a plating process for applying a plating with the second metal is performed.
  • the present invention is the film forming method, wherein the first metal is made of Ta, the second metal is made of Cu, and the third metal is made of Ru.
  • the present invention is the film forming method, wherein the auxiliary seed film forming step is performed by setting the pressure in the processing container within a range of 30 to 90 mTorr.
  • the present invention is the film forming method, wherein the auxiliary seed film forming step is performed by setting the bias power within a range of 100 to 250 watts.
  • the present invention is the film forming method, wherein the auxiliary seed film forming step is performed by setting an electric power for forming the plasma in a range of 0.5 to 2 kilowatts.
  • the present invention provides a film forming method, wherein the concave portion of the object to be processed has a communication hole to be a via hole or a through hole, and is formed in a two-step step shape! is there.
  • the present invention is the film forming method, wherein the concave portion includes a communication hole that becomes a via hole or a through hole.
  • the present invention provides a processing container that can be evacuated, a mounting table for mounting a target object having a recess formed on a surface thereof, and a predetermined container containing at least an inert gas in the processing container.
  • a gas introduction means for introducing a gas; a plasma generation source for generating plasma power and generating a plasma of an inert gas in the processing vessel; and a DC power source applied to the processing vessel.
  • a metal target to be ionized by the plasma a bias power source that supplies a predetermined bias power to the mounting table, a gas introduction unit, a plasma generation source, and a device control unit that controls the bias power source
  • the apparatus controller further comprises a thin film containing a second metal on the surface of the object to be processed including the surface in the recess by further scraping the bottom of the cut-in recess in the recess.
  • the film forming apparatus is characterized in that the gas introducing means, the plasma generation source, and the noise power source are controlled so as to form an auxiliary seed film for use.
  • the film forming method includes: a mounting table provided in a processing container that is evacuated; A step of placing the object to be processed and a plasma formed by converting the inert gas into a plasma in the processing container to ionize a metal target to generate metal particles containing metal ions, Forming a thin film containing the metal on the surface of the object to be processed by drawing the particles into the object to be processed placed on the mounting table in the processing container by bias power, and the surface of the object to be processed
  • an auxiliary seed film for plating containing a second metal is formed on the surface of the object to be processed including the surface in the recess by further cutting the etched recess in the bottom in the recess.
  • the present invention provides a storage medium storing a computer program for causing a computer to execute a film forming method.
  • the film forming method is performed on a surface of a mounting table provided in a processing container that can be evacuated.
  • a metal target containing ions is generated by ionizing a metal target using a plasma formed by plasma forming an inactive gas in the processing container, and placing the object to be processed with recesses on the substrate. And drawing the metal particles into a target object placed on a mounting table in the processing container by bias power to form a thin film containing the metal on the surface of the target object.
  • the step of forming a thin film on the surface of the processing object further comprises a step of further cutting away the cut-in recess at the bottom of the recess to supplement the plating for the metal containing the second metal on the surface of the object to be processed including the surface in the recess.
  • a storage medium characterized by having an auxiliary seed film formation step of forming a seed film.
  • a thin film can be formed over the entire surface. It is possible to cut the bottom part by the same depth without depending on the width of the concave part, and to form a hollow part having the same depth, and further increase the electrical resistance at the bottom part of the hollow part. For example, a thin film can be formed on the side surface and top surface of the recess while removing the Ta′Cu mixed layer.
  • FIG. 1 is a cross-sectional view showing an example of a film forming apparatus according to the present invention.
  • FIG. 2 is a graph showing the angle dependency of the patch etching.
  • FIG. 3 is a graph showing the relationship between the bias power and the amount of film formation on the upper surface of the wafer.
  • FIGS. 4 (A) to (H) are flowcharts for explaining a first embodiment of the method of the present invention.
  • FIG. 5 is a partially enlarged view showing the bottom of the communication hole (the bottom of the cut-in recess) when the main barrier film is formed.
  • FIG. 6 is a graph showing the relationship between the aspect ratio of the recess and the copper etching rate at the bottom.
  • FIGS. 7A and 7B are diagrams schematically showing the trend of Cu metal particles when the process pressure is low and when the process pressure is high.
  • FIGS. 8A to 8D are graphs showing the deposition rate of the Cu film when the plasma power and the bias power are variously changed.
  • FIGS. 9A and 9B are diagrams showing a part of the steps of the second embodiment of the method of the present invention.
  • FIGS. 10 (A) to 10 (C) are process diagrams showing a part of a modification of the method for forming a NOR layer including a TaN film.
  • FIGS. 11 (A) to 11 (C) are views showing a state before the communication holes formed on the semiconductor wafer are embedded.
  • FIGS. 12 (A)-(E) are diagrams showing a process of filling a communication hole.
  • FIGS. 13A and 13B are views showing embodiments of recesses (trench) having various widths.
  • FIG. 11 embeds the communication holes formed on the semiconductor wafer.
  • 11 (A) is a plan view
  • FIG. 11 (B) is a cross-sectional view taken along line A—A in FIG. 11 (A)
  • FIG. 11 (C) is a perspective view. Each is shown.
  • FIG. 12 is a diagram showing the process of embedding the communication holes.
  • the semiconductor wafer W is made of, for example, a silicon substrate, and a lower wiring layer 2 made of, for example, copper and an insulating layer 4 made of a silicon oxide film or the like are sequentially laminated on the surface of the silicon substrate.
  • a recess 5 is formed on the surface of the insulating layer 4.
  • a wiring groove having a predetermined width for forming an upper wiring layer, that is, a trench 6 is formed, and the insulating layer 4 is partially penetrated at the bottom of the trench 6.
  • a via hole or a through hole 8 is formed to communicate with the lower wiring layer 2!
  • the diameter L1 of the communication hole 8 is very small, for example, about 60 to 200 nm, and the width L2 of the concave portion 5, that is, the trench 6 is, for example, about 60 to 1000 nm.
  • a barrier layer 10 made of a metal film is formed by, for example, plasma sputtering for the purpose of improving adhesion to the base layer, preventing diffusion of copper into the insulating layer 4 and preventing migration.
  • the barrier layer 10 mainly employs, for example, a two-layer structure of a tantalum nitride film (TaN film) and a tantalum film (Ta film), or a two-layer structure of tantalum films formed with different film formation conditions. Is done.
  • plasma etching using Ar gas as an inert gas is performed to scrape off the noble layer 10 formed on the bottom of the communication hole 8, and then Etching is performed on the lower wiring layer 2 as a base, and a concavity 12 having a predetermined depth is formed therein.
  • the seed layer 14 for electroplating is extremely applied to the entire surface including the above-described etched recess 12, the communication hole 8, and the inner surface of the trench 6. Form thinly.
  • the seed layer 14 for example, a copper (Cu) film is used because copper plating is performed in a later step.
  • the upper wiring layer 16 electrically connected to the lower wiring layer 2 is formed by scraping off unnecessary metal material on the upper surface by polishing or the like.
  • the shape force of the recess 5 having a communication hole 8 such as a through hole or a via hole at the bottom of the trench 6 and the cross section of which is a stepped shape in two stages so-called dual damascene (Dual Damascene) ) Called structure.
  • FIG. 13 is a diagram showing the form of the recesses 5 (trench 6) having different widths L2.
  • the surface of the force semiconductor wafer W actually has a width L2 as shown in FIG.
  • the aspect ratio of the communication hole 8 this diameter L1 is the same
  • the aspect ratio of the trench 6 is different, the upper side from the bottom of the communication hole 8
  • the thicknesses Hl and H2 of the barrier layer 10 deposited on the bottom of the communication hole 8 which is the bottom layer of the recess are different. End up.
  • the barrier layer is scraped off, resulting in variations in the depth of the cut recess 12 formed at the bottom. There was a problem.
  • FIG. 1 is a cross-sectional view showing an example of a film forming apparatus according to the present invention.
  • an ICP (Inductively Coupled Plasma) type plasma sputtering apparatus will be described as an example of the film forming apparatus.
  • the film forming apparatus 32 includes a processing container 34 formed into a cylindrical shape with, for example, aluminum.
  • the processing vessel 34 is grounded, and an exhaust port 38 is provided at the bottom 36, and can be evacuated by a vacuum pump 42 through a throttle valve 40.
  • a disk-shaped mounting table 44 made of, for example, aluminum is provided, and an electrostatic chuck 46 is installed on the upper surface of the mounting table 44.
  • the semiconductor wafer W as the object to be processed can be adsorbed and held on the substrate.
  • a DC voltage for suction (not shown) is applied to the electrostatic chuck 46 as necessary.
  • the mounting table 44 is supported by a support column 48 extending downward from the center of the lower surface, and the lower portion of the support column 48 penetrates the container bottom 36.
  • the column 48 can be moved up and down by an elevator mechanism (not shown), and the table 44 itself can be moved up and down.
  • a bellows-shaped metal bellows 50 is provided so as to be stretchable so as to surround the support column 48, and the upper end of the metal bellows 50 is airtightly joined to the lower surface of the mounting table 44, Further, the lower end is airtightly joined to the upper surface of the bottom portion 36, and the up / down movement of the mounting table 44 can be allowed while maintaining the airtightness in the processing vessel 34.
  • the mounting table 44 is formed with a refrigerant circulation path 52 through which a refrigerant for cooling the wafer W flows. This refrigerant is not shown in the support column 48! /, And is supplied / discharged through the flow path! /, The
  • three support pins 54 are provided upright on the container bottom 36 so as to correspond to the support pins 54.
  • a pin insertion hole 56 is formed in the mounting table 44 described above. Therefore, when the mounting table 44 is lowered, the wafer W is received by the upper end portion of the support pin 54 penetrating the pin through hole 56 and is received. The wafer W from the outside is not shown! /, And can be transferred to and from the transfer arm. Therefore, a gate valve 58 that can be opened and closed is provided on the lower side wall of the processing vessel 34 to allow the transfer arm to enter.
  • the electrostatic chuck 46 provided on the mounting table 44 is connected to, for example, 13.
  • a bias power source 62 composed of a high frequency power source that generates a 56 MHz high frequency is connected, and a predetermined bias power can be applied to the mounting table 44 described above.
  • the bias power supply 62 can control the output bias power as required.
  • a transmission plate 64 that is permeable to high frequencies made of a dielectric material such as aluminum nitride is hermetically sealed through a seal member 66 such as an O-ring.
  • a plasma generation source 70 is provided in the processing space 68 in the processing vessel 34 for generating plasma by, for example, converting Ar gas as plasma gas into plasma.
  • Ar gas As this plasma gas, another inert gas such as He or Ne may be used instead of Ar.
  • the plasma generation source 70 has an induction coil portion 72 provided in correspondence with the transmission plate 64.
  • the induction coil portion 72 has a high frequency of 13.56 MHz for generating plasma, for example.
  • a power source 74 is connected so that a high frequency can be introduced into the processing space 68 through the transmission plate 64.
  • the plasma power output from the high-frequency power source 74 can be controlled as necessary.
  • a baffle plate 76 made of, for example, aluminum is provided immediately below the transmission plate 64 to diffuse the introduced high frequency.
  • a metal target 78 is provided so as to surround the upper side of the processing space 68.
  • the cross section is inclined inward to form an annular shape (a frustoconical shell shape).
  • a variable DC power supply 80 is connected to the metal target 78.
  • the DC power output from the variable DC power supply 80 can also be controlled as necessary.
  • the metal target 78 for example, tantalum metal is used when forming a Ta film or TaN film, and copper is used when forming a Cu film.
  • a cylindrical protective cover 82 made of, for example, aluminum is provided below the metal target 78 so as to surround the processing space 68. Is bent inward and is located near the side of the mounting table 44 described above.
  • a gas introduction port 84 is provided as a gas introduction means for introducing a predetermined gas required into the processing vessel 34.
  • the gas inlet 84 is supplied as a plasma gas through a gas control unit 86 including, for example, an Ar gas and other necessary gases such as N2 gas, a 1S gas flow controller, a valve, and the like.
  • each component of the film forming apparatus 32 is connected to and controlled by an apparatus control unit 88 formed of, for example, a computer.
  • the device control unit 88 controls the operations of the noise power source 62, the high-frequency power source 74 for plasma generation, the variable DC power source 80, the gas control unit 86, the slot valve 40, the vacuum pump 42, etc.
  • the device control unit 88 controls the operations of the noise power source 62, the high-frequency power source 74 for plasma generation, the variable DC power source 80, the gas control unit 86, the slot valve 40, the vacuum pump 42, etc.
  • Ar gas is allowed to flow while operating the gas control unit 86 into the processing vessel 34 that has been evacuated by operating the vacuum pump 42, and the throttle valve 40 is controlled to control the processing vessel.
  • the inside of 34 is maintained at a predetermined degree of vacuum.
  • direct current power is applied to the metal target 78 via the variable direct current power source 80, and further high frequency power (plasma power) is applied to the induction coil unit 72 via the high frequency power source 74.
  • the device control unit 88 also issues a command to the bias power source 62 and applies a predetermined bias power to the mounting table 44.
  • argon plasma is generated by the power applied to the metal target 78 and the induction coil unit 72 to generate argon ions, and these ions collide with the metal target 78.
  • the metal target 78 is sputtered to release metal particles.
  • metal atoms and metal atomic groups that are metal particles from the sputtered metal target 78 are ionized when passing through the plasma.
  • the metal particles are scattered in a downward state in a state where ionized metal ions and electrically neutral metal atoms are mixed.
  • metal ions are attracted by the bias power applied to the mounting table 44, and have high directivity with respect to the wafer W, and are deposited on the wafer W on the mounting table 44 as metal ions.
  • the apparatus control unit 88 can attract Ar ions in the plasma toward the mounting table 44 by giving a command to output a large output to the bias power source 62, for example. It is achieved that both sputter etchings occur simultaneously.
  • the control of each component of the apparatus is controlled by the apparatus control unit 88 based on a program created so that the metal film is formed under a predetermined condition.
  • a program including instructions for controlling each component is stored in a storage medium 90 such as a floppy disk (FD), a compact disk (CD), a flash memory, and the like, and a predetermined program based on this program is stored.
  • FD floppy disk
  • CD compact disk
  • flash memory a predetermined program based on this program is stored.
  • Fig. 2 is a graph showing the angle dependence of sputter etching
  • Fig. 3 is a graph showing the relationship between the bias power and the amount of film formed on the upper surface of the wafer
  • Fig. 4 is a flowchart for explaining the first embodiment of the method of the present invention.
  • the first feature of the method of the present invention is that, in a specific step in a series of film formation processes, when a thin film such as a metal film is formed by sputtering film formation by plasma, bias power, direct current It is to control the power, plasma power, etc. to an appropriate magnitude.
  • film formation by drawing into metal ions and sputter etching with plasma gas (Ar ions) occur simultaneously, and the bottom of the bottom of the recess is set to a state where it is scraped off and formed on the semiconductor wafer. It is possible to deposit a metal film on the surface while forming a hollow portion by scraping the bottom portion of the lowermost layer of the recessed portion.
  • the bias power at this time is determined by the film formation rate by drawing metal ions and the sputter etching etching rate by plasma gas (Ar + ) on the surface facing the metal target 78, that is, the upper surface of the wafer in FIG. Is set to a size that approximately balances
  • the second feature of the present invention is that when forming a metal film by plasma sputter deposition, the pressure in the processing vessel (process pressure) is set to be considerably higher than in the conventional method.
  • the amount of neutral metal atoms generated in the metal particles is larger than the amount of metal generated, and as a result, the neutral metal atoms predominate on the wafer surface and side wall portions, and the metal film is actively deposited. It is.
  • metal ions and gas ions drawn to the back by the bias power become dominant, and the Ta ′ Cu mixed layer at the bottom, for example, is further scraped off.
  • the angle of the sputtered surface refers to the angle formed by the normal of the sputtered surface and the incident direction (downward direction in FIG. 1) of the sputtering gas (Ar ion: Ar + ). 12) are both "0 degree” and the side walls of the recess are "90 degree".
  • the relationship between the bias power applied to the wafer W side and the film forming amount deposited on the upper surface of the wafer (not the side wall of the recess). Is as shown in Fig. 3. That is, in a situation where a constant plasma power and a constant DC power to the metal target 78 are applied, if the bias power is not so high, a high film formation amount is caused by metal ion attraction and neutral metal atoms. As the obtained power and bias power increase, the wafer surface gradually becomes more prone to be sputtered by argon ions, which are plasma gases accelerated by the bias power (see Fig. 2). The film is etched.
  • a condition generally operated in this type of sputtering apparatus is the region A1, and a high film formation amount (film formation rate) can be obtained without increasing the noise power. It was an area that could be done.
  • the amount of film formation is the region where the metal ions are almost the same as when the bias is zero (etching by inert gas plasma does not occur) and the maximum amount of metal ions to be drawn. This is a region where the film formation amount can be earned.
  • it is performed mainly in a region where film formation by attracted metal ions and neutral metal atoms and sputter etching by plasma gas occur simultaneously.
  • the etching is performed in the region A2 on the upper surface of the wafer where the film formation rate by the drawn metal ions and neutral metal atoms and the etching rate of the sputter etching by the plasma gas are substantially balanced.
  • the “approximately balanced” is not limited to the case where the film formation amount on the upper surface of the wafer is “zero”, but is formed with a slight film thickness of about 3/10 compared with the film formation amount in the area A1. This includes cases where film thickness is generated.
  • the wafer W is loaded into the processing chamber 34 that can be evacuated through the gate valve 58 of the processing chamber 34, and the wafer W is placed on the support pins 54. To support.
  • the mounting table 44 is raised in this state, the wafer W is transferred to the upper surface, and the wafer W is adsorbed to the upper surface of the mounting table 44 by the electrostatic chuck 46.
  • a recess 5 (see FIG. 4A) having the same structure as that described with reference to FIG. That is, the insulating layer 4 is formed on the lower wiring layer 2 made of Cu, and the recess 5 is formed in the insulating layer 4.
  • the recess 5 is formed of a groove-like trench 6 (see FIG. 11 (A)), and a communication hole 8 such as a via hole or a through hole is formed at the bottom so as to reach the wiring layer 2. It is made into a stepped shape! /
  • tantalum is used as the first metal as the metal target 78, and after the inside of the processing vessel 34 is evacuated to a predetermined pressure, an induction coinor of the plasma generation source 70 is used.
  • Plasma power is applied to the unit 72, and a predetermined bias power is applied to the electrostatic chuck 46 of the mounting table 44 from the bias power source 62.
  • a predetermined direct current power is applied to the metal target 78 from the variable direct current power source 80 to perform film formation.
  • a base film forming step for forming the base film 10A is performed as a part of the NOR layer forming process.
  • a TaN film that is, a first metal nitride film as the base film 10A
  • Ar gas which is a plasma gas from the gas inlet 84, for example, N2 gas is used as a nitriding gas in the processing vessel 34.
  • N2 gas is used as a nitriding gas in the processing vessel 34.
  • a TaN film is formed as a base film 10A substantially uniformly not only on the top surface of the wafer W but also on the side walls and bottom surface in the recess 5.
  • the noise power at this time is the area A1 in FIG. 3, which is the same as the conventional general film formation conditions, and is specifically about 100 W (watts).
  • a main barrier film forming step is then performed to form a Ta film as the main barrier film 10B made of the first metal alone.
  • the NOR layer 10 is formed. That is, in this main nano film formation step, the bias power is increased and set in the region A2 in FIG.
  • the main nano film forming step is such that the film deposition amount by the metal particles and the etching amount by the plasma of the inert gas are substantially the same on the surface of the wafer W other than the recess 5.
  • the conditions are set so that the amount of film formation by the metal particles on the surface of the wafer W other than the recess 5 is slightly larger than the etching amount by the plasma of the inert gas.
  • the second step may be used, or the second step may be used alone.
  • the bias power is set to point XI in FIG. 3 in order to set the film formation amount on the wafer upper surface to “zero” in the first step.
  • the bias power at this time is specifically 350 W.
  • the supply of N2 gas is stopped and only Ar gas is supplied from the gas inlet 84.
  • the bottom of the lowermost layer (corresponding to the communication hole 8) of the recess 5 is scraped off, so that the upper surface side of the wiring layer 2 made of Cu is scraped, and a shaved recess 12 is formed here.
  • the magnitude of the bias power is set to the area A2 in FIG. 3, more specifically, to the point XI.
  • the film formation rate by the metal ions and neutral metal atoms drawn on the upper surface of the wafer and the etching rate of the sputter etching by the plasma gas (Ar + ) are substantially balanced, resulting in the formation of the metal film.
  • the etching rate is larger than the film formation rate at the bottom of the communication hole 8 of the recess 5 while the amount is substantially zero.
  • the bottom of the communication hole 8 is cut away. Will go.
  • the above items can be expressed at the atomic level for the wafer unit area as follows.
  • Ta represents a neutral metal atom
  • Ta + represents a metal ion
  • Ar + is an Ar ion and contributes to etching. Therefore, Ta and Ta + reach sufficiently on the upper surface of the wafer, and Ar + also reaches sufficiently, resulting in a film formation amount of “zero”.
  • Ta + and Ar + with high directivity reach Ta, which is a neutral metal atom with poor directivity, reaches. It is difficult to do. As a result, the bottom of the communication hole 8 is scraped off as much as Ta that contributes to the film formation does not reach. The amount of scraping at this time is controlled by controlling the processing time of the first step. For the sake of simplicity, it is assumed here that one Ta and Ta + film is projected (etched) from the surface formed by Ar + 1 collision. Yes.
  • the process proceeds to the second step.
  • the bias power is set to a point other than point XI in area A2, such as A3, and the metal thickness is much less than the film deposition rate in area A1.
  • a film is formed.
  • a Ta film is formed as the main nore film 10 on the entire wafer surface excluding the bottom of the communication hole 8, that is, on the surface in the recess 5 and the side surface of the communication hole 8.
  • the bottom of the communication hole 8 has a higher etching rate than the film formation rate for the reason described above, and therefore the Ta film is further scraped away without adhering. For this reason, the X The shape is even larger.
  • the amount of metal particles contributing to the film formation is set to be larger than the sputter ions so that the film is slightly deposited.
  • the base film in FIG. 4 (B) is obtained even after the process of FIG. 4 (C) is completed.
  • the thickness of 10A does not change. Therefore, the base film 10A can have a thickness of, for example, 3.5 nm on the wafer surface and 1. Onm at the bottom of the communication hole 8 regardless of the depth of the hole in the recess IJ recess 12. LOnm or less, more preferably 5 nm or less.
  • the thickness of the barrier layer 10 in FIG. 12A varies depending on the depth of the hole in the cut-in recess, and when the depth is about 50 nm, About 60nm is required. This is because the wafer surface is simultaneously etched by the Ar etching process shown in FIG. Furthermore, when a 60 nm undercoat film is formed on the wafer surface! /, The bottom of the communication hole! /, The force of about 10 nm to 20 nm, the thickness! /, The formation of a barrier layer is avoided. This indicates that, in the initial stage of the etching process (Fig. 12 (B)), the etched recess is not formed and only the NOR layer is etched.
  • the conditions are set so that the film formation amount on the wafer surface becomes substantially zero through the first and second steps, and as described in FIG. Accumulated protrusions 18 do not occur. Further, the depth of the etched recess 12 formed here is substantially uniform in the wafer plane regardless of the width L2 of the recess (see FIG. 13) since the base film at the bottom of the communication hole is extremely thin. I can do it.
  • FIG. 5 is a partially enlarged view showing the bottom of the communication hole (the bottom of the cut-out recess 12) when the main barrier film is formed (see FIG. 4 (D)) and adheres to the side wall of the communication hole 5.
  • Main barrier film (Ta film) 10B thickness H 1 is a force that makes the film thicker. Even at the bottom part, a slight force H and a main force film 10B are attached. This thickness H2 is, for example, about lnm.
  • Ta + ions are attracted by the bias power in the vicinity of the bottom, so Ta + ions are implanted into the Cu wiring layer 2 and this is the cause of the increase in electrical resistance.
  • the Ta 'Cu mixed layer 100 is formed.
  • the connection electrical resistance at this portion increases.
  • the Ta film is very slightly formed on the wafer surface, the recess 5, the side wall of the communication hole 8, or the like. Since this deposits and forms a TaN / Ta barrier film, only one of the first and second steps may be performed. Even in this case, the problem of electric resistance due to the Ta ′ Cu mixed layer 100 and the Ta film of thickness H2 arises.
  • the Ta film or Ta′Cu mixed film having the above-mentioned thickness H2 is formed in the subsequent auxiliary seed film forming step.
  • the process proceeds to the auxiliary seed film forming process, which is a feature of the present invention.
  • this wafer W is loaded into a film forming apparatus having the same structure as that shown in FIG. 1 in which the metal target 78 is formed of copper instead of tantalum, and the above-described cutting is performed as shown in FIG. 4 (E). Further, the bottom portion of the recess 12 is further cut to form an auxiliary seed film 14A for plating made of a thin film containing the second metal on the wafer surface including the surfaces in the recess 5 and the communication hole 8.
  • Cu is used as the second metal
  • the auxiliary seed film 14A is made of a Cu film.
  • the process conditions are set so that the force and the corner 102 of the step in the recess 5 are not adversely affected.
  • the process pressure is set to, for example, about 5 mTorr. Set it fairly high, for example within the range of 30 to 90 mTorr.
  • the bias power is set within a range of 100 to 250 watts (0.32 W / cm 2 to 0.8 W / cm 2 ), for example.
  • the power for forming plasma in the plasma generation source 70 that is, the power of the high-frequency power source 74 is set within a range of 0.5 to 2 kilowatts.
  • the concentration of plasma is increased, and the amount of neutral metal atoms of copper, which is a factor mainly for film formation, on the upper surface side of the wafer is increased. More than the total ion of Cu + ions and Ar + ions that cause etching, the neutral metal atoms become dominant, and in the deep part of the communicating hole 8, the neutral metal atoms of copper The amount of Cu + ions and Ar + ions that are attracted by the bias power is increased more than the neutral metal atoms so that these ions become dominant.
  • the auxiliary seed film 14A made of a Cu film can be deposited thinly on the other surface while further shaving the bottom of the shaving depression 12 downward.
  • the bottom portion of the engraved depression 12 is further scraped off, so that the Ta′Cu mixed layer 100 located here can be scraped off and removed.
  • the region A2 in FIG. 3 is used for such an auxiliary seed film forming step except that the process pressure is different.
  • the adhesion force between Cu and Cu + ions is lower than that of Ta, Cu + ions act on the deposited Cu film as an etching factor in the A2 region of bias power (see Fig. 3). .
  • the process then proceeds to the present seed film formation step, in which the plasma power is set in region A1 in FIG.
  • the seed layer 14B made of copper is formed not only on the top surface of the wafer but also on the side wall and bottom of the recess 5 to make it thin.
  • the seed layer 14 having a laminated structure of the auxiliary seed film 14A and the present seed film 14B is formed.
  • the film forming apparatus on which the copper metal target as described above is mounted has the above tantalum gold.
  • a semiconductor wafer that can be connected to a film forming apparatus equipped with a metal target via a transfer chamber that can be evacuated can be transferred between both film forming apparatuses in a vacuum atmosphere without being exposed to the atmosphere. Can do.
  • the wafer W is taken out of the film forming apparatus and subjected to a normal plating process to perform a plating process, as shown in FIG. 4 (G). 5 is completely filled with the material of the wiring layer 16 made of copper.
  • only the bottom part of the lowermost layer of the recess 5 is selectively selected by properly selecting the process conditions at the time of film formation of the NOR layer 10 and the auxiliary seed film 14A.
  • a thin film can be formed over the entire surface of the wafer including the surface in the recess 5 while removing.
  • a thin film can be formed on the side surface and upper surface of the recess 5 while removing the Ta ′ Cu mixed layer 100.
  • the setting conditions of the above-mentioned nora layer forming step that is, the setting conditions that can realize the area A2 in FIG. 3 are as follows.
  • Plasma power 500 ⁇ 6000W
  • the operating point is set in the region A2 by appropriately selecting the above three conditions. In this case, if the operating point is set in a portion other than the region A2, the soaked IJ recess 12 is not sufficiently formed, so that a so-called punch-through structure cannot be formed.
  • the flow rate of Ar gas is in the range of about 50 to 1000 sccm, and the process pressure is in the range of about 0.001 Torr (0. lPa) to 0.1 torr (13.3 Pa).
  • the TaN film is formed as the base film 1 OA has been described as an example, but instead, the Ta film may be formed as the base film 10A.
  • the Ta film 10B is formed on the Ta film serving as the base film 10A, the barrier layer 10 is formed in a two-layer structure of Ta films having different film formation conditions.
  • FIG. 6 is a graph showing the relationship between the aspect ratio of the recess and the copper etching rate at the bottom.
  • the concave portion was not formed in a two-step shape but was formed as a single-step concave portion.
  • characteristic A shows the case of the conventional method
  • characteristic B shows the case of the method of the present invention.
  • a barrier layer of approximately 60 nm was plasma sputtered on the wafer surface for the recesses having various aspect ratios, and then Ar etching was performed for a predetermined time. The depth of the cut recess formed at this time was measured and used as the copper etching rate.
  • a base film of about 4 nm was plasma sputtered on the wafer surface with respect to the recesses having various aspect ratios, and then the first step was performed for the same predetermined time as the conventional method. Further, the depth of the cut recess formed at this time was measured to obtain the copper etching rate.
  • the aspect ratio is often 2 or more. According to the above, it was confirmed that the depth of the ridge ij recessed portion 12 related to the aspect ratio can be made substantially uniform, and good results can be obtained. Thus, since the depth of the ridge IJ recess 12 is not affected by the shape of the recess 5, it is possible to always form a recess with the same depth without depending on the width of the recess. it can.
  • the bottom portion of shore IJ recess 12 is further scraped downward to form Ta ′ Cu mixed layer 100.
  • a force to deposit a little metal film on the other wafer surface during removal In this case, the seed film 14B made of Cu film (see Fig. 4 (F)) is attached in the next process.
  • Cu which is the same material as the seed film 14B, is used as the metal target, and as a result, the auxiliary seed film 14A made of the Cu film is deposited.
  • the process pressure is set low as described above, the average number of atoms As the free process becomes larger, the number of collisions with the wafer surface increases and the damage increases. Therefore, the process pressure is increased to some extent, specifically, in the present invention, the process pressure is set within a range of 30 to 90 mTorr, and the metal film is formed while suppressing damage of the wafer surface due to ions. At the same time, the bottom of the dent 12 is shaved deeper.
  • FIG. 7 shows a part of the situation at this time, and is a diagram schematically showing the trend of Cu metal particles when the process pressure is low and high.
  • a high frequency as shown in Fig. 1 is applied to the recess.
  • Fig. 7 (A) shows a case where the process pressure is low, for example, 5mTorr (conventional method), and
  • Fig. 7 (B) shows a high process pressure. In this case, for example, indicate 50 mTorr (invention method)!
  • Fig. 8 shows the results of this evaluation and is a graph showing the Cu film deposition rate when the plasma power and bias power are variously changed.
  • the process pressure was kept constant at 50 mTorr and the DC power supplied to the metal target was maintained at 3.2 kW.
  • the bias power was changed in the range of 0 to 200 watts [W].
  • Fig. 8 (A) shows 4kW
  • Fig. 8 (B) shows 3kW
  • Fig. 8 (C) shows 2kW
  • Fig. 8 (D) shows lkW.
  • the deposition rate is "0" when the bias power is 100W or more. Can not do it.
  • the plasma power is 0.5 kW.
  • the plasma power is preferably set within the range of 0.5 to 2 kW.
  • the bias power preferred in the 250 W range is less than 100 W, the ion attraction becomes too weak to further scrape the bottom of the concavity 12, and the bias power If it is larger than 250 W, the damage to the wafer surface or the like becomes excessively large, and the amount of Cu film formation becomes too small.
  • FIG. 9 is a diagram showing a part of the steps of the second embodiment of the method of the present invention.
  • the step of forming the main noor film 10B made of the Ta film shown in FIG. 4D and the auxiliary seed film 14A shown in FIG. 9A an auxiliary barrier film forming step for forming an auxiliary barrier film 10C containing the third metal is performed.
  • the third metal for example, Ru (ruthenium) or the like can be used.
  • the auxiliary barrier film 10C made of this Ru film is formed on the entire surface including the inner surfaces of the recess 5 and the communication hole 8 by using, for example, CVD (Chemical Vapor Deposition).
  • CVD Chemical Vapor Deposition
  • FIG. 9B shows the final cross-sectional shape in the case of the second embodiment.
  • the seed layer 14 is formed by the auxiliary norr film 10C and the auxiliary seed film 14A. .
  • the method for forming the Ta film or TaN film for forming the NOR layer 10 is not particularly limited.
  • plasma power or the like is repeatedly supplied and stopped at intervals of several seconds, for example,
  • the thin film may be formed by the so-called ALD (Atomic Layer Deposition) method in which a thin film is formed one by one at an atomic level.
  • the TaN film used for the barrier layer 10 is made of Cu, which is a wiring material or an embedding material, as an interlayer insulating film. This prevents diffusion to a certain insulating layer 4.
  • this TaN film is a metal nitride film, the resistivity is considerably higher than that of Cu as well as of Ta film.
  • this TaN film must have a sufficient thickness at the part where the Cu wiring is in contact with the insulating layer 4, and if it exists with a certain thickness at the bottom of the via hole, that is, the bottom of the communication hole 8, Not only will the via resistance at the bottom of the via hole connected to the wiring layer increase, the electrical characteristics of the Cu wiring will deteriorate, but the reliability will also decrease. This phenomenon occurs not only when the wiring material is Cu but also when other metal materials such as tungsten are used.
  • the TaN film at the bottom of the communication hole 8 such as a via hole is selectively removed by a method different from the punch-through process described above.
  • the thickness of the TaN film deposited on the bottom of the communication hole (via hole) 8 is a process that is extremely small compared to the thickness of the TaN film deposited on other parts.
  • the TaN film is selectively removed by removing the TaN film deposited at the bottom of the communication hole 8 by removing the TaN film by performing Ar etching or the like.
  • the mean free path of atoms and molecules is relatively long! / Under low pressure! / And neutral Ta atoms and neutral N atoms released from metal targets are Because the incident light is incident at a certain angle with respect to the vertical direction of the wafer, the probability of reaching the bottom of the communication hole 8 which is the bottom of the via hole is very low.
  • the side wall of the trench 6 and the bottom of the trench 6, that is, the step The film can be sufficiently formed on the part.
  • the traveling direction of Ta ions which are charged with electricity, is changed by the electric force. Although it is the same as the vertical direction of C, Ta and N atoms tilted to a certain degree to the vertical direction are required to form a film on the side wall of the communication hole 8. Therefore, in this modification, by optimizing the ratio of neutral Ta atoms or neutral N atoms to Ta ions, the TaN film is formed on the sidewall of the trench 6, the bottom (step) of the trench 6, and While forming a film on the side wall of the communication hole 8, it is necessary to create a state where it is difficult to form a film on the bottom of the communication hole 8!
  • the noise power is zero.
  • the process pressure is 8 mTorr or less, preferably 5 mTorr or less.
  • the plasma power which is ICP power, is in the range of 0.75-1.5 kW, preferably in the range of 0.8 to 1.2 kW.
  • the TaN film is formed in the thinnest communication hole 8. Since the TaN film at the bottom is completely removed first, only the TaN film at the bottom of the communication hole 8 can be selectively removed by ending the etching at this point.
  • FIG. 10 is a process diagram showing a part of a modification of the method for forming a barrier layer including a TaN film.
  • the TaN film is formed to form the base film 1OA.
  • the process conditions are set so that film formation is unlikely to occur on the bottom 8B of the communication hole 8.
  • the film thickness HI of the wafer top surface is “100”
  • the film thickness H2 of the bottom 6B of the trench 6 is about “50”
  • the film thickness H3 of the bottom 8B of the communication hole 8 is “20”.
  • the bias power is zero and the process pressure force is mTorr or less, preferably 5 mTorr or less.
  • the plasma power is in the range of 0.75 to 1.5 kW, preferably (or in the range of 0.8 to 1.25 kW. In this way, the bias power is set to zero and etching hardly occurs.
  • a TaN film is deposited, where the bias power is set to zero S and the wafer W is sealed with plasma. For example, a voltage of about 20 to 30 volts is applied, so that ions are attracted to the wafer side to some extent.
  • the film thickness H3 deposited on the bottom 8B of 8 becomes too large.
  • the proportion of Ta ions to neutral elements increases. If the plasma power is higher than 1.5kW or the process pressure is higher than 8mTorr, the proportion of Ta ions will become too large, and the thickness H3 of the TaN film deposited on the bottom 8B of the communication hole 8 will be The difference between the film thickness H3 and the film thicknesses HI and H2 in other parts becomes too small! / ⁇ Preferably! /.
  • the base film 10A made of the TaN film is thinned by performing Ar sputtering as shown in FIG. 10B. Scrap off. In this case, the TaN film on the entire surface is gradually scraped off by Ar sputtering, but the TaN film with the thickness H3 deposited on the bottom 8B of the communication hole 8 with the smallest thickness is selected first. However, the etching process is completed when the lower wiring layer 2 is slightly removed by over-etching. In this way, since only the TaN film at the bottom 8B of the communication hole 8 can be completely removed, it is possible to improve the electrical characteristics by reducing the resistance of this part, that is, the via resistance.
  • a Ru film is formed on the entire surface of the trench 6 and the communication hole 8.
  • the auxiliary nano film 10C is formed. This is the same process as shown in Fig. 9 (A).
  • a seed film 14A may be formed and Cu plating may be applied, or the auxiliary noble film 10C made of this Ru film may be used as a seed film. Since it functions, it is possible to apply a Cu plating process directly on this. It is not limited to.
  • the force for performing the Ar sputtering treatment shown in Fig. 10 (B) is not limited to this, and the base film After forming 10A, the main barrier film 10B made of Ta film shown in FIG. 4 (D) is formed, and then the processes described in FIGS. 4 (E) to 4 (H) are continuously performed. You may make it carry out.
  • the film thickness of the bottom 8B of the communication hole 8 can be made very small compared to the film thickness of other parts. Since only this portion of the TaN film can be selectively removed, for example, via resistance can be suppressed and electrical characteristics can be improved.
  • the communication hole 8 is formed in a part of the recess 5, and the force described by taking the recess 5 formed in a so-called two-stage step shape as an example is not limited to this.
  • the present invention can also be applied to a so-called one-step recess in which the recess 5 itself is a through hole 8 for a through hole or a via hole.
  • the numbers in the above-described embodiments are merely examples, and it is needless to say that the numbers are not limited thereto.
  • the force described by taking the TaN / Ta / Cu, Ta / Ta / Cu laminated structure as an example of the laminated structure of the barrier film / seed film as a whole is not limited to this kind of laminated structure, for example, TiN /
  • the present invention also relates to a Ti / Cu laminated structure, a TaN / Ru / Cu laminated structure, a Ti / Cu laminated structure, and a TiN / Ti / Ru, Ti / Ru, TaN / Ru, and TaN / Ta / Ru laminated structure.
  • the method can be applied.
  • each high-frequency power source is not limited to 13.56 MHz, and other frequencies such as 27.0 MHz can also be used.
  • the inert gas for plasma is not limited to Ar gas, and other inert gas such as He or Ne may be used.
  • the force S described by taking the semiconductor wafer as an example of the object to be processed is not limited thereto, and the present invention can be applied to an LCD substrate, a glass substrate, a ceramic substrate, and the like.

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Abstract

La présente invention concerne un procédé pour la formation d'un film, comprenant la sélection correcte des conditions de traitement pour la formation d'un film comme une couche barrière ou un film de culture auxiliaire, le dégagement de la partie inférieure d'une partie d'encastrement sous les conditions de traitement et la formation d'un film mince sur les faces latérale et supérieure, tout en retirant une couche ayant causé l'augmentation de la résistance électrique dans la partie inférieure de la partie d'encastrement dégagée. Une cible métallique (78) est ionisée dans un contenant de traitement (34) pour produire des particules métalliques contenant des ions métalliques et des particules métalliques sont attirées dans un objet (W) monté sur une table de montage (44) par une énergie électrique dérivée pour former un film mince sur la surface de l'objet avec une partie d'encastrement (5) formée dans sa surface. Pendant que la partie inférieure de la couche la plus inférieure de la partie d'encastrement de l'objet est dégagée pour former une partie d'encastrement dégagée (12), une première couche barrière contenant du métal (10) est formée sur l'objet dans toute sa surface, y compris la surface dans la partie d'encastrement (étape de formation de couche barrière). La partie inférieure de la partie d'encastrement dégagée est ensuite dégagée et un second film de culture auxiliaire contenant du métal (14A) pour le placage est formé sur l'objet dans sa surface, y compris la surface dans la partie d'encastrement (étape de formation de film de culture auxiliaire).
PCT/JP2007/064891 2006-08-01 2007-07-30 Procédé et appareil de formation de film, programme informatique et support de stockage WO2008016004A1 (fr)

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JP2006209944A JP2008041700A (ja) 2006-08-01 2006-08-01 成膜方法、成膜装置及び記憶媒体

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JP5162869B2 (ja) * 2006-09-20 2013-03-13 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7964497B2 (en) * 2008-06-27 2011-06-21 International Business Machines Corporation Structure to facilitate plating into high aspect ratio vias
JP5193913B2 (ja) * 2009-03-12 2013-05-08 東京エレクトロン株式会社 ＣＶＤ−Ｒｕ膜の形成方法および半導体装置の製造方法
JP5544943B2 (ja) * 2010-03-11 2014-07-09 富士通株式会社 半導体装置及びその製造方法
JP5719212B2 (ja) * 2011-03-30 2015-05-13 東京エレクトロン株式会社 成膜方法およびリスパッタ方法、ならびに成膜装置
JP2013077631A (ja) * 2011-09-29 2013-04-25 Ulvac Japan Ltd 半導体装置の製造方法、半導体装置
US9728501B2 (en) * 2015-12-21 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
TW202409344A (zh) * 2022-07-05 2024-03-01 日商東京威力科創股份有限公司 基板液處理方法及基板液處理裝置

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