TW200824041A - Method and apparatus of forming film, and recording medium - Google Patents

Method and apparatus of forming film, and recording medium Download PDF

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Publication number
TW200824041A
TW200824041A TW96128229A TW96128229A TW200824041A TW 200824041 A TW200824041 A TW 200824041A TW 96128229 A TW96128229 A TW 96128229A TW 96128229 A TW96128229 A TW 96128229A TW 200824041 A TW200824041 A TW 200824041A
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Taiwan
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film
metal
film forming
processed
concave portion
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TW96128229A
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Chinese (zh)
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Taro Ikeda
Yasushi Mizusawa
Takashi Sakuma
Osamu Yokoyama
Tatsuo Hatano
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Tokyo Electron Ltd
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Publication of TW200824041A publication Critical patent/TW200824041A/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/021—Cleaning or etching treatments
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C23C14/025—Metallic sublayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

To provide a method and an apparatus of forming a film capable of appropriately selecting film formation process conditions of a barrier layer, an auxiliary seed layer or the like to scrape a bottom of a recess, and forming a thin film on a side face or an upper surface while removing a layer to cause a rise in electric resistance on the bottom of a scraped dent, and a recording medium. The film forming method ionizes a metallic target 78 in a processing vessel 34 to generate metallic particles containing metallic ions, pulls the particles into a material W to be processed mounted on a mount 44 by bias power, and forms a thin film on the surface of the material where a recess 5 is formed on the surface. Further, the method includes a barrier layer formation step of forming the barrier layer 10 made of a thin film containing first metal entirely on the surface of the material to be processed containing the surface in the recess while scraping the bottom of the lowermost layer of the recess to form the scraped dent 12, and an auxiliary seed film formation step of further scraping the bottom of the scraped dent and forming the auxiliary seed film 14A for plating made of a thin film containing second metal on the surface of the material to be processed containing the surface in the recess.

Description

200824041 九、發明說明 【發明所屬之技術領域】 本發明關於在半導體晶圓等被處理體表面形成之凹部 表面，有效形成金屬膜等薄膜的成膜方法、成膜裝置、電 腦程式及記憶媒體。 【先前技術】 通常製造半導體裝置時係對半導體晶圓重複進行成膜 處理或圖案鈾刻處理等各種處理而製造所要裝置，因爲半 導體裝置更高集積化及高微細化之要求，使線寬或孔（ ho le )徑益加微細化。因此作爲配線材料或塡埋材料，由 於各種尺寸之微細化而需要更減少電阻導致電阻極小、且 便宜之銅有被使用的傾向（特開2000-77365號公報）。 作爲配線材料或塡埋材料而使用銅時，考慮與其下層間之 密接性等問題，通常以鉬（Ta )金屬或氮化鉅（TaN )等 作爲阻障層。 欲形成該阻障層時，首先，於電漿濺鍍裝置內於晶圓 表面形成作爲底層之氮化鉅膜（以下稱TaN膜）或钽膜（ 以下稱Ta膜）之後，於同一電漿濺鍍裝置內形成鉬膜（ 底層爲Ta膜時變化成膜條件）而形成阻障層。之後，於 該阻障層表面形成銅膜構成之較薄之種（seed)膜，之後 ，於晶圓表面全體進行鍍銅處理而埋入凹部內。 但是，將下層配線層與挾持絕緣膜被積層的上層配線 層進行電連接時，係於上述下層配線層形成上述絕緣層之 -5 - 200824041 後，於該絕緣層形成導孔（via hole )或通孔（through hole)等連通孔，於該連通孔底部露出上述下層配線層之 後，以上層配線層之材料塡埋該連通孔之同時，沈積形成 上層配線層。如上述說明，因爲微細化之要求，使線寬或 孔徑益加變小，關於上述上下之配線層間之連接構造亦需 要採取更加降低其電阻之工夫。例如可採用將上述連通孔 底部於下層配線層之厚度方向削去特定深度，而更縮小塡 埋該連通孔之塡埋材料與下層配線層間之接觸電阻的構造 。稱此種構造爲沖孔（punch through )構造，稱此作成方 法爲沖孔製程。 於此沖孔製程，雖削去凹部底部而形成削去凹陷部， 但是和凹部之寬度無關，而難以形成同一深度之削去凹陷 部。另外，於凹部難以良好精確度形成阻障層或薄種膜亦 爲實情。 【發明內容】 (發明所欲解決之課題） 本發明有鑑於上述問題，目的在於提供，藉由適當選 擇阻障層或種膜等之成膜時之製程條件，可以僅選擇性削 去凹部之最下層底部而在包含凹部內表面之被處理體表面 全體區域形成薄膜，而且不受凹部之寬度影響，可以削去 同一深度範圍之底部、形成同一深度之削去凹陷部，另外 ，可以除去削去凹陷部之底部之電阻上升原因之例如 Ta/Cu混合層，而於凹部側面或上面形成薄膜的成膜方法[Technical Field] The present invention relates to a film forming method, a film forming apparatus, a computer program, and a memory medium for efficiently forming a thin film such as a metal film on the surface of a concave portion formed on a surface of a workpiece such as a semiconductor wafer. [Prior Art] When manufacturing a semiconductor device, various processes such as film formation processing or pattern uranium etching are repeated on a semiconductor wafer to manufacture a desired device. Because of the higher integration and high refinement of the semiconductor device, the line width or The hole ( ho le ) diameter is added and refined. Therefore, as a wiring material or a burying material, it is necessary to reduce the electric resistance of various sizes, and it is necessary to reduce the electric resistance, and the copper having a small electric resistance is required to be used (JP-A-2000-77365). When copper is used as the wiring material or the buried material, a barrier layer such as molybdenum (Ta) metal or tantalum nitride (TaN) is usually considered in consideration of problems such as adhesion to the underlying layer. When the barrier layer is to be formed, first, in the plasma sputtering apparatus, a nitride film (hereinafter referred to as a TaN film) or a tantalum film (hereinafter referred to as a Ta film) as a bottom layer is formed on the surface of the wafer, in the same plasma. A barrier layer is formed by forming a molybdenum film in the sputtering apparatus (the film formation condition is changed when the underlayer is a Ta film). Thereafter, a thin seed film formed of a copper film is formed on the surface of the barrier layer, and then the entire surface of the wafer is subjected to a copper plating treatment to be buried in the concave portion. However, when the lower wiring layer and the upper wiring layer in which the barrier insulating film is laminated are electrically connected, a via hole or a via hole is formed in the insulating layer after forming the insulating layer -5 - 200824041 in the lower wiring layer. A communication hole such as a through hole is formed, and after the lower wiring layer is exposed at the bottom of the communication hole, the material of the upper wiring layer is buried and the upper wiring layer is deposited. As described above, since the line width or the aperture is reduced in size as required for the miniaturization, it is necessary to take measures to further reduce the electric resistance of the connection structure between the upper and lower wiring layers. For example, it is possible to reduce the contact resistance between the buried material of the via hole and the underlying wiring layer by cutting the bottom of the via hole in the thickness direction of the lower wiring layer to a specific depth. This structure is referred to as a punch through structure, which is referred to as a punching process. In this punching process, although the bottom of the recess is cut to form the cut recess, the recess is not formed at the same depth, and it is difficult to form the recessed portion of the same depth. In addition, it is also difficult to form a barrier layer or a thin film in a concave portion with good precision. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the invention to provide a process for selectively removing only a concave portion by appropriately selecting a process condition at the time of film formation such as a barrier layer or a seed film. The bottom layer of the lowermost layer forms a film on the entire surface of the surface of the object to be processed including the inner surface of the concave portion, and is not affected by the width of the concave portion, and the bottom portion of the same depth range can be cut off to form the cut-out recess portion of the same depth, and the cut portion can be removed. A film forming method for forming a thin film on the side or above the concave portion due to, for example, a Ta/Cu mixed layer due to an increase in resistance at the bottom of the depressed portion

200824041 、成膜裝置、電腦程式及記憶媒體。 本發明人經由硏究獲得，藉由電漿濺鍍處理形 膜時，適當調整偏壓或對金屬靶之直流電力或電漿 製程條件，而控制金屬粒子之中性原子與金屬粒子 之比率，而可於包含半導體晶圓表面之晶圓表面全 形成金屬膜的發現。 本發明人經由硏究獲得，於電漿濺鍍處理時， 設定製程壓力成爲大於習知處理壓力，和離子比較 較多之金屬粒子之中性原子，依此而於晶圓表面之 或側壁部分使Cu中性原子成爲優勢，而可積極沈| ，另外，於深的凹陷部之底部藉由偏壓電力而使被 深度部的金屬離子或氣體離子成爲優勢，而可以更 底部的發現。 (用以解決課題的手段） 本發明之成膜方法，其特徵爲具備：載置工 面形成有凹部的被處理體，載置於可抽成真空的 內設置之載置台；及形成工程，於處理容器內藉 體電漿化而產生之電漿，使金屬靶離子化而產生 離子的金屬粒子，藉由偏壓電力使該金屬粒子被 述處理容器內之載置台上載置的被處理體而於上 體表面形成含有上述金屬的薄膜；於上述被處理 成薄膜的工程係具有：阻障層形成工程，係削去 理體之凹部之底部而形成削去凹陷部之同時，於 成金屬 電力等 離子間 體區域 特別是 可產生 平坦面 I Cu膜 吸引至 加削去 ，使表 理容器 惰性氣 有金屬 引至上 被處理 表面形 述被處 含上述 -7- 200824041 凹部內表面之上述被處理體表面全體形成含有第1金屬的 阻障層；及補助種膜形成工程，更進一步削去上述削去凹 陷部之底部，而於包含上述凹部內表面之上述被處理體表 面形成含有第2金屬的鍍層用補助種膜。 依本發明，藉由適當選擇阻障層或補助種膜等之成膜 時之製程條件，可以選擇性僅削去凹部之最下層底部之同 時，在包含凹部內之表面的被處理體之表面全體區域形成 φ 薄膜。而且不受凹部之寬度影響，可以削去同一深度範圍 之底部、形成同一深度之削去凹陷部，另外，可以除去削 去凹陷部之底部之電阻上升原因之例如Ta/Cu混合層之同 時，於凹部之側面或上面形成薄膜。 本發明之成膜方法，係於上述補助種膜形成工程之後 ，進行本質種膜形成工程而形成鍍層用之本質種膜。 本發明之成膜方法，係於上述本質種膜形成工程之後 ，進行對上述第2金屬施予鍍層之鍍層工程。 φ 本發明之成膜方法中，上述阻障層形成工程包含：底 層膜形成工程，係於包含上述凹部內表面之上述被處理體 表面全體形成由上述第1金屬之氮化膜構成的底層膜；及 主阻障膜形成工程，係於形成上述削去凹陷部之同時，至 ^ 少於上述凹部內之側壁形成由上述第1金屬之單體構成的 主阻障膜。 本發明之成膜方法中，上述第1金屬由Ta構成，而 且上述第2金屬由Cu構成。 本發明之成膜方法中，上述阻障層形成工程包含：底 -8- 200824041 層膜形成工程，係於包含上述凹部內表面之上述被處理體 表面全體形成由上述第1金屬之氮化膜構成的底層膜；主 阻障膜形成工程，係於形成上述削去凹陷部之同時，至少 於上述凹部內之側壁形成由上述第1金屬之單體構成的主 阻障膜；及補助阻障膜形成工程，係形成含有第3金屬之 補助阻障膜。 本發明之成膜方法中，於上述補助阻障膜形成工程之 φ 後’進行對上述第2金屬施予鍍層之鍍層工程。 本發明之成膜方法中，上述第1金屬由Ta構成，上 述第2金屬由Cu構成，而且上述第3金屬由Ru構成。 本發明之成膜方法中，上述補助種膜形成工程，係設 定上述處理容器內之壓力爲30〜90mT〇rr之範圍內而進行 〇 本發明之成膜方法中，上述補助種膜形成工程，係設 定上述偏壓電力爲100〜250瓦特之範圍內而進行。 9 本發明之成膜方法中，上述補助種膜形成工程，係設 定上述電漿形成用電力爲〇· 5〜2千瓦特之範圍內而進行。 本發明之成膜方法中，上述被處理體之凹部，係具有 成爲導孔（via hole)或通孔（through hole)之連通孔， ' 被形成爲2階段之段部形狀。 本發明之成膜方法中，上述凹部，係由成爲導孔或g 孔之連通孔構成。 本發明之成膜裝置，係具備：可抽成真空的處埋容$ ;載置台，用於載置表面形成有凹部的被處理體；氣體_ -9 - 200824041 入手段，對上述處理容器內導入至少含有惰性氣體的特定 氣體；電漿產生源，產生電漿電力，對上述處理容器內產 生惰性氣體之電漿；金屬靶，設於上述處理容器內，被施 加直流電力，藉由上述電漿應被離子化；偏壓電源，對上 述載置台供給特定之偏壓電力；及裝置控制部，用於控制 氣體導入手段、電漿產生源、及偏壓電源；其特徵爲：上 述裝置控制部，係控制氣體導入手段、電漿產生源、及偏 壓電源，以使上述凹部內之上述削去凹陷部之底部更進一 步被削去，而於包含上述凹部內表面之上述被處理體表面 形成含有第2金屬的薄膜所構成之鍍層用補助種膜。 本發明之電腦程式，係使電腦執行成膜方法者，其特 徵爲：成膜方法具備：載置工程，使表面形成有凹部的被 處理體，載置於可抽成真空的處理容器內設置之載置台； 及形成工程，於處理容器內藉由惰性氣體電漿化而產生之 電漿，使金屬靶離子化而產生含有金屬離子的金屬粒子， 藉由偏壓電力使該金屬粒子被吸引至上述處理容器內之載 置台上載置的被處理體而於上述被處理體表面形成含有上 述金屬的薄膜；於上述被處理體表面形成薄膜的工程具有 :補助種膜形成工程，更進一步削去凹部內之底部之削去 凹陷部，而於包含上述凹部內表面之上·述被處理體表面形 成含有第2金屬的鍍層用補助種膜。 本發明之記憶媒體，係記憶有使電腦執行成膜方法之 電腦程式者，其特徵爲：成膜方法具備：載置工程，使表 面形成有凹部的被處理體，載置於可抽成真空的處理容器 -10- 200824041 內設置之載置台；及形成工程，於處理容器內藉由惰性氣 體電漿化而產生之電漿，使金屬靶離子化而產生含有金屬 離子的金屬粒子，藉由偏壓電力使該金屬粒子被吸引至上 述處理容器內之載置台上載置的被處理體而於上述被處理 體表面形成含有上述金屬的薄膜；上述被處理體表面形成 薄膜的工程具有··補助種膜形成工程，更進一步削去上述 凹部內之底部之削去凹陷部，而於包含上述凹部內表面之 上述被處理體表面形成含有第2金屬的鍍層用補助種膜。 【實施方式】 爲容易理解本發明，參照圖1 1、1 2說明通常之沖孔 製程之一例。圖1 1爲半導體晶圓上形成之連通孔之塡埋 前之狀態圖，圖11(A)爲平面圖。圖11(B)爲圖11 ( A )中之沿A_ A線之斷面圖。圖1 1 ( C )爲斜視圖。圖12 '爲連通孔之塡埋工程圖。 9 半導體晶圓w爲例如由矽基板構成，於該矽基板表 面依序積層例如銅構成之下層配線層2及氧化矽膜構成之 絕緣層4。於絕緣層4之表面形成凹部5。該凹部5，成爲 上層配線層形成用之特定寬度之配線溝、亦即溝部（ * trench ) 6。於該溝部6之底部之一部分，形成貫穿絕緣層 4、和下層配線層2連通的成爲導孔（via hole )或通孔（ through hole)之連通孔8。連通孔8之直徑L1極小、例 如爲約60〜20Onm，凹部5，亦即溝部6之寬度L2例如爲 約 6 0 〜1 0 0 0 n m 〇 -11 - 200824041 欲塡埋上述連通孔8及溝部6時，首先，如圖1: )所示，在包含溝部6內或連通孔8內之表面的晶U 之表面全體，藉由例如電漿濺鍍等形成金屬膜構成之 層1 〇，用於提升和底層間之密接性或防止銅之朝絕緣 之擴散或遷移等之產生。阻障層10，主要採用例如 膜與Ta膜之2層構造，或以互相成膜條件不同而形 Ta膜彼此之2層構造。 φ 之後，如圖12 ( B )所示，使用例如惰性氣體之 氣體進行電漿蝕刻，削去上述連通孔8之底部形成之 層1 〇，進而蝕刻其底層之下層配線層2，形成特定深 削去凹陷部1 2。 之後，如圖12 ( C )所示，進行例如濺鍍，在包 述削去凹陷部12或連通孔8或溝部6之內面的全表 成極薄之電鍍用種層14，其中，作爲種層14，係因 如於後續工程進行銅鍍層而使用Cu膜。 Φ 之後，如圖12 ( D )所示，以種層14爲起點進 鍍，以上層配線層1 6之材料分別塡埋削去凹陷部1 2 _ 通孔8、及溝部6。上層配線層16之材料，如上述說 係使用例如銅。 如圖1 2 ( E )所示，以硏磨處理等削去上面之不 金屬材料，形成和下層配線層2電連接之上層配線層 又，如上述說明，於溝部6之底部具有導孔或通 連通孔8，其斷面以2階段之段部形狀形成之凹部5 狀被稱爲所謂雙嵌入（Dual Damascene)構造。 2 ( A B W 阻障 層4 TaN 成之 ：Ar 阻障 度之 含上 面形 爲例 行電 、連 明， 要之 16。 孔之 之形 -12- 200824041 於上述習知成膜方法，如圖1 2 ( B)所示電漿蝕刻工 程中，於例如點P1所示角部，因蝕刻而飛散之阻障層粒 子具備在收斂於特定方向之角度範圍內具有指向性而飛散 之特性。此情況下，線寬或溝寬極大時雖不會有顯著問題 ，但如上述說明，在溝寬等小至約100nm時，朝上述特定 方向飛散之粒子附著於對向壁面而形成沈積突起物1 8之 情況有可能產生。如上述說明，產生沈積突起物1 8時， 於後續圖1 2 ( C)所示電漿濺鍍工程中，濺鍍粒子之指向 性高而產生成爲沈積突起物1 8之屏蔽的部分，亦即產生 屏蔽（Shad〇 wing )現象，如此則，種層1 4難以附著於沈 積突起物1 8之屏蔽部分20的問題存在。種層14未附著 之部分產生時，如圖12 ( D )所示，於該部分產生空洞（ void) 22，而較爲不好。 圖1 3爲各種不同寬度L2之凹部5 (溝部6 )之態樣 圖。於晶圓W之表面，實際上如圖13所示，存在多數種 類之不同寬度L2之凹部5。此情況下，即使連通孔8 (其 直徑L1相同）之深寬比相同時，因爲溝部6深寬比不同 導致自連通孔8之底部看至上方之角度0 1、0 2，如圖所 示呈現不同（角度01<角度02)，因而凹部最下層之連 通孔8之底部所沈積之阻障層1 0之厚度Η1、H2分別不 同。該厚度HI、Η2之不同將引起削去該阻障層而形成於 底部之削去凹陷部1 2之深度有所變動（不均一），而較 不好之問題。 又，於圖12 ( A)所示，形成阻障層1 〇時，一部分 -13- 200824041 之Ta金屬被偏壓電力吸引而打入連通孔8之底部之Cu下 層配線層2之較深處，於此形成削去凹陷部1 2時因爲殘 存成爲電阻變大原因之Ta/Cu混合物，而導致該部分之連 接電阻上升。 以下依據圖面說明本發明成膜方法、成膜裝置、電腦 程式及記憶媒體之一實施形態。 圖1爲本發明之成膜裝置之一例之斷面圖。其中成膜 裝置以 ICP ( Inductively Coupled Plasma)型電漿濺鍍裝 置爲例說明。如圖所示，該成膜裝置3 2，具有例如鋁等形 成爲筒狀體之處理容器34。處理容器34被接地，於底部 36設置排氣口 38，介由節流閥40，藉由真空幫補42可抽 成真空。 於處理容器34內設置例如鋁等形成之圓板狀載置台 44之同時，於載置台44之上面設置靜電夾頭46，於靜電 夾頭46上可吸附保持被處理體之半導體晶圓W，於靜電 夾頭46必要時施加吸附用直流電壓（未圖式）。載置台 44，係由較其下面之中心部更朝下方延伸之支柱4 8支撐 ，該支柱48之下部貫穿上述容器底部36。支柱48，可藉 由升降機構（未圖示）上下移動，可升降載置台44本身 〇 包圍支柱48而可伸縮的蛇腹狀之金屬波紋管50被設 置，金屬波紋管5 0之上端氣密接合於載置台4 4之下面， 其之下端氣密接合於底部3 6之上面，如此則可維持處理 容器34內之氣密性之同時，可容許載置台44之升降移動 -14- 200824041 。於該載置台4 4，形成冷媒循環路5 2可流通冷媒而冷卻 晶圓W，該冷媒介由支柱48內之流路（未圖式）被供給/ 排出。 又，於容器底部3 6，朝其之更上方以豎立方式設置例 如3個（圖中僅圖示2個）支撐銷54，和支撐銷54對應 而於載置台44形成銷插通孔56。因此，下降載置台44時 ，以貫穿銷插通孔56之支撐銷54上端部承受晶圓W，使 該晶圓W於其和由外部進入之搬送臂部（未圖示）間可 移動。因此，於處理容器3 4之下部側壁設置可關閉之閘 閥58可使上述搬送臂部進入。 於載置台44上設置之靜電夾頭46，介由配線60連接 高頻電源構成之偏壓電源62用於產生例如13.56MHz之高 頻，可對載置台44施加特定之偏壓電力。又，偏壓電源 62必要時可控制其輸出之偏壓電力。 於處理容器34之天井部，介由0型環等之密封構件 66以氣密方式設置例如由氮化鋁等介電體構成之對高頻具 有透過性之透過板64。於透過板64外方，於處理容器34 內之處理空間6 8設置電漿產生源7 0，可使例如作爲電漿 氣體之Ar氣體電漿化而產生電漿。作爲該電漿氣體，亦 可取代Ar氣體而使用其他惰性氣體，例如He、Ne等。具 體言之爲，電漿產生源70，具有對應於透過板64而設置 之感應線圈部72，於感應線圈部72連接電漿產生用之例 如13·56ΜΗζ之高頻電源74，介由透過板64可將高頻導 入處理空間68。其中該局頻電源74輸出之電漿電力亦可 -15- 200824041 於必要時進行控制。 於透過板64正下方設置使導入之高頻擴散的例如鋁 構成之導波板76。於導波板76下部，以包圍處理空間68 之上側部方式設置例如斷面朝內側傾斜之環狀（截頭圓錐 殻形狀）之金屬靶78，於金屬靶78連接可變直流電源80 。因此，由可變直流電源80輸出之直流電力必要時可控 制。金屬靶78，例如於Ta膜或TaN膜之形成時使用钽金 屬，於Cu膜之形成時使用銅，彼等金屬藉由電漿中之Ar 離子被濺鍍成爲金屬原子或金屬原子團之同時，通過電漿 中時多數被離子化。 於金屬靶78下部，以包圍處理空間68之方式設置例 如鋁構成之圓板狀保護蓋82，該保護蓋82被接地之同時 ，其下部朝內側彎曲而位於載置台44之側部附近。於處 理容器44底部設置作爲氣體導入手段之例如氣體導入口 84，用於對處理容器34內導入必要之特定氣體。由該氣 體導入口 84，使例如作爲電漿氣體之Ar氣體或其他必要 之例如N 2氣體等，經由氣體流量控制器、閥等構成之氣 體控制部8 6被供給。 成膜裝置3 2之各構成部被連接於例如電腦等構成之 裝置控制部88而被控制。具體言之爲，裝置控制部88控 制偏壓電源62、電漿產生用高頻電源74、可變直流電源 8〇、氣體控制部86、節流閥40、真空幫補42等之動作， 本發明之金屬膜等薄膜形成時之動作如下。 首先，在裝置控制部88支配下，作動真空幫補42使 -16 - 200824041 處理容器44內抽成真空，作動氣體控制部86之同時流入 Ar氣體，控制節流閥4 0使處理容器4 4內維持特定真空 度，之後’介由可變直流電源8 0對金屬靶7 8施加直流電 力，介由高頻電源74對感應線圈部72施加高頻電力（電 漿電力）。 另外，裝置控制部8 8亦對偏壓電源62發出指令，對 載置台44施加特定之偏壓電力，於如此被控制之處理容 器3 4內，藉由施加於金屬靶7 8、感應線圈部72之電力形 成Ar電漿，產生Ar離子，彼等離子撞及金屬靶78使金 屬靶78被濺鍍而放出金屬粒子。 又，來自被濺鍍之金屬靶78的金屬粒子（金屬原子 、金屬原子團）通過電漿中時大多數被離子化，其中金屬 粒子，成爲被離子化之金屬離子與電氣中性之中性金屬原 子混在之狀態朝下方飛散。其中，特別是金屬離子被載置 台44施加之偏壓電力吸引而作爲對晶圓W具有高指向性 之金屬離子沈積於載置台44上之晶圓W。 如後述說明，裝置控制部88，例如對偏壓電源62下 達輸出較大輸出的指令，而於電漿中之Ar離子亦可被吸 引至載置台44側，可同時實現成膜與濺鍍触刻之雙方。 裝置各構成部之控制，係藉由裝置控制部88，依據特定條 件下可進行金屬膜之成膜而被作成的程式而被控制。此時 例如於FD (軟碟）或CD (光碟），快閃記憶體等記憶媒 體90儲存包含各構成部之控制用指令的程式’依該程式 控制各構成部而於特定條件下進行處理。 -17- 200824041 以下說明使用上述構成之成膜裝置32進行之本發明 之成膜方法。 圖2爲濺鍍鈾刻之角度依存性之分布圖。圖3爲偏壓 電力與晶圓上面之成膜量間之關係之分布圖。圖4爲本發 明之成膜方法中第1實施形態說明用之流程圖。 首先，本發明方法之第1特徵爲，在一連串成膜處理 內之特定工程中，藉由電漿之濺鍍成膜而形成金屬膜等薄 膜時，藉由控制偏壓電力、直流電力、電漿電力等成爲適 當之大小。如此則，設定爲對金屬離子之吸引引起之成膜 及電漿氣體（Ar離子）引起之濺鍍触刻同時產生，而且 設定爲凹部最下層之底部被削去狀態，使半導體晶圓上形 成之凹部最下層之底部被削去而形成削去凹陷部之同時， 可於表面沈積金屬膜。具體言之爲，此時之偏壓電力被設 爲，對於金屬靶78之對向面、亦即圖1之晶圓W上面， 以對金屬離子吸引產生之成膜速率和電漿氣體（Ar+)引 起之濺鍍蝕刻之触刻速率成爲大略均衡之大小。 本發明方法之第2特徵爲，藉由電漿濺鍍進行成膜處 理而形成金屬膜時，特別是設定處理容器內之壓力（製程 壓力）成爲遠大於習知方法，和離子之產生量比較可產生 更多量之金屬粒子之中性金屬原子，依此而於晶圓表面或 側壁部分使中性金屬原子成爲優勢，而可積極沈積金屬膜 。另外，於深的凹陷部之底部藉由偏壓電力而使被吸引至 深度部的金屬離子或氣體離子成爲優勢，而可以更加削去 底部之例如Ta/Cu混合層。 -18- 200824041 以下更詳細說明。 首先，在不考慮成膜量情況下檢討電漿氣體引起之灑 鍍鈾刻之鈾刻速率之特性時，濺鍍面之角度與蝕刻速率之 關係如圖2之分布圖所示，其中，濺鍍面之角度係指濺鍍 面之法線成爲濺鍍氣體（Ar離子：Ar+ )之射入方向（圖 中向下之方向）的角度，例如晶圓W上面與凹部5(參照 圖1 2 )之底部均爲〃 〇度〃，凹部側壁爲〃 90度〃。 由該分布圖可知，晶圓上面（濺鍍面之角度=0度） 某種程度被濺鍍鈾刻，但凹部側壁（濺鍍面之角度=90度 )幾乎不被進行濺鍍鈾刻。又，凹部開口之角部（濺鍍面 之角度=40〜80度附近）被強烈進行濺鍍蝕刻。 又，於圖1所示ICP型濺鍍裝置構成之成膜裝置，晶 圓W側施加之偏壓電力與晶圓上面（非凹部側壁）沈積 之成膜量之關係如圖3所示。亦即，在一定之電漿電力及 對金屬靶78施加一定之直流電力情況下，偏壓電力不是 太大時，藉由金屬離子之吸引及中性金屬原子而可獲得高 的成膜量，但隨偏壓電力之增加，晶圓表面被偏壓電力加 速之電漿氣體（Ar離子）濺鍍之傾向逐漸變強（參照圖2 )。結果，特意沈積之金屬膜被蝕刻掉。 當然，該蝕刻隨偏壓電力變大而變強。因此，當被吸 引之金屬離子及中性金屬原子引起之成膜速率，和電漿氣 體之離子引起之濺鍍蝕刻之飩刻速率成爲相同時，成膜與 蝕刻互相抵消，晶圓上面之成膜量成爲〇，此時之條件對 應於圖3之點Xl(偏壓電力：350W)。又，圖3之偏壓 -19- 200824041 電力或成膜量僅爲一例，藉由控制電漿電力與直流電力可 使上述特性曲線如圖3之一點虛線變動。 習知此種濺鍍裝置之通常動作條件爲區域A1之部分 ，係偏壓電力設爲不太大，.可稼動高的成膜量（成膜速率 )之區域。亦即，和偏壓爲0時幾乎相同（未產生惰性氣 體之電漿引起之飩刻），而且被吸引之金屬離子成爲最大 之區域，於凹部底部亦有某種程度成膜量進行之區域。相 φ 對於此，本發明主要係在當被吸引之金屬離子及中性金屬 原子引起之成膜，和電漿氣體引起之濺鍍蝕刻同時產生之 區域進行。更詳言之爲，如上述說明，於晶圓W之上面 ，在被吸引之金屬離子及中性金屬原子引起之成膜速率， 和電漿氣體引起之濺鍍蝕刻之蝕刻速率成爲大略均衡之區 域A2進行。其中所謂「大略均衡」並非僅指晶圓W上面 之成膜量爲“ 0 “之情況，亦包含和區域A 1之成膜量比較 約爲3/10之些許膜厚而產生之成膜量。 φ 爲理解以上現象，說明本發明方法。 首先，於圖1，使載置台4 4下降至下方狀態下，介由 處理容器34之閘閥58將晶圓W搬入可吸成真空之處理 容器34內，使其支撐於支撐銷54上。於此狀態下上升載 ' 置台44使晶圓W受讓於其上面，該晶圓W藉由靜電夾頭 46被吸附保持於載置台44上面。 晶圓W被載置、吸附保持於載置台44上之後開始成 膜處理。此時，於晶圓W上面，和圖1 1 ( B )所示構成相 同構造之凹部5 (參照圖4(A))事先於搬入前藉由前工 -20- 200824041 形 係 成 形 內 應 44 藉 先 行 膜 □ 氣 (B 形 電 爲 束 ;之 :即 :域 程被形成。亦即，於下層之Cu構成的下層配線層2上 成絕緣層4，於該絕緣層4形成上述凹部5。該凹部5， 由溝形狀之溝部6 (參照圖1 1 ( A))構成，於底部形 可以到達配線層2之導孔或通孔之連通孔8，凹部全體 成爲2段之階梯形狀。200824041, film forming equipment, computer programs and memory media. The present inventors obtained a method for controlling the ratio of a neutral atom to a metal particle of a metal particle by appropriately adjusting a bias voltage or a direct current power or a plasma process condition of a metal target by plasma sputtering. The discovery that a metal film can be formed on the surface of the wafer including the surface of the semiconductor wafer. The inventors obtained through the study, in the plasma sputtering process, the process pressure is set to be larger than the conventional processing pressure, and the metal particles are relatively neutral, and thus the wafer surface or the sidewall portion Cu neutral atoms are advantageous, and they can be positively swelled. Further, metal ions or gas ions in the depth portion are dominant by the bias electric power at the bottom of the deep depressed portion, and the bottom portion can be found. (Means for Solving the Problem) The film forming method of the present invention is characterized in that: the object to be processed in which the concave portion is formed on the mounting surface is placed on the mounting table which is placed in a vacuumable manner; The metal particles generated by ionizing the plasma in the container and ionizing the metal target to generate ions, and the metal particles are placed on the substrate to be placed on the mounting table in the processing container by bias electric power. Forming a thin film containing the above metal on the surface of the upper body; the engineering system processed as the thin film has a barrier layer forming process, which is to cut the bottom of the concave portion of the physical body to form the cut recessed portion, and to form a metal power The plasma inter-body region, in particular, can produce a flat surface, and the Cu film is attracted to the undercut, so that the inert gas of the symmetry container is led to the upper surface to be processed, and the above-mentioned object to be processed containing the inner surface of the recess of the above-mentioned -7-200824041 is described. Forming a barrier layer containing the first metal as a whole; and forming a film forming process, further cutting off the bottom portion of the recessed portion, and including the recess Body surface to be treated with a surface coating formed of a film containing a second grant seed metal. According to the present invention, by appropriately selecting the process conditions at the time of film formation such as the barrier layer or the auxiliary seed film, it is possible to selectively remove only the bottom portion of the lowermost layer of the concave portion while the surface of the object to be treated including the surface in the concave portion A φ film is formed in the entire area. Moreover, it is possible to remove the bottom portion of the same depth range and to form the shaved portion of the same depth without being affected by the width of the concave portion, and to remove the reason for the resistance increase of the bottom portion of the depressed portion, for example, the Ta/Cu mixed layer, A film is formed on the side or on the side of the recess. In the film formation method of the present invention, after the above-mentioned auxiliary seed film formation process, an essential seed film formation process is performed to form an essential seed film for plating. In the film forming method of the present invention, after the above-described essential film forming process, a plating process for applying a plating layer to the second metal is performed. φ In the film forming method of the present invention, the barrier layer forming process includes an underlayer film forming process for forming an underlayer film composed of the nitride film of the first metal on the entire surface of the object to be processed including the inner surface of the concave portion. And the main barrier film forming process is to form the main barrier film composed of the single metal of the first metal at the same time as the side wall of the recessed portion is formed. In the film forming method of the present invention, the first metal is composed of Ta, and the second metal is made of Cu. In the film forming method of the present invention, the barrier layer forming process includes: a bottom layer forming process of the bottom layer -8-200824041, wherein the nitride film of the first metal is formed on the entire surface of the object to be processed including the inner surface of the concave portion a primary barrier film forming process for forming a primary barrier film composed of a single metal of the first metal at least a sidewall of the recessed portion while forming the above-described stripped recessed portion; and a protective barrier In the film formation process, a barrier film containing a third metal is formed. In the film forming method of the present invention, the plating process for applying the plating layer to the second metal is performed after the φ of the barrier film forming process. In the film forming method of the present invention, the first metal is made of Ta, the second metal is made of Cu, and the third metal is made of Ru. In the film forming method of the present invention, the auxiliary seed film forming process is performed by setting the pressure in the processing container to a range of 30 to 90 mT 〇rr, and performing the film forming method of the present invention. This is done by setting the above-mentioned bias power to be in the range of 100 to 250 watts. In the film forming method of the present invention, the above-mentioned auxiliary seed film forming process is performed by setting the electric power for forming the plasma to be in the range of 〜 5 to 2 kW. In the film forming method of the present invention, the concave portion of the object to be processed has a communication hole which is a via hole or a through hole, and is formed in a two-stage segment shape. In the film forming method of the present invention, the concave portion is constituted by a communicating hole which is a via hole or a g hole. The film forming apparatus of the present invention includes: a chamber capable of drawing a vacuum; a mounting table for placing a processed object having a concave portion formed on the surface; and a gas _-9 - 200824041 means for injecting the inside of the processing container Introducing a specific gas containing at least an inert gas; generating a source of plasma, generating plasma power, and generating a plasma of an inert gas in the processing container; the metal target is disposed in the processing container, and DC power is applied by the electricity The slurry should be ionized; a bias power source supplies a specific bias power to the mounting table; and a device control unit for controlling the gas introduction means, the plasma generating source, and the bias power source; wherein the device controls a control gas introducing means, a plasma generating source, and a bias power source for further cutting the bottom of the shaved recess in the recess to cover the surface of the object to be processed including the inner surface of the recess A seed film for a plating layer comprising a film containing a second metal is formed. The computer program of the present invention is a method for forming a film forming method by a computer, characterized in that the film forming method includes: a substrate to be processed, a processed object having a concave portion formed on a surface thereof, and placed in a processing container capable of being evacuated a mounting stage; and a forming process, the plasma generated by the plasma of the inert gas in the processing vessel ionizes the metal target to generate metal ions containing metal ions, and the metal particles are attracted by bias power a film to be processed placed on the mounting table in the processing container to form a film containing the metal on the surface of the object to be processed; and a process for forming a film on the surface of the object to be processed: an auxiliary seed film forming process, and further cutting The depressed portion is cut in the bottom portion of the concave portion, and the auxiliary seed film for the plating layer containing the second metal is formed on the inner surface of the concave portion including the inner surface of the concave portion. The memory medium of the present invention is a computer program that stores a film forming method for a computer, and is characterized in that the film forming method includes: a substrate to be processed, and a processed object having a concave portion formed on the surface, which is placed in a vacuum a processing chamber provided in the processing container -10- 200824041; and a forming process in which a plasma generated by plasma-burning of an inert gas is used to ionize the metal target to generate metal particles containing metal ions. The bias electric power causes the metal particles to be attracted to the object to be processed placed on the mounting table in the processing container to form a film containing the metal on the surface of the object to be processed, and the film forming the film on the surface of the object to be processed has a subsidy In the seed film forming process, the cut-out recessed portion at the bottom of the recessed portion is further removed, and the auxiliary seed film for the plating layer containing the second metal is formed on the surface of the object to be processed including the inner surface of the recessed portion. [Embodiment] For easy understanding of the present invention, an example of a normal punching process will be described with reference to Figs. Fig. 11 is a state diagram of a state in which a via hole formed in a semiconductor wafer is buried, and Fig. 11(A) is a plan view. Figure 11 (B) is a cross-sectional view taken along line A-A of Figure 11 (A). Figure 1 1 (C) is an oblique view. Figure 12' is a buried engineering drawing of the connecting hole. The semiconductor wafer w is made of, for example, a tantalum substrate, and an insulating layer 4 composed of, for example, copper, a lower wiring layer 2 and a tantalum oxide film is laminated on the surface of the tantalum substrate. A recess 5 is formed on the surface of the insulating layer 4. The recessed portion 5 serves as a wiring groove having a specific width for forming the upper wiring layer, that is, a groove portion (* trench) 6. A communication hole 8 which is a via hole or a through hole which communicates with the insulating layer 4 and the lower wiring layer 2 is formed in a portion of the bottom portion of the groove portion 6. The diameter L1 of the communication hole 8 is extremely small, for example, about 60 to 20 nm, and the recess 5, that is, the width L2 of the groove portion 6 is, for example, about 60 to 1 0 0 nm. 〇-11 - 200824041 To bury the communication hole 8 and the groove portion At 6 o'clock, first, as shown in FIG. 1 : ), a layer 1 made of a metal film is formed on the entire surface of the crystal U including the surface of the groove portion 6 or the communication hole 8 by, for example, plasma sputtering. The adhesion between the lifting and the bottom layer or the prevention of the diffusion or migration of the copper to the insulation. The barrier layer 10 is mainly composed of, for example, a two-layer structure of a film and a Ta film, or a two-layer structure in which Ta films are formed differently depending on film formation conditions. After φ, as shown in Fig. 12(B), plasma etching is performed using a gas such as an inert gas, and the layer 1 formed by the bottom of the communication hole 8 is cut, and the underlying wiring layer 2 is etched to form a specific deep. The recessed portion 1 2 is cut away. Thereafter, as shown in FIG. 12(C), for example, sputtering is performed, and the entire surface of the recessed portion 12, the communication hole 8 or the groove portion 6 is cut out to form an extremely thin plating seed layer 14, wherein The seed layer 14 is a Cu film because the copper plating is performed as follows. After Φ, as shown in Fig. 12(D), the seed layer 14 is used as a starting point for plating, and the material of the upper wiring layer 16 is used to bury the recessed portion 1 2 _ through hole 8 and the groove portion 6, respectively. The material of the upper wiring layer 16 is, for example, copper as described above. As shown in FIG. 1 2 (E), the upper non-metal material is removed by honing treatment or the like, and the upper wiring layer 2 is electrically connected to the upper wiring layer. Further, as described above, there is a via hole at the bottom of the trench portion 6 or The through-holes 8, which have a concave portion 5 whose cross section is formed in a two-stage shape, are referred to as a so-called dual damascene structure. 2 ( ABW barrier layer 4 TaN into: Ar barrier resistance contains the above shape as routine electricity, Lian Ming, and 16 of it. Hole shape -12- 200824041 In the above conventional film formation method, as shown in Figure 1 2 ( In the plasma etching process shown in FIG. 2, the barrier layer particles scattered by etching at a corner portion shown by the point P1 have a characteristic of being directional and scattering in an angular range that converges in a specific direction. When the line width or the groove width is extremely large, there is no significant problem. However, as described above, when the groove width is as small as about 100 nm, the particles scattered in the specific direction adhere to the opposing wall surface to form the deposition protrusions 18. It is possible to produce. As described above, when the deposited protrusions 18 are produced, in the subsequent plasma sputtering process shown in Fig. 12 (C), the directivity of the sputtered particles is high and the shielding becomes the deposition of the protrusions 18. The portion, that is, the phenomenon of shielding (Shad〇wing), causes the problem that the seed layer 14 is difficult to adhere to the shielding portion 20 of the deposition protrusion 18. When the unattached portion of the seed layer 14 is generated, as shown in Fig. 12 (D), creating a void in this part Void) 22, which is not good. Fig. 13 is a view of the concave portion 5 (groove portion 6) of various widths L2. On the surface of the wafer W, as shown in Fig. 13, there are many different types. The recess 5 of the width L2. In this case, even if the aspect ratios of the communicating holes 8 (the diameters L1 are the same) are the same, since the depth ratio of the groove portions 6 is different, the angle from the bottom of the communicating hole 8 to the upper side is 0 1 and 0. 2, as shown in the figure is different (angle 01 < angle 02), so the thickness Η1, H2 of the barrier layer 10 deposited at the bottom of the communication hole 8 of the lowermost layer of the recess is different. The difference of the thickness HI, Η2 will be The depth of the chipped portion 1 2 formed at the bottom of the barrier layer is changed (non-uniform), which is a problem of poor quality. Further, as shown in FIG. 12 (A), a barrier layer is formed. When 1 〇, a portion of the Ta metal of the-13-200824041 is attracted by the bias electric power and is driven into the deeper portion of the Cu underlying wiring layer 2 at the bottom of the communication hole 8, thereby forming a resistance when the recessed portion 1 2 is removed. The reason for the increase in the Ta/Cu mixture causes the connection resistance of the portion to rise. An embodiment of a film forming method, a film forming apparatus, a computer program, and a memory medium according to the present invention is shown in Fig. 1. Fig. 1 is a cross-sectional view showing an example of a film forming apparatus of the present invention, wherein the film forming apparatus is an ICP (Inductively Coupled Plasma) type. The slurry sputtering apparatus is exemplified. As shown in the figure, the film forming apparatus 32 has a processing container 34 formed of a cylindrical body such as aluminum. The processing container 34 is grounded, and an exhaust port 38 is provided at the bottom portion 36. From the throttle valve 40, a vacuum can be drawn by the vacuum relief 42. A disk-shaped mounting table 44 formed of, for example, aluminum or the like is provided in the processing container 34, and an electrostatic chuck 46 is provided on the upper surface of the mounting table 44, and the semiconductor wafer W of the object to be processed can be adsorbed and held by the electrostatic chuck 46. A DC voltage for adsorption (not shown) is applied to the electrostatic chuck 46 as necessary. The mounting table 44 is supported by a post 48 that extends downward from a lower central portion thereof, and a lower portion of the post 48 extends through the container bottom 36. The pillar 48 can be vertically moved by a lifting mechanism (not shown), and the bellows-shaped metal bellows 50, which can be stretched and supported by the lifting platform 44 itself, surrounds the pillar 48, and the upper end of the metal bellows 50 is hermetically joined. Below the mounting table 44, the lower end is hermetically joined to the upper surface of the bottom portion 36, so that the airtightness in the processing container 34 can be maintained, and the lifting and lowering of the mounting table 44 can be tolerated-14-200824041. At the mounting table 44, a refrigerant circulation path 52 is formed to allow the refrigerant to flow, and the wafer W is cooled. The cold medium is supplied/discharged by a flow path (not shown) in the support 48. Further, at the bottom of the container 36, for example, three (only two are shown) support pins 54 are provided in an upright manner, and the pin insertion holes 56 are formed in the mounting table 44 in correspondence with the support pins 54. Therefore, when the mounting table 44 is lowered, the wafer W is received by the upper end portion of the support pin 54 penetrating the pin insertion hole 56, and the wafer W is movable between the wafer W and the transfer arm portion (not shown) that enters from the outside. Therefore, the closable valve 58 is provided on the lower side wall of the processing container 34 to allow the transfer arm portion to enter. The electrostatic chuck 46 provided on the mounting table 44 is connected to a bias power source 62 composed of a high-frequency power source via a wiring 60 for generating a high frequency of, for example, 13.56 MHz, and a specific bias power can be applied to the mounting table 44. Further, the bias power supply 62 can control the bias power of its output as necessary. In the ceiling portion of the processing container 34, a transmissive plate 64 which is transparent to a high frequency, such as a dielectric material such as aluminum nitride, is hermetically provided via a sealing member 66 such as a 0-ring. Outside the transmission plate 64, a plasma generating source 70 is disposed in the processing space 68 in the processing container 34, and the Ar gas, for example, as a plasma gas, can be plasma-generated to generate plasma. As the plasma gas, another inert gas such as He, Ne or the like may be used instead of the Ar gas. Specifically, the plasma generating source 70 has an induction coil portion 72 provided corresponding to the transmission plate 64, and the induction coil portion 72 is connected to a high-frequency power source 74 for generating plasma for example, for example, a transparent plate 74. 64 can be introduced into the processing space 68 at a high frequency. The plasma power outputted by the local frequency power source 74 can also be controlled as necessary -15-200824041. A waveguide plate 76 made of, for example, aluminum which diffuses the introduced high frequency is provided directly below the transmission plate 64. In the lower portion of the waveguide 76, a metal target 78 having an annular shape (a frustoconical shape) whose cross section is inclined inward is provided so as to surround the upper side of the processing space 68, and the variable DC power supply 80 is connected to the metal target 78. Therefore, the DC power outputted from the variable DC power source 80 can be controlled as necessary. The metal target 78 is, for example, a tantalum metal formed in the formation of a Ta film or a TaN film, and copper is used in the formation of the Cu film, and the metal is sputtered into a metal atom or a metal atom group by Ar ions in the plasma. Most of the ions are ionized when passing through the plasma. In the lower portion of the metal target 78, a disk-shaped protective cover 82 made of, for example, aluminum is provided so as to surround the processing space 68. The protective cover 82 is grounded and the lower portion thereof is bent inward and located in the vicinity of the side portion of the mounting table 44. For example, a gas introduction port 84 as a gas introduction means is provided at the bottom of the processing container 44 for introducing a necessary specific gas into the processing container 34. The gas introduction port 84 is supplied with, for example, Ar gas as a plasma gas or other necessary N 2 gas, etc., via a gas control unit 86 composed of a gas flow controller, a valve or the like. Each component of the film forming apparatus 3 2 is controlled by being connected to a device control unit 88 constituted by, for example, a computer. Specifically, the device control unit 88 controls operations of the bias power source 62, the plasma generating high-frequency power source 74, the variable DC power source 8A, the gas control unit 86, the throttle valve 40, and the vacuum remedy 42. The operation at the time of forming a film such as a metal film is as follows. First, under the control of the device control unit 88, the vacuum assisting 42 is actuated to evacuate the inside of the processing container 44, and the operating gas control unit 86 is simultaneously introduced into the Ar gas, and the throttle valve 40 is controlled to be in the processing container 4 4 . The specific vacuum degree is maintained, and then DC power is applied to the metal target 78 via the variable DC power source 80, and high frequency power (plasma power) is applied to the induction coil unit 72 via the high frequency power source 74. Further, the device control unit 88 also issues a command to the bias power source 62 to apply a specific bias power to the mounting table 44, and is applied to the metal target 78 and the induction coil unit in the processing container 34 thus controlled. The power of 72 forms Ar plasma, which generates Ar ions, and the ions collide with the metal target 78 to cause the metal target 78 to be sputtered to emit metal particles. Moreover, most of the metal particles (metal atoms, metal radicals) from the sputtered metal target 78 are ionized when passing through the plasma, wherein the metal particles become ionized metal ions and electrically neutral neutral metals. The state in which the atoms are mixed is scattered downward. Among them, in particular, the metal ions are attracted by the bias electric power applied from the stage 44, and the metal ions having high directivity to the wafer W are deposited on the wafer W on the mounting table 44. As will be described later, the device control unit 88 issues, for example, a command to output a large output to the bias power source 62, and Ar ions in the plasma can also be attracted to the mounting table 44 side, thereby simultaneously achieving film formation and sputtering contact. Engraved on both sides. The control of each component of the apparatus is controlled by the device control unit 88 in accordance with a program that can be formed by film formation of a metal film under specific conditions. At this time, for example, in the FD (floppy disk) or CD (disc), the memory medium 90 such as a flash memory stores a program including control commands for the respective components, and the components are controlled by the program to perform processing under specific conditions. -17- 200824041 A film forming method of the present invention which is carried out using the film forming apparatus 32 having the above configuration will be described below. Figure 2 is a plot of the angular dependence of the uranium engraving. Fig. 3 is a distribution diagram of the relationship between the bias power and the amount of film formation on the wafer. Fig. 4 is a flow chart for explaining the first embodiment of the film forming method of the present invention. First, in the first aspect of the method of the present invention, in a specific process in a series of film formation processes, when a film such as a metal film is formed by plasma sputtering, a bias voltage, a direct current power, and a power are controlled. Plasma power, etc. become an appropriate size. In this case, the film formation caused by the attraction of the metal ions and the sputtering of the plasma gas (Ar ions) are simultaneously generated, and the bottom portion of the lowermost layer of the concave portion is set to be cut off to form a semiconductor wafer. The bottom of the lowermost layer of the recess is cut away to form a chipped portion, and a metal film can be deposited on the surface. Specifically, the bias power at this time is set to the film formation rate and plasma gas (Ar+) generated by the attraction of the metal ions to the opposite surface of the metal target 78, that is, the wafer W of FIG. The resulting etch rate of the sputter etch becomes a roughly balanced size. According to a second feature of the method of the present invention, when a metal film is formed by film formation by plasma sputtering, in particular, the pressure (process pressure) in the processing container is set to be much larger than a conventional method, and the amount of ions is compared. It can produce a larger amount of metal particles than a neutral metal atom, thereby making neutral metal atoms dominant on the surface or sidewall portion of the wafer, and actively depositing a metal film. Further, metal ions or gas ions attracted to the depth portion are favored by the bias electric power at the bottom of the deep depressed portion, and the bottom portion such as the Ta/Cu mixed layer can be further removed. -18- 200824041 The following is a more detailed description. First, when the characteristics of the uranium engraving rate of the arsenic engraved plasma caused by the plasma gas are not considered in consideration of the film formation amount, the relationship between the angle of the sputter surface and the etching rate is as shown in the distribution diagram of Fig. 2, in which the splash The angle of the plating surface refers to the angle at which the normal line of the sputtering surface becomes the direction of incidence of the sputtering gas (Ar ion: Ar+) (the downward direction in the drawing), for example, the upper surface of the wafer W and the concave portion 5 (refer to FIG. The bottom of the recess is 〃 〇 〃, and the side wall of the recess is 〃 90 degrees 〃. As can be seen from the map, the upper surface of the wafer (the angle of the sputtered surface = 0 degrees) is somewhat etched by uranium, but the sidewall of the recess (the angle of the sputtered surface = 90 degrees) is hardly etched by uranium. Further, the corner portion of the opening of the recess (the angle of the sputter surface = 40 to 80 degrees) is strongly sputter-etched. Further, in the film forming apparatus comprising the ICP type sputtering apparatus shown in Fig. 1, the relationship between the bias electric power applied to the wafer W side and the deposition amount of the wafer upper surface (non-recessed side wall) is as shown in Fig. 3. That is, in the case of a certain plasma power and a certain direct current power applied to the metal target 78, when the bias power is not too large, a high film formation amount can be obtained by the attraction of the metal ions and the neutral metal atom. However, as the bias power increases, the tendency of the plasma gas (Ar ion) to be accelerated by the biased electric power on the wafer surface becomes stronger (refer to FIG. 2). As a result, the deliberately deposited metal film is etched away. Of course, the etching becomes stronger as the bias power becomes larger. Therefore, when the film formation rate caused by the attracted metal ions and the neutral metal atoms is the same as the sputtering rate caused by the ions of the plasma gas, the film formation and the etching cancel each other, and the wafer is formed on the wafer. The film amount becomes 〇, and the condition at this time corresponds to the point X1 (bias power: 350 W) of FIG. Further, the bias voltage of Fig. 3 is -19-200824041. The power or film formation amount is only an example. By controlling the plasma power and the direct current power, the above characteristic curve can be changed as shown by a dotted line in Fig. 3. Conventional operating conditions of such a sputtering apparatus are a part of the region A1, and the bias electric power is set to a region where the amount of film formation (film formation rate) is not too large. That is, it is almost the same as when the bias voltage is 0 (the engraving caused by the plasma which does not generate an inert gas), and the metal ions to be attracted become the largest region, and there is also a certain degree of film formation at the bottom of the concave portion. . Phase φ For this reason, the present invention is mainly carried out in a region where filming by attracted metal ions and neutral metal atoms occurs simultaneously with sputtering etching by plasma gas. More specifically, as described above, on the wafer W, the deposition rate caused by the attracted metal ions and neutral metal atoms, and the etching rate caused by the plasma gas are roughly balanced. Area A2 is performed. The term "major equilibrium" means not only the case where the film formation amount on the wafer W is "0", but also the film formation amount which is about 3/10 of the film thickness of the area A1. . φ To understand the above phenomenon, the method of the present invention will be described. First, in Fig. 1, when the mounting table 44 is lowered to the lower state, the wafer W is carried into the vacuum-processable processing container 34 via the gate valve 58 of the processing container 34 to be supported by the support pin 54. In this state, the load 44 is placed on the wafer 44, and the wafer W is adsorbed and held on the mounting table 44 by the electrostatic chuck 46. After the wafer W is placed, adsorbed, and held on the mounting table 44, film formation processing is started. At this time, on the upper surface of the wafer W, the concave portion 5 having the same structure as that shown in Fig. 11 (B) (see Fig. 4(A)) is previously borrowed by the former -20-200824041 before the loading. The film is made of a gas (B-shaped electricity is a beam; that is, a domain is formed. That is, an insulating layer 4 is formed on the lower wiring layer 2 made of Cu of the lower layer, and the concave portion 5 is formed in the insulating layer 4. The concave portion 5 is formed of a groove-shaped groove portion 6 (see FIG. 1 1 (A)), and can reach the communication hole 8 of the guide hole or the through hole of the wiring layer 2 in the bottom shape, and the entire concave portion has a stepped shape of two stages.

使用第1金屬之鉅作爲金屬靶7 8，對處理容器3 4 進行吸成真空成爲特定壓力後，對電漿產生源70之感 線圈部72施加電漿電力，且由偏壓電源62對載置台 之靜電夾頭46施加特定之偏壓電力。又，於金屬靶78 由可變直流電源80施加特定之直流電力進行成膜。首 ，如圖4 ( B )所示，作爲阻障層形成工程之一部分進 形成底層膜1 0 A之底層膜形成步驟。其中，爲形成底層 1 0A之TaN膜、亦即第1金屬之氮化膜，而由氣體導入 84，除例如作爲電漿激發氣體之Ar氣體以外，將氮化 體之N 2氣體供給至處理容器3 4內。如此則，如圖4 )所示，不僅於晶圓上面，於凹部5內之側壁或底面亦 成大略均勻之作爲底層膜10A的TaN膜。此時之偏壓 力爲圖3之區域A1，和習知成膜條件相同，具體言之 約1〇〇瓦特。 如上述說明，作爲底層膜10A的TaN膜之形成結 後，進行主阻障膜形成步驟而形成第1金屬之單體構成 作爲主阻障膜1 0B的Ta膜，如此而形成阻障層1 0。亦 ’於該主阻障膜形成步驟，增加偏壓電力設爲圖3之區 A2。於該第〗實施形態中，該主阻障膜形成步驟，可由 -21 - 200824041 在凹部5以外之晶圓W之表面，以上述金屬粒子引起之 成膜量和惰性氣體之電漿引起之蝕刻量實質上成爲相同而 被條件設定的第1步驟；及在凹部5以外之晶圓W之表 面，以上述金屬粒子引起之成膜量相較於惰性氣體之電漿 引起之飩刻量僅稍微變大而被條件設定的第2步驟構成， 或僅由第2步驟構成亦可。 例如由第1及第2步驟構成時，於第1步驟，欲設定 晶圓W之上面之成膜量爲“0 “時將偏壓電力設爲圖3之 點XI，此時之偏壓電力，具體言之爲35 0W (瓦特）。又 ，此時係停止由氣體導入口 84之N 2氣體之供給，僅供 給Ar氣體。如此則，如圖4 ( C )所示，凹部5之最下層 (相當於連通孔8 )之底部被削去，Cu構成之配線層2之 上面側被削去，而形成削去凹陷部1 2。 上述之所以幾乎未形成膜之理由說明如下。亦即，如 上述說明，藉由設定偏壓電力之大小爲圖3之區域A2, 詳言之爲點X1，如此則，於晶圓W上面被吸引之金屬離 子及中性金屬原子引起之成膜速率，和電漿氣體（Ar+ ) 引起之濺鍍蝕刻之鈾刻速率成爲大略均衡，結果，金屬膜 之成膜量大略成爲“ 0 “，相對於此，關於凹部5之連通 孔8之底部，蝕刻速率相對於成膜速率變爲較大，結果， 連通孔8之底部被削去。關於上述事項針對晶圓單位面積 以原子位準表示如下。 (晶圓上面） 22- 200824041 Σ Ta+ Σ Ta +二 Σ Ar + (連通孔8之底部） Σ Ta+ < Σ Ar + 其中，Ta表示中性金屬原子，Ta +表示金屬離子，彼 等均有助於金屬膜之成膜。相對於此，Ar+表示Ar離子， 有助於蝕刻。於晶圓上面，Ta及Ta+均可有效到達，A, 亦有效到達，結果成膜量成爲“ 〇 “。 相對於此，於連通孔8之底部，孔徑極爲小之故，指 向性高之Ta+及Ar+雖可到達，指向性差之中性金屬原子 之Ta難以到達，結果，有助於金屬膜之成膜之Ta難以到 達的範圍部分內，連通孔8之底部被削去。此時之削去量 可藉由控制第1步驟之處理時間而控制。又，其中爲簡單 說明而假設，成膜之Ta、Ta+之1個分，分別藉由Ar+Ι個 之撞及而由成膜面飛出（被飩刻）。 第1步驟結束後，進行第2步驟。於第2步驟，設定 偏壓電力之大小爲區域A2之點X1以外之點，例如設定 爲區域A3，形成和區域A 1之成膜速率比較遠較少的些微 厚度之金屬膜。結果，在除去連通孔8之底部以外的晶圓 W之表面全體，亦即，在凹部5內之表面或連通孔8之側 面形成作爲主阻障膜1 〇的Ta膜。此情況下，如上述說明 之理由，連通孔8之底部因飩刻速率大於成膜速率之故， Ta膜未能附著而更被削去。因此，削去凹陷部1 2之凹陷 -23- 200824041 形狀變爲更大。亦即，於晶圓上面成爲“ Σ Ta+ Σ Ta + > Σ Ar “，於連通孔8之底部成爲“ Σ Ta+ < Σ Ar+。又，此 情況下，底部之蝕刻速率，係以晶圓W上面僅些微沈積 膜的方式，在設定有助於成膜之金屬粒子多於濺鍍離子的 範圍內，較上述第1步驟之情況僅稍微變小。 如上述說明’於上述第1步驟，晶圓 w之表面之成 膜量與濺鍍鈾刻量吻合，因此於圖4 ( C )之製程結束後 圖4(B)之底層膜10A之厚度不變。因此作爲底層膜 1 0 A，不受削去凹陷部1 2之孔深度影響，其厚度可設爲， 於晶圓W之表面例如爲3 · 5nm，於連通孔8之底部例如爲 l.Onm，設爲l〇nm以下較好，更好是設爲5nm以下之極 薄。 另外，於習知技術之成膜方法，於圖1 2 ( A )所示， 阻障層1 0之厚度受削去凹陷部1 2之孔深度影響而變，其 深度設爲約50nm時，於晶圓W之表面需要約60nm。此 乃因爲於圖12 ( B )所示Αι:蝕刻製程中，晶圓W之表面 亦同時被蝕刻。於晶圓W之表面被形成60nm之底層膜時 ，於連通孔底部無可避免會被形成約l〇nm〜20nm之相當 厚之阻障層，此於飩刻製程（圖12 ( B ))初期，表示削 去凹陷部未被形成，僅阻障層被飩刻。 本發明中藉由上述第1步驟、第2步驟，設定條件使 晶圓W之表面之成膜量大略成爲0，因此如圖12(B)所 示於凹部之側面不會產生沈積突起物1 8。另外，形成之削 去凹陷部1 2之深度，因爲連通孔8之底部之底層膜極薄 -24- 200824041 ，而不受凹部之寬度L2 (參照圖1 3 )影響，可於晶圓W 面內設爲大略均勻。 其中理想情況爲，如上述說明，於連通孔8之底部（ 削去凹陷部12之凹部）不附著Ta膜，但實際上，於上述 第1步驟、第2步驟，於底部無可避免會附著些微Ta膜 (主阻障膜）。亦即，圖5爲主阻障膜之成膜時（參照圖 4 ( D ))之連通孔底部（削去凹陷部12之底部）之一部 分擴大圖，附著於連通孔5之側壁的主阻障膜（Ta膜） 10B之厚度H1雖厚，其底部亦僅爲些微之厚度H2,但附 著主阻障膜10B。其厚度H2約爲例如Inm。 更不好的是，於該底部附近Ta +離子被偏壓電力被吸 引而使Ta +離子植入Cu配線層2中，於此將形成成爲電 阻上升原因之Ta/Cu混合層100。結果，於該狀態下，形 成Cu薄膜，再度施予銅鍍層時，將受到Ta/Cu混合層 100或厚度H2之Ta膜構成之主阻障膜10B之影響，於該 部分產生連接電阻上升之不良情況。 上述說明進行第1、第2步驟雙方，但於第1步驟， 係於晶圓表面或凹部5或連通孔8之側壁等亦沈積些微 Ta膜、形成TaN/Ta主阻障膜，因此僅進行第1、第2步 驟中之一方亦可。此情況下，亦不會產生上述Ta/Cu混合 層100或厚度H2之Ta膜引起之電阻上升問題。 本發明中，爲除去上述厚度H2之Ta膜或Ta/Cu混合 層1 〇〇之問題，而於以下進行之補助種膜形成工程中除去 上述厚度H2之Ta膜或Ta/Cu混合層100。 -25- 200824041 亦即，如上述說明，形成TaN膜與Ta膜之積層構造 構成之阻障層1 〇的阻障層形成工程結束後，移至本發明 特徵之補助種膜形成工程。 首先，將晶圓W搬入金屬靶78非以鉅而以銅形成之 和如圖1所示構成相同構成之成膜裝置內，如圖4(E) 所示，更進一步削去上述削去凹陷部1 2之底部，而於包 含凹部5內或8內之表面的晶圓W表面形成含有第2金 屬之薄膜構成的鍍層用補助種膜14A。其中使用Cu作爲 第2金屬，補助種膜14A由Cu膜構成。在形成Cu膜構 成之補助種膜1 4 A時，設定之製程條件爲，更進一步植入 上述削去凹陷部1 2之底部而予以削去之同時，在包含晶 圓W上面側以及該凹部5或連通孔8之側面亦分別沈積 Cu膜，而且不會對凹部5內之段部之角部102有不良影 響的條件。 此種製程條件，例如於習知方法進行電漿濺鍍形成 Cu膜時，係設定製程壓力爲例如約5ηιΤογτ，但本發明之 成膜方法時，係設定製程壓力爲相當高、例如設爲 30〜90mT〇]rr之範圍內。又，偏壓電力設定爲例如1〇〇〜250 瓦特0.32W/cm2〜0.8W/cm2)之範圍內。 另外，設定電槳產生源70之電漿形成用電力、亦即 高頻電源74之電力爲0.5〜2千瓦特之範圍內。 如上述說明，特別是藉由設定製程壓力爲上述範圍’ 而提升電漿濃度之同時，於晶圓W上面側，和飩刻因子 之Cu +離子與Ar+離子之合計離子比較，產生更多量之主 -26- 200824041 要成爲膜附著因子之Cu之中性金屬原子’依此而使中性 金屬原子成爲優勢狀態，而且於連通孔8之深部分使銅之 中性金屬原子幾乎不存在，使被偏壓電力引入之Cu+離子 或Ar +離子多於中性金屬原子，而彼等離子成爲優勢狀態 〇 結果，如上述說明，更進一步使上述削去凹陷部12 之底部朝下方被削去之同時，在其以外之表面可沈積薄 Cu膜構成之補助種膜14A。如上述說明，削去凹陷部12 之凹部更被削去，位於該處之Ta/Cu混合層100可被削去 、除去。此種補助種膜形成工程之處理，除製程壓力不同 之點以外，使用圖3中之例如區域A2。又，和Ta比較， Cu和Cu +離子之附著力較低，因此於偏壓電力之區域A2 (參照圖3 ) ，Cu +離子對沈積之Cu膜發揮作爲蝕刻因子 之功能。 補助種膜形成工程結束後，移至本質種膜形成工程， 其中設定偏壓電力爲圖3中之區域A1，設爲和習知方法 同樣條件，如圖4 ( F )所示，不僅於晶圓W上面，於凹 部5內之側壁極底部亦形成薄的Cu膜構成之本質種層 14B，藉由補助種膜14A與本質種膜14B之積層構造而形 成種層1 4。 又，上述安裝有銅之金屬靶的成膜裝置，可介由對上 述安裝有鉅之金屬靶的成膜裝置抽成真空的傳送腔室連結 ，使晶圓 W不會曝曬於大氣，而於真空環境中在兩成膜 裝置中互相搬送。 -27- 200824041 形成種層14之後由成膜裝置取出晶圓W對其進行通 常之鍍層處理而進行鍍層工程，如圖4 ( G )所示，於凹 部5內完全塡埋由銅構成之配線層16之材料。 如圖4(H)所示，藉由硏磨除去晶圓上面不要部分 ，完成上層配線層16之形成。 於上述實施形態中，藉由適當選擇阻障層1 0或補助 種膜1 4A等之成膜時之製程條件，則可以選擇性僅削去凹 部5之最下層底部之同時，在包含凹部5內之表面的晶圓 表面全體區域形成薄膜。而且不受凹部5之寬度影響，可 以削去同一深度範圍之底部、形成同一深度之削去凹陷部 12，另外，可以除去成爲削去凹陷部12之底部之電阻上 升原因之例如Ta/Cu混合層1 00，而於凹部5側面或上面 形成薄膜。 上述阻障層形成工程（第1、第2步驟）之設定條件 、亦即可實現圖3中之區域A2內之設定條件如下：When the processing container 34 is vacuumed to a specific pressure using the giant metal of the first metal, the plasma is applied to the sensitive coil portion 72 of the plasma generating source 70, and is biased by the bias power source 62. The electrostatic chuck 46 placed is biased to apply a specific bias voltage. Further, a specific DC power is applied to the metal target 78 by the variable DC power source 80 to form a film. First, as shown in Fig. 4(B), as a part of the barrier layer forming process, an underlayer film forming step of forming the underlying film 10A is carried out. In order to form the TaN film of the underlayer 10A, that is, the nitride film of the first metal, the gas is introduced 84, and the N 2 gas of the nitride is supplied to the treatment except for, for example, the Ar gas as the plasma excitation gas. Inside the container 3 4 . Thus, as shown in Fig. 4), not only the upper surface of the wafer but also the side wall or the bottom surface in the recess 5 is substantially uniform as the TaN film of the underlying film 10A. The biasing force at this time is the area A1 of Fig. 3, which is the same as the conventional film forming condition, specifically, about 1 watt. As described above, after the formation of the TaN film of the underlayer film 10A, the main barrier film forming step is performed to form a single metal of the first metal to form a Ta film as the main barrier film 10B, thereby forming the barrier layer 1 0. Also in the main barrier film forming step, the bias power is increased to be the area A2 of Fig. 3. In the first embodiment, the main barrier film forming step may be performed by etching the film forming amount and the plasma of the inert gas caused by the metal particles on the surface of the wafer W other than the recess 5 from -2 to 200824041. The first step of setting the condition substantially the same, and the surface of the wafer W other than the concave portion 5, the amount of film formation by the metal particles is slightly smaller than the amount of plasma caused by the inert gas. It may be configured to be larger in the second step and set as the condition, or may be constituted only in the second step. For example, when the first step and the second step are used, in the first step, when the film formation amount on the upper surface of the wafer W is set to "0", the bias power is set to point XI in FIG. Specifically, it is 35 0W (watt). Further, at this time, the supply of the N 2 gas from the gas introduction port 84 is stopped, and only the Ar gas is supplied. Thus, as shown in FIG. 4(C), the bottom of the lowermost layer (corresponding to the communication hole 8) of the recess 5 is cut off, and the upper side of the wiring layer 2 made of Cu is cut off to form the cut recess 1 2. The reason why the film is hardly formed as described above is explained below. That is, as described above, by setting the magnitude of the bias power to be the region A2 of FIG. 3, in detail, the point X1, so that the metal ions and the neutral metal atoms attracted on the wafer W are caused by the formation. The film rate and the uranium engraving rate of the sputter etching caused by the plasma gas (Ar+) are roughly equalized, and as a result, the film formation amount of the metal film is roughly "0", whereas the bottom of the communication hole 8 with respect to the recess 5 is formed. The etching rate becomes larger with respect to the film formation rate, and as a result, the bottom of the communication hole 8 is cut. Regarding the above matters, the unit area of the wafer is expressed by the atomic level as follows. (on the wafer) 22- 200824041 Σ Ta+ Σ Ta + Σ Ar + (bottom of the communication hole 8) Σ Ta+ < Σ Ar + where Ta represents a neutral metal atom, Ta + represents a metal ion, and they have Helps film formation of metal films. On the other hand, Ar+ represents Ar ions and contributes to etching. On the wafer, both Ta and Ta+ can be effectively reached, and A is also effectively reached. As a result, the film formation becomes "〇". On the other hand, at the bottom of the communication hole 8, since the aperture is extremely small, Ta+ and Ar+ having high directivity are reachable, and Ta having poor directivity is difficult to reach. As a result, it contributes to film formation of the metal film. In the portion of the range where the Ta is difficult to reach, the bottom of the communication hole 8 is cut off. The amount of shaving at this time can be controlled by controlling the processing time of the first step. Further, for the sake of simplicity, it is assumed that one of Ta and Ta+ of the film formation is caused to fly out of the film formation surface by being rubbed by Ar+. After the completion of the first step, the second step is performed. In the second step, the magnitude of the bias power is set to a point other than the point X1 of the area A2, for example, the area A3, and a metal film having a slight thickness which is much smaller than the film formation rate of the area A1 is formed. As a result, the entire surface of the wafer W other than the bottom portion of the communication hole 8 is removed, that is, a Ta film as the main barrier film 1 is formed on the surface of the concave portion 5 or the side surface of the communication hole 8. In this case, for the reason of the above description, since the bottom of the communication hole 8 is larger than the film formation rate because of the engraving rate, the Ta film is not attached and is further removed. Therefore, the shape of the recessed portion -23-200824041 in which the depressed portion 12 is cut is made larger. That is, on the wafer, it becomes "Σ Ta+ Σ Ta + > Σ Ar", and becomes "Σ Ta+ < Σ Ar+ at the bottom of the communication hole 8. Further, in this case, the etching rate of the bottom is performed by the wafer. The method of depositing only a few micro-deposited films on W is only slightly smaller than the case of the above-described first step in the range in which the metal particles contributing to film formation are more than the sputter ions. As described above, in the first step described above, The film formation amount of the surface of the wafer w coincides with the sputtering uranium engraving amount, so the thickness of the underlying film 10A of FIG. 4(B) after the end of the process of FIG. 4(C) is unchanged. Therefore, as the underlying film 10A, It is not affected by the depth of the hole of the recessed portion 12, and the thickness thereof may be, for example, 3 · 5 nm on the surface of the wafer W, for example, l. Onm at the bottom of the communication hole 8, and is set to be less than 10 nm. Preferably, it is set to be extremely thinner than 5 nm. In addition, in the film forming method of the prior art, as shown in Fig. 12 (A), the thickness of the barrier layer 10 is cut by the hole of the depressed portion 12 The depth is changed, and when the depth is set to about 50 nm, about 60 nm is required on the surface of the wafer W. This is because the etching process is as shown in Fig. 12 (B) The surface of the wafer W is also etched at the same time. When a 60 nm underlying film is formed on the surface of the wafer W, a relatively thick barrier layer of about 10 nm to 20 nm is inevitably formed at the bottom of the via hole. In the initial stage of the etching process (Fig. 12(B)), it is indicated that the chipped portion is not formed, and only the barrier layer is etched. In the present invention, the wafer is set by the first step and the second step. The film formation amount of the surface of W is substantially 0, so that the deposition protrusions 18 are not generated on the side surface of the concave portion as shown in Fig. 12(B). Further, the depth of the depressed portion 12 is formed by the cut because the communication hole 8 The bottom film of the bottom layer is extremely thin -24-200824041, and is not affected by the width L2 of the recess (refer to FIG. 13), and can be set to be substantially uniform in the plane of the wafer W. Ideally, as described above, in the connection The bottom of the hole 8 (the recessed portion of the recessed portion 12 is not removed) does not adhere to the Ta film, but actually, in the first step and the second step, some micro-Ta film (main barrier film) is inevitably attached to the bottom portion. That is, FIG. 5 is the bottom of the communication hole at the time of film formation of the main barrier film (refer to FIG. 4 (D)) (the depressed portion 12 is removed) The bottom portion of the bottom portion is enlarged, and the thickness H1 of the main barrier film (Ta film) 10B attached to the side wall of the communication hole 5 is thick, and the bottom portion thereof is only a small thickness H2, but the main barrier film 10B is attached. The thickness H2 is approximately, for example, Inm. Further, in the vicinity of the bottom portion, Ta + ions are attracted by the bias power, and Ta + ions are implanted into the Cu wiring layer 2, thereby forming Ta/ which is a cause of resistance rise. Cu mixed layer 100. As a result, in this state, a Cu thin film is formed, and when a copper plating layer is applied again, the main barrier film 10B composed of the Ta/Cu mixed layer 100 or the Ta film of thickness H2 is affected, and the portion is affected. A problem arises in which the connection resistance rises. In the first step, both the first step and the second step are performed. However, in the first step, a micro-Ta film is formed on the surface of the wafer or the recess 5 or the side wall of the communication hole 8 to form a TaN/Ta main barrier film. One of the first and second steps is also possible. In this case as well, the problem of resistance rise caused by the Ta/Cu mixed layer 100 or the Ta film of the thickness H2 does not occur. In the present invention, in order to remove the above-mentioned problem of the Ta film or the Ta/Cu mixed layer 1 of the thickness H2, the Ta film or the Ta/Cu mixed layer 100 having the thickness H2 is removed in the auxiliary seed film formation process described below. In the above, as described above, after the formation of the barrier layer forming the barrier layer 1 of the TaN film and the Ta film, the barrier layer formation process is completed, and the film formation process of the present invention is carried out. First, the wafer W is carried into the film forming apparatus in which the metal target 78 is not formed in a large size and formed of copper and has the same configuration as shown in FIG. 1. As shown in FIG. 4(E), the above-described shaving recess is further removed. At the bottom of the portion 1 2, a plating seed film 14A made of a film containing a second metal is formed on the surface of the wafer W including the surface in the concave portion 5 or the inside of the film. Among them, Cu is used as the second metal, and the seed film 14A is made of a Cu film. When the auxiliary seed film 1 4 A composed of the Cu film is formed, the process conditions are set such that the bottom portion of the recessed portion 1 2 is further implanted and cut, and the upper surface of the wafer W and the concave portion are included. 5 or the side surface of the communication hole 8 is also deposited with a Cu film, and does not adversely affect the corner portion 102 of the segment in the recess 5. Such a process condition, for example, when a conventional method is used to form a Cu film by plasma sputtering, the process pressure is set to, for example, about 5 ηι Τ γ τ. However, in the film formation method of the present invention, the process pressure is set to be relatively high, for example, 30. ~90mT〇]rr within the range. Further, the bias power is set to be, for example, in the range of 1 〇〇 to 250 watts 0.32 W/cm 2 to 0.8 W/cm 2 ). Further, the electric power for forming plasma of the electric blade generating source 70, that is, the electric power of the high-frequency power source 74 is set to be in the range of 0.5 to 2 kW. As described above, in particular, by setting the process pressure to the above range and increasing the plasma concentration, the amount of Cu + ions and the total ions of the Ar+ ions is larger on the upper side of the wafer W than the engraving factor. The main -26- 200824041 Cu neutral metal atom to be a film adhesion factor', thereby making the neutral metal atom a dominant state, and the copper neutral metal atom is hardly present in the deep portion of the communication hole 8. The Cu+ ions or Ar+ ions introduced by the biased electric power are more than the neutral metal atoms, and the ions become the dominant state. As described above, the bottom of the above-described shaved recess 12 is further cut downward. At the same time, a seed film 14A composed of a thin Cu film may be deposited on the surface other than the surface. As described above, the recessed portion of the recessed portion 12 is further removed, and the Ta/Cu mixed layer 100 located there can be removed and removed. For the treatment of such a seed film formation process, for example, the area A2 in Fig. 3 is used except for the difference in process pressure. Further, since the adhesion between Cu and Cu + ions is lower than that of Ta, the Cu + ions collide with the deposited Cu film as an etching factor in the region A2 of the bias power (see Fig. 3). After the completion of the film formation process, the process proceeds to the intrinsic seed film formation process, in which the bias power is set to the area A1 in FIG. 3, and the conditions are the same as those of the conventional method, as shown in FIG. 4(F), not only in the crystal On the upper surface of the circle W, an essential seed layer 14B made of a thin Cu film is formed on the bottom of the side wall of the concave portion 5, and the seed layer 14 is formed by the laminated structure of the seed film 14A and the essential seed film 14B. Further, the film forming apparatus to which the metal target of copper is mounted can be connected to the transfer chamber in which the film forming apparatus to which the giant metal target is attached is vacuumed, so that the wafer W is not exposed to the atmosphere. They are transported to each other in a two film forming apparatus in a vacuum environment. -27- 200824041 After the seed layer 14 is formed, the wafer is taken out by the film forming apparatus, and the plating process is performed by a normal plating process. As shown in FIG. 4(G), the wiring made of copper is completely buried in the recess 5. The material of layer 16. As shown in Fig. 4(H), the upper wiring layer 16 is formed by honing to remove unnecessary portions of the wafer. In the above embodiment, by appropriately selecting the process conditions at the time of film formation such as the barrier layer 10 or the auxiliary seed film 14A, it is possible to selectively remove only the bottom portion of the lowermost layer of the concave portion 5, and include the concave portion 5 The entire surface of the wafer surface on the inner surface forms a thin film. Further, without being affected by the width of the concave portion 5, the bottom portion of the same depth range can be cut, and the shaved portion 12 having the same depth can be formed. Further, for example, Ta/Cu mixing which is the cause of the rise in the bottom portion of the cut recess portion 12 can be removed. The layer 100 is formed on the side or above the recess 5 to form a film. The setting conditions of the barrier layer forming process (first and second steps) and the setting conditions in the region A2 in Fig. 3 can be realized as follows:

電漿電力：500〜6000WPlasma power: 500~6000W

直流電力：100〜1 2000WDC power: 100~1 2000W

偏壓電力：100〜2000W 如上述說明，藉由適當選擇上述3個條件，可於區域 A2內設定動作點。此時若於區域A2以外之部分設定動作 點，則未能充分形成削去凹陷部1 2，亦即無法形成所謂沖 孔構造。 seem 又，其他製程條件爲，Ar氣體流量設爲約50〜1〇〇〇 範圍內、製程壓力設爲約 O.OOlTorr -28- 200824041 (O.lPa)〜0.1Torr(13.3Pa)範圍內。 又，於上述阻障層形成工程說明形成TaN膜作爲底層 膜1 0 A之例，但亦可改爲形成Ta膜作爲底層膜〗〇 a。此 情況下，於底層膜10A之Ta膜上形成Ta膜10B，藉由成 膜條件不同之Ta膜彼此之2層構造形成阻障層〗〇。 以下針對本發明之成膜方法及習知方法形成之削去凹 陷部1 2進行評估結果發現，習知方法形成時於凹部5之 上端開口部被形成沈積突起物而較爲不好，相對於此，依 本發明之成膜方法形成時不會產生沈積突起物，可於良好 狀態下形成削去凹陷部1 2。 以下針對凹部5之底部被形成之削去凹陷部丨2之深 寬比之依存性進行評估，說明評估結果。 圖6爲凹部之深寬比與底部之銅蝕刻量間之關係之分 布圖。其中凹部並非2階段之段部形狀而是使用以i段之 凹部形成者。圖6之特性A表示習知方法，特性B表示本 發明之成膜方法。 具體言之爲，於習知方法，針對具有各種深寬比之凹 部，於晶圓表面進行電漿濺鍍形成大略60nm之阻障層， 之後施予特定時間之Ar蝕刻。測定此時形成之削去凹陷 部12之深度，設爲銅之蝕刻速率。另外，於本發明之成 膜方法，針對具有各種深寬比之凹部，於晶圓表面進行電 漿濺鍍形成大略4nm之底層膜，之後和上述習知方法同樣 於特定時間範圍內進行第1步驟。測定此時形成之削去凹 陷部1 2之深度，設爲銅之蝕刻速率。 -29- 200824041 由圖6可知，於特性A、B之任一情況下，和深寬比 大之情況比較，深寬比小時凹部底部之成膜量增加，因此 銅之蝕刻速率減少。另外，特性A之習知方法中，隨深寬 比之增加，銅之蝕刻速率會變化，因此意味著深寬比之差 異使削去凹陷部1 2之深度變化而較爲不好。相對於此， 特性B之本發明之成膜方法中，深寬比爲2以下時銅之飩 刻速率雖大幅變化，但深寬比爲2以上時銅之蝕刻速率成 爲大略一定。 通常之凹部5，深寬比大多爲2以上，因此依據本發 明之成膜方法可以確認，不受深寬比影響，可使削去凹陷 部1 2之深度大略保持均一，可獲得良好結果。如上述說 明’削去凹陷部12之深度不受凹部5之形狀影響，因此 不受凹部之寬度影響，可以經常形成同一深度之削去凹陷 部。 以下針對如圖4 ( E )所示補助種膜形成工程之製程 條件進行評估。 首先，於圖4 ( D )所示工程，欲除去削去凹陷部12 之底部產生之厚度H2之Ta膜10B或電阻大的Ta/Cu混 合層100時，通常考慮於較低製程壓力、例如約5mT〇rr 壓力下進行Ar氣體之電漿濺鍍而除去上述Ta/Cu混合層 1 00等。但是，此情況下，雖可除去上述削去凹陷部1 2之 厚度H2之Ta膜10B或Ta/Cu混合層100，但與此同時， 對晶圓表面全體、特別是凹部5之段部之角部1 02 (參照 圖4(C))會因爲進行Ar氣體之電漿濺鍍而帶來較大損 -30- 200824041 傷，較爲不好。 因此，本發明中使用圖3中之區域A2，使用金 更進一步使削去凹陷部12之底部朝下方被削去而 Ta/Cu混合層100之同時，在其他之晶圓面雖僅沈積 金屬膜，而於次一工程使附著Cu膜構成之本質種膜 (參照圖4(F))，其中金屬靶使用和該本質種膜 相同材料之Cu，如此則可以沈積由Cu膜構成之補助 14A。 另外，使用Cu金屬靶沈積補助種膜14A之同時 進一步使削去凹陷部1 2被削去時，如上述說明，設 低製程壓力時，原子或離子之平均自由工程變大，會 對晶圓表面之衝及次數而增加損傷。因此，設定某一 較高之製程壓力，具體言之爲，本發明中設定製程壓 30〜90mT〇rr範圍內，如此則，可抑制離子引起之對 表面之損傷之同時，可沈積金屬膜，與此同時，削去 部1 2之底部可以削去更深。 圖7爲此時之狀況之一部分，表示製程壓力低時 時之Cu金屬粒子之動向模式圖，表示於凹部藉由使 圖1所示高頻之成膜裝置’以Cu金屬靶進行濺鍍之 ，圖7 ( A)表示製程壓力低時、例如5mTorr (習知 )，圖7 (B)表示製程壓力高時、例如50mTorr (本 方法）。 依此則，於圖7 ( A )所示習知方法，製程壓力 因而離子或各原子之平均自由工程變長，結果，Cu + 屬靶 除去 微少 14B 14B 種膜 ，更 定較 增加 程度 力爲 晶圓 凹陷 與高 用如 狀況 方法 發明 低， 離子 -31 - 200824041 多數撞及晶圓表面對先前沈積之Ta膜等帶來較多損傷， 另外，沈積之Cu再度飛散使Cu沈積量變少。相對於此， 圖7(B)所示本發明方法中，Cu之雲110產生於處理空 間，離子或各原子之平均自由工程變短，結果，被Cu+離 子撞及而由沈積膜中飛出之Cu金屬原子因爲上述Cu之雲 110而跳回，該Cu金屬原子再度沈積於晶圓表面。結果 ，圖7 ( B )所示本發明方法中，朝晶圓表面之Cu沈積量 變多。因此，於圖7 ( B )所示狀態中，藉由控制偏壓電 力，則除中性金屬原子以外可使Cu +離子或Ar+離子被強 力吸引至下方而對凹部之底部進行削去。 以下針對補助種膜形成工程之電漿電力進行評估。 圖8爲評估結果，表示變化各種之電漿電力與偏壓電 力時之Cu膜之成膜速率分布圖。其中，製程壓力維持於 5 OmTorr之一定之同時，供給至金屬靶之直流電力維持於 3.2kW。偏壓電力於〇〜200瓦特（W)範圍內變化，關於 電漿電力分別爲，圖8 ( A )表示4kW，圖8 ( B )表示 3kW，圖 8 ( C )表示 2kW，圖 8 ( D )表示 lkW。 由圖可知，電漿電力爲圖8(A)之4kW及圖8 ( B ) 之3 kW時，在偏壓電力爲100瓦特以上時成膜速率爲“〇 “，無法利用。 相對於此，電漿電力爲圖8 ( C )之2kW時，在偏壓 電力超過100瓦特時可沈積微少之Cu膜，某種程度可利 用。電漿電力爲圖8(D)之lkW時，在偏壓電力於 0〜200W範圍內可沈積充分之Cu膜，確認爲良好。 -32- 200824041 又，分布圖雖未記載，針對電漿電力爲0.5kW時亦進 行和上述同樣之實驗結果確認亦可充分利用。另外，電漿 電力設爲小於〇.5kW時無法穩定產生電漿。因此可確認電 漿電力設於0.5〜2kW範圍內爲良好。 又，針對補助種膜形成工程之偏壓電力之實驗結果確 認，設於1 〇 〇〜2 5 0 W範圍內爲良好。偏壓電力設爲小於 1 00 W時離子之吸入變爲太弱，無法更進一步削去削去凹 陷部12之底部。偏壓電力設爲大於250W時對晶圓表面 之損傷變爲太大，而且Cu成膜量太小，較爲不好。 以下說明本發明之成膜方法第2實施形態。 圖9爲本發明第2實施形態之工程之一部分圖。本發 明之成膜方法中，係於圖4所示第1實施形態之形成圖4 (D )之Ta膜構成之主阻障膜10B的工程，與形成圖4 ( E)之補助種膜14A的工程之間，如圖9(A)所示，進行 補助阻障膜形成步驟而形成含有第3金屬的補助阻障膜 10C。其中，第3金屬可使用例如Ru (釕）等。該Ru膜 構成之補助阻障膜1 0C，可使用例如CVD (化學氣相沈積 )等形成於包含凹部5或連通孔8之內面的表面全體。結 果，阻障層1 0成爲底層膜1 0A、主阻障膜1 0B、補助阻障 膜10C之3層構造。 如上述說明，形成Ru膜構成之補助阻障膜l〇C時， 該Ru膜作爲補助種膜的功能，因此於該補助阻障膜1 0C 之形成後，形成圖4 ( E )之補助種膜14 A之後，不進行 圖4 ( F )之主阻障膜1 〇B的形成工程，而可直接進入圖4 -33- 200824041 (G )之鍍層工程。圖9 ( B )爲第2實施形態之最終之斷 面形狀。此情況下，以補助阻障膜10C及補助種膜14A形 成種層1 4。 - 又，Ru膜構成之補助阻障膜l〇C，亦作爲對Cu之種 膜功能，因此不設置Cu膜之補助種膜14A，而直接於上 述Ru膜之補助阻障膜10C上進行Cu鍍層亦可。 又，形成構成阻障層1〇之Ta膜或TaN膜時之方法並 未特別限定，例如使用對電漿電力等重複進行短時間、例 如數秒間隔之供給及停止供給，而以原子位準之厚度1層 1層地形成薄膜之所謂 ALD( Atomic Layer Deposition) 法亦可。 (TaN膜之形成方法之變形例） 以下說明成爲阻障層10之底層膜10A的TaN膜之形 成方法之變形例。如習知，阻障層10使用之TaN膜，係 爲防止配線材料或塡埋材料之Cu之擴散至層間絕緣膜之 絕緣層4者。但是，該TaN膜爲金屬氮化膜之故，不用說 和Cu比較，就連和Ta膜比較其之電阻係數亦相當高。因 此，該TaN膜，在Cu配線與絕緣層4接觸之部分需要存 在充分之厚度，然而若於導孔（via hole )、亦即連通孔8 之底部亦存在某種程度之厚度時，和下層配線層連接之導 孔底之部分的導孔電阻會上升，不僅導致Cll配線之電氣 特性惡化，亦將導致信賴性之劣化。此現象不限定於配線 材料爲C u之情況，對於其他金屬膜材料、例如w (鎢） -34- 200824041 等亦會產生。 5 於該變形例中，係藉由和上述沖孔製程不同之另一方 法除去導孔等連通孔8之底部之TaN膜。具體言之爲，於 TaN膜之成膜時設定製程條件，以使連通孔（導孔）8之 底部沈積之TaN膜之厚度，和其他部分沈積之TaN膜之 厚度比較變爲極端少，之後進行Ar蝕刻等而削去TaN膜 ，據以選擇性除去該連通孔8之底部沈積之微小厚度之 TaN 膜。 換言之，原子或分子之平均自由行程較長之低壓下’ 由金屬靶放出之中性Ta原子或中性N原子對晶圓W之垂 直方向以具有某種程度之角度射入，到達導孔底之連通孔 8之底部的機率雖變爲極少，但卻可以在溝部6之側壁或 溝部6之底部、亦即段部充分成膜。 相對於此，帶電之Ta離子，藉由電氣力可使進行方 向和晶圓 W之垂直方向相同，但欲於連通孔8之側壁成 膜時需要某種程度對垂直方向傾斜之Ta原子或N原子。 因此，本實施形態中，藉由中性Ta原子或中性N原子與 Ta離子間之比率之最適當化，需要創設出TaN膜可對溝 部6之側壁、溝部6之底部（段部）及連通孔8之側壁進 行成膜之同時，對連通孔8之底部難以進行成膜之狀態。 關於創設出之上述狀態之製程條件爲，偏壓電力爲〇 (圖3之縱軸），製程壓力爲8mTorr以下，較好是5 mTorr以下。ICP電力之電漿電力爲0.75〜1.5kW範圍內， 較好是0.8〜1.25kW範圍內。如上述說明，形成TaN膜後 -35- 200824041 ，於後續工程，藉由例如Ar氣體蝕刻而蝕刻全體之TaN 膜予以漸漸除去，此情況下，TaN膜最薄之連通孔8之底 部之TaN膜最先完全被除去，於此時點結束飩刻，如此則 ，可以選擇性僅除去連通孔8之底部之TaN膜。 參照圖1 〇說明包含上述成膜工程之一連串流程。圖 10爲含有TaN膜之阻障層之形成方法之變形例之一部分 工程圖。 首先，如圖4 ( A )所示，對表面形成有溝部6或導 孔等連通孔8之晶圓W，如圖10 ( A )所示，使用圖1之 成膜裝置32進行TaN膜之成膜處理形成底層膜10A。此 情況下，製程條件設定爲，晶圓W之最上之表面、溝部6 之側壁6A、或連通孔8之側壁8A及溝部6之段部、亦即 溝部6之底部6B可以分別充分進行成膜，而對連通孔8 之底部8B卻難以進行成膜之狀態。結果，例如晶圓W之 最上面之膜厚Η1設爲“ 1 00 “時，可製作出溝部6之底部 6Β之膜厚Η2約爲“ 50 “，連通孔8之底部8Β之膜厚Η3 約爲“ 20 “之膜厚差。 如上述說明，關於上述製程條件爲，偏壓電力爲0， 製程壓力爲8mTorr以下，較好是5 mTorr以下。電漿電 力爲0.75〜1.5kW範圍內，較好是〇·8〜1.25kW範圍內。如 上述說明，偏壓電力設爲〇，於幾乎不產生蝕刻之狀態下 進行TaN膜之成膜。其中，偏壓電力雖設爲〇，但於晶圓 W會被施加電漿引起之鞘電壓、例如20〜30伏特，依此則 離子於某種程度會被吸引至晶圓W側。 -36- 200824041 施加上述偏壓電力時，Ta離子被吸引過多，連通孔8 之底部8B沈積之膜厚H3過多，較爲不好。又，電漿電力 或製程壓力過大時，相對於中性元素之Ta離子佔有比率 會變多。電漿電力大於1.5kW時或製程壓力大於8mTorr 時，Ta離子佔有比率會變爲過多，連通孔8之底部8B沈 積之膜厚H3變大，膜厚H3和其他部分之厚度H2、H1間 之差變少，較爲不好。 反之，電漿電力小於0.7 5kW時，相對於中性元素之 Ta離子佔有比率會變爲過少，本來應成膜之溝部6之底 部6B之成膜量變爲過少，較爲不好。另外，製程壓力相 較於8mTorr降低至基礎壓力（l(T9Torr)附近時，亦不會 產生上述特別之問題。 如上述說明，形成由TaN膜構成之底層膜10A後， 如圖1 0 ( B )所示進行Ar濺鍍，削薄上述TaN膜構成之 底層膜1 〇A ’此情況下，雖然全表面之TaN膜被Ar濺鍍 慢慢被削去，但膜厚最薄之連通孔8之底部8 B上沈積之 膜厚H3之TaN膜最先被選擇性削去，在僅稍微過度蝕刻 而少量削去下層配線層2之時點結束飩刻處理。如此則， 可完全除去連通孔8之底部8B之部分之TaN膜，可減少 該部分之電阻、亦即導孔電阻，可提升電氣特性。Bias power: 100 to 2000 W As described above, the operating point can be set in the area A2 by appropriately selecting the above three conditions. At this time, if the operating point is set in a portion other than the region A2, the depressed portion 1 2 is not sufficiently formed, that is, the so-called punching structure cannot be formed. Also, other process conditions are such that the Ar gas flow rate is set to be in the range of about 50 to 1 Torr, and the process pressure is set to be in the range of about 0.001 Torr -28 to 200824041 (0.15 Pa) to 0.1 Torr (13.3 Pa). Further, in the above-described barrier layer forming process, a TaN film is formed as an example of the underlying film 10A, but a Ta film may be formed instead as an underlayer film. In this case, the Ta film 10B is formed on the Ta film of the underlayer film 10A, and the barrier layer is formed by the two-layer structure of the Ta film having different film forming conditions. In the following, as a result of the evaluation of the film-forming method of the present invention and the conventionally formed method, it is found that the conventional method is formed by depositing protrusions at the upper end of the concave portion 5, which is relatively poor. Therefore, the deposition film is not formed when the film formation method of the present invention is formed, and the depressed portion 12 can be formed in a good state. The following is an evaluation of the dependence of the aspect ratio of the shaved portion 丨2 on which the bottom portion of the concave portion 5 is formed, and the evaluation results are explained. Fig. 6 is a view showing the relationship between the aspect ratio of the concave portion and the amount of copper etching at the bottom. The recess is not a two-stage segment shape but is formed using a recess of the i-stage. Characteristic A of Fig. 6 shows a conventional method, and characteristic B shows a film forming method of the present invention. Specifically, in the conventional method, for a recess having various aspect ratios, plasma sputtering is performed on the surface of the wafer to form a barrier layer of approximately 60 nm, and then Ar etching is applied for a specific time. The depth of the recessed portion 12 formed at this time was measured, and the etching rate of copper was set. Further, in the film forming method of the present invention, for the recesses having various aspect ratios, plasma sputtering is performed on the surface of the wafer to form an underlayer film of approximately 4 nm, and then the first time is performed in a specific time range as in the above-described conventional method. step. The depth of the recessed portion 12 formed at this time was measured, and the etching rate of copper was set. -29- 200824041 It can be seen from Fig. 6 that in any of the characteristics A and B, the film formation amount at the bottom of the recess portion is increased as compared with the case where the aspect ratio is large, so that the etching rate of copper is reduced. Further, in the conventional method of the characteristic A, as the aspect ratio increases, the etching rate of copper changes, which means that the difference in the aspect ratio makes it difficult to cut the depth of the depressed portion 12 and is not preferable. On the other hand, in the film forming method of the present invention of the characteristic B, the etching rate of copper is largely changed when the aspect ratio is 2 or less, but the etching rate of copper is substantially constant when the aspect ratio is 2 or more. In the conventional concave portion 5, the aspect ratio is often 2 or more. Therefore, according to the film forming method of the present invention, it is confirmed that the depth of the cut recessed portion 12 is kept substantially uniform without being affected by the aspect ratio, and good results can be obtained. As described above, the depth of the recessed portion 12 is not affected by the shape of the recess 5, and therefore the recessed portion of the same depth can be often formed without being affected by the width of the recess. The following is an evaluation of the process conditions for the film formation process as shown in Fig. 4 (E). First, in the process shown in FIG. 4(D), when the Ta film 10B of the thickness H2 or the Ta/Cu mixed layer 100 having a large electric resistance generated by the bottom of the depressed portion 12 is removed, it is generally considered to have a lower process pressure, for example, The slurry of Ar gas was sputtered under a pressure of about 5 mT Torr to remove the above-mentioned Ta/Cu mixed layer 100 and the like. However, in this case, the Ta film 10B or the Ta/Cu mixed layer 100 in which the thickness H2 of the depressed portion 12 is removed may be removed, but at the same time, the entire surface of the wafer, particularly the portion of the concave portion 5, may be removed. The corner portion 1 02 (refer to FIG. 4(C)) may cause a large damage -30-200824041 due to the plasma sputtering of the Ar gas, which is not preferable. Therefore, in the present invention, the region A2 in Fig. 3 is used, and the gold is further used to further cut off the bottom of the recessed portion 12 toward the Ta/Cu mixed layer 100 while depositing only metal on the other wafer faces. Membrane, and in the next project, an essential seed film formed by attaching a Cu film (refer to FIG. 4(F)), wherein the metal target uses Cu of the same material as the essential seed film, so that a subsidy 14A composed of a Cu film can be deposited. . In addition, when the Cu metal target deposition support film 14A is used while further cutting the recessed portion 1 2 is removed, as described above, when the low process pressure is set, the average free atomic or ion engineering becomes large, and the wafer is wafer The surface is washed and the number of times increases the damage. Therefore, a certain higher process pressure is set. Specifically, in the present invention, the process pressure is set within a range of 30 to 90 mT 〇 rr, so that the metal film can be deposited while suppressing damage to the surface caused by ions. At the same time, the bottom of the cut portion 1 2 can be cut deeper. Fig. 7 is a schematic view showing a state of movement of Cu metal particles when the process pressure is low, showing a state in which the high-frequency film forming apparatus shown in Fig. 1 is sputtered with a Cu metal target in a part of the state at this time. Fig. 7 (A) shows a case where the process pressure is low, for example, 5 mTorr (preferred), and Fig. 7 (B) shows a case where the process pressure is high, for example, 50 mTorr (this method). Accordingly, in the conventional method shown in FIG. 7(A), the process pressure and thus the average free engineering of ions or atoms are lengthened. As a result, the Cu+ target removes a small amount of 14B 14B film, and the degree of force is increased. Wafer dents and high-use methods such as the state of the invention are low. Ion-31 - 200824041 Most collisions with the wafer surface cause more damage to the previously deposited Ta film. In addition, the deposited Cu re-scatters to reduce the Cu deposition amount. On the other hand, in the method of the present invention shown in Fig. 7(B), the cloud of Cu 110 is generated in the processing space, and the average free engineering of ions or atoms becomes short, and as a result, it is hit by the Cu+ ions and flies out of the deposited film. The Cu metal atoms jump back due to the above-mentioned Cu cloud 110, which is again deposited on the wafer surface. As a result, in the method of the present invention shown in Fig. 7(B), the deposition amount of Cu toward the surface of the wafer becomes large. Therefore, in the state shown in Fig. 7(B), by controlling the bias voltage, Cu + ions or Ar + ions can be strongly attracted to the lower side and the bottom portion of the concave portion can be removed in addition to the neutral metal atoms. The following is an evaluation of the plasma power of the subsidized seed film formation project. Fig. 8 is a graph showing the results of evaluation of the film formation rate of the Cu film when various plasma powers and bias voltages are changed. Among them, the process pressure was maintained at 5 OmTorr while the DC power supplied to the metal target was maintained at 3.2 kW. The bias power varies within a range of 〇200 watts (W), with respect to the plasma power, Figure 8 (A) shows 4 kW, Figure 8 (B) shows 3 kW, and Figure 8 (C) shows 2 kW, Figure 8 (D) ) indicates lkW. As can be seen from the figure, when the plasma power is 4 kW in Fig. 8(A) and 3 kW in Fig. 8(B), the film formation rate is "〇" when the bias power is 100 watt or more, and it cannot be used. On the other hand, when the plasma power is 2 kW as shown in Fig. 8(C), a small amount of Cu film can be deposited when the bias power exceeds 100 watts, and it can be used to some extent. When the plasma power was lkW of Fig. 8(D), a sufficient Cu film was deposited in the range of 0 to 200 W of the bias power, and it was confirmed to be good. -32- 200824041 Further, although the distribution map is not described, it is also possible to use the same experimental results as described above for the plasma power of 0.5 kW. In addition, when the plasma power is set to be less than 〇5 kW, plasma cannot be stably generated. Therefore, it was confirmed that the power of the plasma was set to be in the range of 0.5 to 2 kW. Further, the experimental results of the bias power for the subsidized seed film formation project were confirmed, and it was good in the range of 1 〇 〇 2 250 W. When the bias power is set to be less than 100 W, the suction of the ions becomes too weak, and the bottom of the recessed portion 12 cannot be further removed. When the bias power is set to be larger than 250 W, the damage to the surface of the wafer becomes too large, and the amount of Cu film formation is too small, which is not preferable. Next, a second embodiment of the film formation method of the present invention will be described. Fig. 9 is a partial view showing the construction of the second embodiment of the present invention. In the film formation method of the present invention, the main barrier film 10B formed of the Ta film of Fig. 4 (D) shown in Fig. 4 is formed, and the auxiliary seed film 14A of Fig. 4 (E) is formed. As shown in FIG. 9(A), the protective barrier film forming step is performed to form the auxiliary barrier film 10C containing the third metal. Among them, for the third metal, for example, Ru (ruthenium) or the like can be used. The auxiliary barrier film 10C composed of the Ru film can be formed on the entire surface including the concave portion 5 or the inner surface of the communication hole 8 by, for example, CVD (Chemical Vapor Deposition). As a result, the barrier layer 10 becomes a three-layer structure of the underlying film 10A, the main barrier film 10B, and the auxiliary barrier film 10C. As described above, when the barrier film l〇C is formed by the Ru film, the Ru film functions as a seed film. Therefore, after the formation of the auxiliary barrier film 10C, the auxiliary species of FIG. 4(E) is formed. After the film 14 A, the formation process of the main barrier film 1 〇 B of FIG. 4 (F) is not performed, and the plating process of FIG. 4 - 33 - 200824041 (G) can be directly entered. Fig. 9 (B) shows the final sectional shape of the second embodiment. In this case, the seed layer 14 is formed by the auxiliary barrier film 10C and the auxiliary seed film 14A. - In addition, the protective barrier film l〇C composed of the Ru film also functions as a seed film for Cu. Therefore, the Cu film is not provided with the auxiliary film 14A, and Cu is directly applied to the resist film 10C of the Ru film. The coating can also be used. Further, the method for forming the Ta film or the TaN film constituting the barrier layer 1 is not particularly limited. For example, the plasma power or the like is repeatedly supplied for a short time, for example, at intervals of several seconds, and the supply is stopped, and the atomic level is used. The so-called ALD (Atomic Layer Deposition) method in which a film is formed in one layer and one layer in thickness is also possible. (Modification of Method of Forming TaN Film) A modification of the method of forming the TaN film which becomes the underlying film 10A of the barrier layer 10 will be described below. As is conventionally known, the TaN film used for the barrier layer 10 is for preventing the diffusion of Cu of the wiring material or the buried material to the insulating layer 4 of the interlayer insulating film. However, the TaN film is a metal nitride film, and it is needless to say that the resistivity of the TaN film is relatively high as compared with the Cu film. Therefore, the TaN film needs to have a sufficient thickness in the portion where the Cu wiring is in contact with the insulating layer 4, but if there is a certain thickness in the via hole, that is, the bottom of the communication hole 8, the lower layer The via resistance of the portion of the via hole to which the wiring layer is connected increases, which not only causes deterioration in electrical characteristics of the C11 wiring, but also causes deterioration in reliability. This phenomenon is not limited to the case where the wiring material is Cu, and other metal film materials such as w (tungsten) -34-200824041 may also be generated. In the modification, the TaN film at the bottom of the communication hole 8 such as the via hole is removed by another method different from the above-described punching process. Specifically, the process conditions are set at the time of film formation of the TaN film so that the thickness of the TaN film deposited at the bottom of the via hole (guide hole) 8 is extremely less than the thickness of the TaN film deposited in other portions, after which The TaN film is cut by Ar etching or the like to selectively remove the TaN film of a minute thickness deposited at the bottom of the communication hole 8. In other words, when the average free path of the atom or molecule is longer, the neutral Ta atom or the neutral N atom is emitted from the metal target at a certain angle to the vertical direction of the wafer W, reaching the bottom of the via hole. Although the probability of the bottom of the communication hole 8 is extremely small, the film can be sufficiently formed on the side wall of the groove portion 6 or the bottom portion of the groove portion 6, that is, the segment portion. On the other hand, the charged Ta ions may have the same direction of progress as the vertical direction of the wafer W by electrical force, but a certain amount of Ta atoms or N inclined to the vertical direction is required to form a film on the sidewall of the communication hole 8. atom. Therefore, in the present embodiment, by optimizing the ratio of the neutral Ta atom or the neutral N atom to the Ta ion, it is necessary to create the TaN film to the side wall of the groove portion 6 and the bottom portion (segment portion) of the groove portion 6 and While the side wall of the communication hole 8 is formed into a film, it is difficult to form a film on the bottom of the communication hole 8. The process conditions for the above-described state are set such that the bias electric power is 〇 (the vertical axis of Fig. 3), and the process pressure is 8 mTorr or less, preferably 5 mTorr or less. The plasma power of the ICP power is in the range of 0.75 to 1.5 kW, preferably in the range of 0.8 to 1.25 kW. As described above, after forming the TaN film -35-200824041, in the subsequent process, the entire TaN film is etched by, for example, Ar gas etching, and gradually removed. In this case, the TaN film at the bottom of the thinnest via hole 8 of the TaN film is used. It is completely removed first, and the engraving is finished at this point. Thus, it is possible to selectively remove only the TaN film at the bottom of the communication hole 8. Referring to Fig. 1, a series of processes including the above film forming process will be described. Fig. 10 is a partial structural view showing a modification of a method of forming a barrier layer containing a TaN film. First, as shown in FIG. 4(A), the wafer W having the groove portion 6 or the communication hole 8 such as the via hole formed on the surface thereof is formed by using the film forming apparatus 32 of FIG. 1 as shown in FIG. 10(A). The film formation process forms the underlayer film 10A. In this case, the process conditions are such that the uppermost surface of the wafer W, the side wall 6A of the groove portion 6, or the side wall 8A of the communication hole 8 and the segment portion of the groove portion 6, that is, the bottom portion 6B of the groove portion 6, can be sufficiently formed into films. However, it is difficult to form a film on the bottom portion 8B of the communication hole 8. As a result, for example, when the film thickness Η1 of the uppermost surface of the wafer W is set to "100", the film thickness Η2 of the bottom portion 6 of the groove portion 6 can be made approximately "50", and the film thickness Η3 of the bottom portion 8 of the communication hole 8 is approximately The film thickness is "20". As described above, the above process conditions are such that the bias power is 0, and the process pressure is 8 mTorr or less, preferably 5 mTorr or less. The plasma power is in the range of 0.75 to 1.5 kW, preferably in the range of 〇·8 to 1.25 kW. As described above, the bias power is set to 〇, and the TaN film is formed in a state where etching is hardly caused. Here, although the bias power is set to 〇, the sheath voltage caused by the plasma is applied to the wafer W, for example, 20 to 30 volts, whereby the ions are attracted to the wafer W side to some extent. -36- 200824041 When the above-mentioned bias electric power is applied, Ta ions are excessively attracted, and the film thickness H3 deposited on the bottom portion 8B of the communication hole 8 is excessively large, which is not preferable. Further, when the plasma power or the process pressure is too large, the Ta ion occupancy ratio with respect to the neutral element increases. When the plasma power is greater than 1.5 kW or the process pressure is greater than 8 mTorr, the Ta ion occupancy ratio becomes excessive, and the film thickness H3 deposited at the bottom 8B of the communication hole 8 becomes large, and the film thickness H3 and the thickness of other portions are between H2 and H1. The difference is less, it is not good. On the other hand, when the plasma power is less than 0.7 5 kW, the Ta ion occupancy ratio with respect to the neutral element becomes too small, and the film formation amount of the bottom portion 6B of the groove portion 6 to be film-formed is too small, which is not preferable. In addition, the above process is not caused when the process pressure is lowered to the base pressure (1 (T9 Torr)) in comparison with the 8 mTorr. As described above, after the underlayer film 10A composed of the TaN film is formed, as shown in Fig. 10 (B) In the case where Ar sputtering is performed, the underlying film 1 〇A' of the above TaN film is thinned. In this case, although the TaN film of the entire surface is slowly cut by Ar sputtering, the thinned via hole 8 is formed. The TaN film of the film thickness H3 deposited on the bottom portion 8 B is first selectively removed, and the etching process is finished at the point of only slightly over-etching and a small amount of the lower wiring layer 2 is removed. Thus, the communication hole 8 can be completely removed. The TaN film of the portion of the bottom portion 8B can reduce the resistance of the portion, that is, the via resistance, and can improve the electrical characteristics.

Ar濺鍍處理結束後，如圖10 ( C )所示進行例如 CVD處理，於溝部6或連通孔8之全表面形成例如RU膜 構成的補助阻障膜10C。此爲荷圖9(A)同樣之處理。 之後，如圖9(B)所示，形成種膜14A進行Cu鍍層 -37- 200824041 處理亦可，或以Ru膜構成的補助阻障膜10C作爲種膜之 功能，於其上直接進行Cu鍍層處理亦可，後續工程之處 理種類未特別限定。 又，說明形成如圖1 〇 ( A )所示TaN膜構成之底層膜 1 〇A後，進行如圖1 0 ( B )所示Ar濺鍍處理，但不限定 於此，形成底層膜1 〇A後，進行如圖4 ( D )所示Ta膜構 成之主阻障膜10B後，連續進行圖4 ( E)〜圖4 ( H)所 示各處理亦可。 任一情況下，均藉由採用上述TaN膜之形成方法，和 其他部分之膜厚比較，可將連通孔8之底部8B之膜厚設 爲極小，結果可以選擇性僅除去該部分之TaN膜，可抑制 例如導孔電阻，可提升電氣特性。 上述實施形態中，說明於凹部5之一部分形成連通孔 8，亦即所謂2階段之段部形狀之凹部5之例，但本發明 不限定於此，亦適用於凹部5本身爲導孔或通孔之連通孔 8的所謂1階段之凹部。 上述實施形態中，各數値僅爲一例，但不限定於此， 又，上述實施形態中，說明TaN/Ta/Cu、Ta/Ta/Cu之積層 構造作爲全體之阻障層/種膜之積層構造，但本發明不限 定於此種積層構造。本發明亦適用於例如TiN/Ti/Cu積層 構造、TaN/Ru/Cu積層構造、Ti/Cu積層構造、以及 TiN/Ti/Ru、Ti/Ru、TaN/Ru、TaN/Ta/Ru 之各積層構造。 另外，高頻電源之頻率不限定於13.56MHz，可使用 其他例如27.0MHz之頻率。又，作爲電漿用之惰性氣體不 -38- 200824041 限定於Ar氣體，可使用其他例如He或Ne等。 另外，被處理體以半導體晶圓爲例說明，但不限定於 此，亦可使用其他例如LCD基板、玻璃基板、陶瓷基板 等。 (發明效果） 依本發明之成膜方法、成膜裝置及記憶媒體可發揮以 φ 下極佳作用效果。 藉由適當選擇阻障層或補助種膜等之成膜時之製程條 件，可以選擇性僅削去凹部之最下層底部而在包含凹部內 之表面的被處理體表面全體區域形成薄膜，而且不受凹部 之寬度影響，可以削去同一深度範圍之底部、形成同一深 度之削去凹陷部，另外，可以除去削去凹陷部之底部之電 阻上升原因之例如Ta/Cu混合層，而於凹部側面或上面形 成薄膜。 【圖式簡單說明】 圖1爲本發明之成膜裝置之一例之斷面圖。 圖2爲濺鍍蝕刻之角度依存性之分布圖。 * 圖3爲偏壓電力與晶圓上面之成膜量間之關係之分布 圖。 圖4(A) - (H)爲本發明之成膜方法中第1實施形 態說明用之流程圖。 圖5爲主阻障膜之成膜時之連通孔底部（削去凹陷部 -39- 200824041 之底部）之一部分擴大圖。 圖6爲凹部之深寬比與底部之銅蝕刻量間之關係之分 布圖。 圖7(A) - (B)爲製程壓力低時與高時之Cu金屬粒 子之動向模式圖。 圖8(A) - (D)爲變化各種之電漿電力與偏壓電力 時之Cu膜之成膜速率分布圖。 圖9 ( A ) - ( B )爲本發明第2實施形態之工程之一 部分圖。 圖1 0 ( A ) - ( C )爲含有丁以膜之阻障層之形成方法 之變形例之一部分工程圖。 圖11(A) - (C)爲半導體晶圓上形成之連通孔之塡 埋前之狀態。 圖12(A) - (E)爲連通孔之塡埋工程圖。 圖1 3 ( A ) - ( B )爲各種不同寬度之凹部（trench ) 之態樣圖。 【主要元件符號說明】 2 :下層配線層，4 :絕緣層，5 :凹部，6 :溝部， 8 :連通孔，10 ··阻障層，12 :削去凹陷部，14 :種層， 1 6 :上層配線層，1 8 :沈積突起物，20 :屏蔽部，W :晶 圓，32 :成膜裝置，34 :處理容器，36 :底部，38 :排氣 口，40 :節流閥，42 :真空幫補，44 :載置台，46 :靜電 夾頭，4 8 :支柱，5 0 :金屬波紋管，5 2 :冷媒循環路， -40- 200824041 54 :支撐銷，56 :銷插通孔，60 :配線，62 :偏壓電源， 64 :透過板，66 :密封構件，68 :處理空間，70 :電漿產 生源，72 :感應線圈部，74 :高頻電源，76 :導波板， 78 :金屬靶，80 :可變直流電源，82 :保護蓋，84 :氣體 導入口，86 :氣體控制部，88 :裝置控制部。 -41 -After the Ar sputtering process is completed, for example, a CVD process is performed as shown in Fig. 10(C), and a barrier film 10C made of, for example, an RU film is formed on the entire surface of the groove portion 6 or the communication hole 8. This is the same processing as in Figure 9 (A). Thereafter, as shown in FIG. 9(B), the seed film 14A is formed to perform Cu plating-37-200824041 treatment, or the auxiliary barrier film 10C composed of a Ru film is used as a seed film function, and Cu plating is directly performed thereon. Processing may also be performed, and the type of processing of subsequent projects is not particularly limited. Further, after forming the underlying film 1 〇A formed of a TaN film as shown in Fig. 1 (A), the Ar sputtering process as shown in Fig. 10 (B) is performed. However, the present invention is not limited thereto, and the underlying film 1 is formed. After A, the main barrier film 10B having a Ta film as shown in Fig. 4(D) is applied, and the respective processes shown in Figs. 4(E) to 4(H) may be continuously performed. In either case, by using the above-described method of forming a TaN film, the film thickness of the bottom portion 8B of the communication hole 8 can be made extremely small as compared with the film thickness of other portions, and as a result, only the portion of the TaN film can be selectively removed. It can suppress, for example, the via resistance and improve electrical characteristics. In the above-described embodiment, an example in which the communication hole 8 is formed in one portion of the recessed portion 5, that is, the recessed portion 5 having a two-stage segment shape is described. However, the present invention is not limited thereto, and is also applicable to the recessed portion 5 itself being a guide hole or a through hole. A so-called one-stage recess of the communication hole 8 of the hole. In the above-described embodiment, each number is only an example, but the present invention is not limited thereto. In the above embodiment, the laminated structure of TaN/Ta/Cu and Ta/Ta/Cu is described as the entire barrier layer/film. The laminated structure is not limited to such a laminated structure. The present invention is also applicable to, for example, a TiN/Ti/Cu buildup structure, a TaN/Ru/Cu buildup structure, a Ti/Cu buildup structure, and each of TiN/Ti/Ru, Ti/Ru, TaN/Ru, TaN/Ta/Ru. Laminated structure. Further, the frequency of the high-frequency power source is not limited to 13.56 MHz, and other frequencies such as 27.0 MHz can be used. Further, the inert gas for plasma is not limited to Ar gas, and other examples such as He or Ne can be used. Further, the object to be processed is exemplified by a semiconductor wafer, but the invention is not limited thereto, and other examples such as an LCD substrate, a glass substrate, a ceramic substrate, or the like may be used. (Effect of the Invention) According to the film forming method, the film forming apparatus, and the memory medium of the present invention, it is possible to exhibit an excellent effect in φ. By appropriately selecting the process conditions at the time of film formation such as the barrier layer or the seed film, it is possible to selectively remove only the bottommost layer bottom portion of the concave portion and form a film on the entire surface of the object surface including the surface in the concave portion, and Due to the influence of the width of the concave portion, the bottom portion of the same depth range can be cut, and the cut-out recess portion of the same depth can be formed. Further, for example, the Ta/Cu mixed layer can be removed from the bottom portion of the recessed portion, and the side of the concave portion can be removed. Or forming a film on top. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing an example of a film forming apparatus of the present invention. Figure 2 is a plot of the angular dependence of sputter etching. * Figure 3 is a plot of the relationship between bias power and the amount of film formed on the wafer. Fig. 4 (A) - (H) is a flow chart for explaining the first embodiment of the film forming method of the present invention. Fig. 5 is a partial enlarged view of the bottom of the communication hole at the time of film formation of the main barrier film (the bottom portion of the depressed portion -39-200824041). Fig. 6 is a view showing the relationship between the aspect ratio of the concave portion and the amount of copper etching at the bottom. Fig. 7(A) - (B) is a schematic diagram showing the movement pattern of Cu metal particles at a low and high process pressure. Fig. 8(A) - (D) are graphs showing the film formation rate distribution of the Cu film when various plasma powers and bias powers are varied. Fig. 9 (A) - (B) is a partial view showing the construction of the second embodiment of the present invention. Fig. 10 (A) - (C) is a partial engineering view of a modification of the method for forming a barrier layer containing a film. Fig. 11(A) - (C) shows the state before the burying of the communication hole formed in the semiconductor wafer. Fig. 12(A) - (E) are the buried engineering drawings of the communication holes. Figure 1 3 ( A ) - ( B ) is a pattern of various widths of the trench. [Description of main component symbols] 2: lower wiring layer, 4: insulating layer, 5: recessed portion, 6: groove portion, 8: communication hole, 10 · barrier layer, 12: chipped portion, 14: seed layer, 1 6: upper wiring layer, 18: deposited protrusions, 20: shield, W: wafer, 32: film forming device, 34: processing container, 36: bottom, 38: exhaust port, 40: throttle valve, 42: vacuum, 44: mounting table, 46: electrostatic chuck, 4 8: pillar, 50: metal bellows, 5 2: refrigerant circulation, -40- 200824041 54: support pin, 56: pin insertion hole , 60 : Wiring, 62 : Bias power supply, 64 : Transmissive plate, 66 : Sealing member, 68 : Processing space, 70 : Plasma generating source, 72 : Inductive coil part, 74 : High frequency power supply, 76 : Guide wave board , 78: metal target, 80: variable DC power supply, 82: protective cover, 84: gas inlet, 86: gas control, 88: device control. -41 -

Claims (1)

200824041 十、申請專利範圍 1.一種成膜方法，其特徵爲： 具備： 載置工程，使表面形成有凹部的被處理體，載置於可 抽成真空的處理容器內設置之載置台；及 形成工程，於處理容器內藉由惰性氣體電漿化而產生 之電漿，使金屬靶離子化而產生含有金屬離子的金屬粒子 φ ，藉由偏壓電力使該金屬粒子被吸引至上述處理容器內之 載置台上載置的被處理體而於上述被處理體表面形成含有 上述金屬的薄膜； 於上述被處理體表面形成薄膜的工程係具有： 阻障層形成工程，係削去上述被處理體之凹部之底部 而形成削去凹陷部之同時，於包含上述凹部內表面之上述 被處理體表面全體形成含有第1金屬的阻障層；及 補助種膜形成工程，更進一步削去上述削去凹陷部之 • 底部，而於包含上述凹部內表面之上述被處理體表面形成 含有第2金屬的鍍層用補助種膜。 I 2.如申請專利範圍第1項之成膜方法，其中， 於上述補助種膜形成工程之後，進行本質種膜形成工 ' 程而形成鍍層用之本質種膜。 3 .如申請專利範圍第2項之成膜方法，其中， 於上述本質種膜形成工程之後，進行對上述第2金屬 施予鍍層之鍍層工程。 4.如申請專利範圍第1項之成膜方法，其中， -42- 200824041 上述阻障層形成工程包含： 底層膜形成工程，係於包含上述凹部內表面之上述被 處理體表面全體形成由上述第1金屬之氮化膜構成的底層 膜；及 主阻障膜形成工程，係於形成上述削去凹陷部之同時 ，至少於上述凹部內之側壁形成由上述第1金屬之單體構 成的主阻障膜。 5·如申請專利範圍第1項之成膜方法，其中， 上述第1金屬由Ta構成，而且上述第2金屬由Cu構 成。 6·如申請專利範圍第1項之成膜方法，其中， 上述阻障層形成工程包含： 底層膜形成工程，係於包含上述凹部內表面之上述被 處理體表面全體形成由上述第1金屬之氮化膜構成的底層 膜； 主阻障膜形成工程，係於形成上述削去凹陷部之同時 ，至少於上述凹部內之側壁形成由上述第1金屬之單體構 成的主阻障膜；及 補助阻障膜形成工程，係形成含有第3金屬之補助阻 障膜。 7·如申請專利範圍第6項之成膜方法，其中， 於上述補助阻障膜形成工程之後，進行對上述第2金 屬施予鍍層之鍍層工程。 8 ·如申請專利範圍第5或6項之成膜方法，其中， -43- 200824041 上述第1金屬由Ta構成，上述第2金屬由Cu構成， 而且上述第3金屬由Ru構成。 9. 如申請專利範圍第1項之成膜方法，其中， 上述補助種膜形成工程，係設定上述處理容器內之壓 力爲30〜90mTorr之範圍內而進行。 10. 如申請專利範圍第1項之成膜方法，其中， 上述補助種膜形成工程，係設定上述偏壓電力爲 φ 1〇〇〜250瓦特（watt)之範圍內而進行。 11. 如申請專利範圍第1項之成膜方法，其中， 上述補助種膜形成工程，係設定上述電漿形成用電力 爲0.5〜2千瓦（kilowatt )之範圍內而進行。 12. 如申請專利範圍第1項之成膜方法，其中， 上述被處理體之凹部，係具有成爲導孔（via hole ) 或通孔（through hole )之連通孔，被形成爲2階段之段 部形狀。 • 1 3 ·如申請專利範圍第1項之成膜方法，其中， 上述凹部，係由成爲導孔或通孔之連通孔構成。 14·-種成膜裝置，其具備： 可抽成真空的處理容器； ~ 載置台，用於載置表面形成有凹部的被處理體； 氣體導入手段，對上述處理容器內導入至少含有惰性 氣體的特定氣體； 電漿產生源，產生電漿電力，對上述處理容器內產生 惰性氣體之電漿； -44 - 200824041 金屬靶，設於上述處理容器內，被施加直流電力，藉 由上述電漿應被離子化； 偏壓電源，對上述載置台供給特定之偏壓電力； '及 裝置控制部，用於控制氣體導入手段、電漿產生源、 及偏壓電源；其特徵爲： 上述裝置控制部，係控制氣體導入手段、電漿產生源 、及偏壓電源，以使上述凹部內之上述削去凹陷部之底部 更進一步被削去，而於包含上述凹部內表面之上述被處理 體表面形成含有第.2金屬的薄膜所構成之鍍層用補助種膜 〇 1 5 · —種電腦程式，係使電腦執行成膜方法者，其特 徵爲： 成膜方法具備： 載置工程，使表面形成有凹部的被處理體，載置於可 抽成真空的處理容器內設置之載置台；及 形成工程，於處理容器內藉由惰性氣體電漿化而產生 之電漿，使金屬靶離子化而產生含有金屬離子的金屬粒子 ，藉由偏壓電力使該金屬粒子被吸引至上述處理容器內之 載置台上載置的被處理體而於上述被處理體表面形成含有 上述金屬的薄膜； 於上述被處理體表面形成薄膜的工程係具有： 補助種膜形成工程，更進一步削去凹部內之底部之削 去凹陷部，而於包含上述凹部內表面之上述被處理體表面 形成含有第2金屬的鍍層用補助種膜。 -45- 200824041 1 6 · —種記憶媒體，係記憶有使電腦執行成膜方法之 電腦程式者，其特徵爲·· 成膜方法具備： 載置工程，使表面形成有凹部的被處理體，載置於可 抽成真空的處理容器內設置之載置台；及 形成工程，於處理容器內藉由惰性氣體電漿化而產生 之電漿，使金屬靶離子化而產生含有金屬離子的金屬粒子 ，藉由偏壓電力使該金屬粒子被吸引至上述處理容器內之 載置台上載置的被處理體而於上述被處理體表面形成含有 上述金屬的薄膜； 於上述被處理體表面形成薄膜的工程係具有： 補助種膜形成工程，更進一步削去上述凹部內之底部 之削去凹陷部，而於包含上述凹部內表面之上述被處理體 表面形成含有第2金屬的鍍層用補助種膜。200824041 X. Patent application scope 1. A film forming method, comprising: a mounting object, a processed object having a concave portion formed on a surface thereof, and a mounting table placed in a processing container capable of being evacuated; and Forming a process, ionizing the metal target by ionizing the metal target in the processing vessel to generate metal particles φ containing metal ions, and attracting the metal particles to the processing container by bias electric power a film to be processed placed on the mounting table to form a film containing the metal on the surface of the object to be processed; and a process for forming a film on the surface of the object to be processed: a barrier layer forming process for cutting the object to be processed a bottom portion of the concave portion is formed with the recessed portion, and a barrier layer containing the first metal is formed on the entire surface of the object to be processed including the inner surface of the concave portion; and the seed film forming process is supplemented, and the above-mentioned shaving is further removed. a bottom portion of the depressed portion, and a coating for the second metal is formed on the surface of the object to be processed including the inner surface of the concave portion Seed film. I. The film forming method according to the first aspect of the invention, wherein after the above-mentioned auxiliary seed film forming process, an essential seed film forming process is performed to form an essential seed film for plating. 3. The film forming method of claim 2, wherein after the above-described essential film forming process, a plating process for applying the plating to the second metal is performed. 4. The film forming method of claim 1, wherein the barrier layer forming process comprises: an underlayer film forming process, wherein the entire surface of the object to be processed including the inner surface of the concave portion is formed by the above The underlying film formed of the nitride film of the first metal; and the main barrier film forming process are formed by forming the above-described shaved recessed portion and forming a main body of the first metal alone at least in the sidewall of the recessed portion Barrier film. 5. The film forming method according to claim 1, wherein the first metal is composed of Ta, and the second metal is composed of Cu. 6. The method of forming a film according to the first aspect of the invention, wherein the barrier layer forming process comprises: forming an underlayer film on the entire surface of the object to be processed including the inner surface of the concave portion by the first metal The underlying film formed of a nitride film; the main barrier film forming process is formed by forming the main recessed film composed of the single metal of the first metal at least at the sidewall of the recess; The barrier film formation process is supplemented to form a barrier film containing a third metal. 7. The film forming method of claim 6, wherein the plating process for applying the plating to the second metal is performed after the auxiliary barrier film forming process. 8. The film forming method according to claim 5 or 6, wherein the first metal is composed of Ta, the second metal is made of Cu, and the third metal is made of Ru. 9. The film forming method according to the first aspect of the invention, wherein the auxiliary seed film forming process is performed by setting a pressure in the processing container to be in a range of 30 to 90 mTorr. 10. The film forming method according to the first aspect of the invention, wherein the auxiliary seed film forming process is performed by setting the bias electric power to be within a range of φ 1 〇〇 to 250 watts. 11. The film forming method according to the first aspect of the invention, wherein the auxiliary seed film forming process is performed by setting the electric power for forming the plasma to be within a range of 0.5 to 2 kilowatts. 12. The film forming method according to claim 1, wherein the concave portion of the object to be processed has a communication hole which is a via hole or a through hole, and is formed into a two-stage segment. Part shape. The film forming method of the first aspect of the invention, wherein the concave portion is constituted by a communicating hole which is a guide hole or a through hole. A film forming apparatus comprising: a processing container capable of being evacuated; a mounting table for placing a target object having a concave portion formed on a surface thereof; and a gas introduction means for introducing at least an inert gas into the processing container a specific gas; a plasma generating source, generating plasma power, and a plasma generating an inert gas in the processing container; -44 - 200824041 a metal target, disposed in the processing container, being applied with DC power by the above plasma Should be ionized; a bias power supply to supply a specific bias power to the mounting table; and a device control unit for controlling the gas introduction means, the plasma generating source, and the bias power source; characterized by: a control gas introducing means, a plasma generating source, and a bias power source for further cutting the bottom of the shaved recess in the recess to cover the surface of the object to be processed including the inner surface of the recess A method for forming a plating film for a plating layer containing a film of a second metal, a computer program, and a computer for performing a film forming method, The film forming method includes: a mounting process, a workpiece to be formed with a concave portion on a surface thereof, a mounting table placed in a processing container that can be evacuated, and a forming process in which an inert gas is used in the processing container The plasma generated by the plasma is ionized to generate metal particles containing metal ions, and the metal particles are attracted to the object to be processed placed on the mounting table in the processing container by bias electric power. A film containing the metal is formed on the surface of the object to be processed; and a process for forming a film on the surface of the object to be processed includes: a film forming process for assisting the film formation, and further cutting off the depressed portion at the bottom of the concave portion, and including the concave portion The surface of the object to be processed on the inner surface forms a seed film for a plating layer containing a second metal. -45- 200824041 1 6 - A type of memory medium, which is a computer program that causes a computer to perform a film formation method, and is characterized in that: the film formation method includes: a workpiece to be placed on a surface, and a processed body having a concave portion formed thereon; a mounting table disposed in a processing chamber capable of being evacuated; and a forming process, wherein the metal target is ionized to generate metal ions containing metal ions by plasma generated by plasma mastication in the processing container The metal particles are attracted to the object to be processed placed on the mounting table in the processing container by bias electric power to form a film containing the metal on the surface of the object to be processed, and a film is formed on the surface of the object to be processed. The auxiliary seed film forming process is performed, and the cut-out recessed portion in the bottom portion of the concave portion is further removed, and the auxiliary seed film for the plating layer containing the second metal is formed on the surface of the object to be processed including the inner surface of the concave portion. -46--46-
TW96128229A 2006-08-01 2007-08-01 Method and apparatus of forming film, and recording medium TW200824041A (en)

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