WO2006074847A1 - Convertisseur analogique-numerique - Google Patents

Convertisseur analogique-numerique Download PDF

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Publication number
WO2006074847A1
WO2006074847A1 PCT/EP2005/056670 EP2005056670W WO2006074847A1 WO 2006074847 A1 WO2006074847 A1 WO 2006074847A1 EP 2005056670 W EP2005056670 W EP 2005056670W WO 2006074847 A1 WO2006074847 A1 WO 2006074847A1
Authority
WO
WIPO (PCT)
Prior art keywords
analog
digital converter
digital
quantization
adc
Prior art date
Application number
PCT/EP2005/056670
Other languages
German (de)
English (en)
Inventor
Wolfram Bauer
Christoph Lang
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to US11/795,430 priority Critical patent/US8188900B2/en
Priority to JP2007550724A priority patent/JP2008527869A/ja
Priority to EP05817220A priority patent/EP1842289B1/fr
Publication of WO2006074847A1 publication Critical patent/WO2006074847A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0614—Continuously compensating for, or preventing, undesired influence of physical parameters of harmonic distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

Definitions

  • the invention is based on an analog-digital converter with an analog input signal and with at least one quantization threshold.
  • Digital controllers can be used to control analog quantities, since they have the following advantages:
  • the time constants are digitally adjustable, which excludes both temperature dependencies and aging.
  • the time constants can be chosen arbitrarily large.
  • Fig. 1 such a control loop is shown in the form of a principle block diagram.
  • Digital control of an analogue size requires the use of an analog-to-digital converter (ADC). This compares its analog input signal, which can run via an analog preamplifier, with its quantization thresholds and outputs a correspondingly quantized digital value. This digital value is processed by the controller and fed to a digital-to-analog converter, which acts with its analog output signal to the analog variable to be controlled.
  • ADC analog-to-digital converter
  • One way to reduce the amplitude of the limit cycle is to reduce the gap between two quantization thresholds in the ADC, thereby reducing the quantization error of the ADC. If the measuring range remains the same, however, the number of quantization thresholds must be increased.
  • ADU reacts with a change of its output signal. One then speaks of a "dead zone”.
  • the conversion rate of the ADC must be high. This is where the use of a flash ADC, which compares an analog input signal with each of its quantization thresholds at one time, is useful. This is done by using comparators, each of which compares the input signal to an analog reference.
  • a possible application example is the regulation of a high-frequency oscillator amplitude with a comparatively small controller bandwidth.
  • the analogue vibration is converted from a flash ADC to a digital one.
  • the digital then the rectification and subsequent Tiefpassf ⁇ ltêt. This is shown in FIG. 2.
  • the invention is based on an analog-digital converter with an analog input signal and with at least one quantization threshold.
  • the essence of the invention is that the analog-to-digital converter has means for changing the at least one NEN quantization threshold has. It is advantageous here that the resolution can be changed by changing the quantization threshold.
  • Quantization thresholds is changeable.
  • the means for changing at least one quantization threshold are configured such that a targeted change of the quantization threshold is represented by an average value. By averaging the digital output signal over several changes of the quantization threshold, effects of these changes on the digital output signal can be filtered out.
  • An advantageous embodiment of the invention provides that the analog to digital conversion and / or the means for changing at least one quantization threshold are controlled by one clock.
  • Flash ADU can be used and the time of the analog to digital implementation can be determined. This is advantageous in terms of time-varying, such as high-frequency periodic signals.
  • Digital converter represents a periodic signal and the clock (645) to this periodic signal has a fixed phase relationship.
  • An advantageous embodiment of the invention provides an analog-to-digital converter with an array of comparators (Kl, ... K7) as a threshold value switch, with a first reference voltage U ref and with an array of resistors (Rl, ..., R6) Representation of further, generated from the first reference voltage U ref reference voltages for the determination of quantization thresholds before.
  • the means for changing at least one quantization threshold are designed as controllable resistors (Rl,..., R6).
  • Another advantageous embodiment of the invention provides an analog-to-digital converter with an arrangement of comparators (K1, K7) as a threshold value switch, with a first reference voltage Uref and with an arrangement of resistors (R1, ..., R6). to illustrate further, generated from the first reference voltage U ref
  • the means for changing at least one quantization threshold as a controllable current source (I dice), which is connected to the arrangement of resistors (Rl, ..., R6) formed.
  • the invention is advantageous.
  • Another field of application of the invention is a digital tracking synchronization (PLL).
  • PLL digital tracking synchronization
  • the invention provides the advantage of reducing the dead zones of the ADC.
  • ADC analog-to-digital converter
  • An advantageous embodiment of the invention includes a circuit principle according to FIG. 4 for scrambling the gains of a flash ADC.
  • amplification cubeing is advantageous due to the easy-to-implement scrambling of the current flowing through the resistor network shown in FIG.
  • a gain scrambling through the use of controlled resistors in the resistor network shown in FIG.
  • Particularly advantageous is a fully differential realization of the circuit principle shown in Figure 4 as shown in Fig. 5.
  • An advantageous embodiment of the invention involves filtering the measurement results of the ADC by a digital filter in order to further process the mean value of the ADC output signal and to suppress the influence of the amplification scrambling on the output signal of the system.
  • a digital filter is advantageously advantageous in the way that there is a zero at the repetition frequency of the change in the gains. It is advantageous to derive the clock frequency of the digital filter from the analog oscillation to be regulated, whereby the frequency of the zero point of the digital filter automatically adapts to the repetition frequency of the amplifications and the effect of the filter always remains optimal over temperature and also over the lifetime.
  • An advantageous embodiment of the invention involves adjusting the various values of the gains of the ADC in a repetitive sequence of gains such that the values of the gains result from the superposition of gain sequences of different frequencies, thereby reducing the amplitude of a limit cycle to a broad one Frequency spectrum of low Störamplitude is distributed.
  • Fig. 1 shows a digital control for analog signals with analog-to-digital converter.
  • Fig. 2 shows a digital control for high-frequency analog vibration signals with
  • Fig. 3 shows an example of the variation of the gain by an inventive
  • FIG 4 shows an embodiment of the analog-digital converter according to the invention with comparators with variable reference voltage.
  • Fig. 5 shows an embodiment of the analog-to-digital converter according to the invention with comparators with variable reference voltage fully different.
  • Fig. 6 shows schematically a digital phase locked loop with an inventive ADC converter. Description of exemplary embodiments
  • Fig. 1 shows a digital control for analog signals with analog-to-digital converter. Shown is such a control loop in the form of a principle block diagram.
  • An analog size 100 generates an analog input signal which is supplied to an analog amplifier 110.
  • the amplified analog input signal is then fed to an analog to digital converter (ADC) 120 and converted to a digital input signal.
  • ADC analog to digital converter
  • the digital input signal is fed to a digital controller 130 which generates a digital control signal therefrom.
  • the digital control signal is supplied to a digital-to-analog converter 140, which generates an analog control signal therefrom.
  • the analog control signal is in turn supplied to the analog size 100, with which the control loop is closed.
  • ADU analog-to-digital converter
  • This digital value is processed by the controller and fed to a digital-to-analog converter, which acts with its analog output signal to the analog variable to be controlled.
  • the requirements for the ADC when converting analogue vibrations with high frequency are made more stringent.
  • the conversion rate of the ADC must be high.
  • the use of a flash ADC is suitable, which at one time compares an analog input signal with all its quantization thresholds. This is done by using comparators, each of which compares the input signal to an analog reference. To determine the time at which the comparison takes place, the flash ADC is clocked as usual in the art.
  • a typical example of application is the regulation of a high-frequency oscillator amplitude with a comparatively small controller bandwidth.
  • the analogue vibration is converted from a flash ADC to a digital one.
  • the digital In the digital then the rectification and subsequent low-pass filtering.
  • Fig. 2 shows an example of a digital control for high-frequency analog vibration signals with analog-to-digital converter. Shown is an expanded control loop according to FIG. 1.
  • ADC analog-to-digital converter
  • a digital part 200 follows in the signal path.
  • the digital control signal is generated, which is supplied to the digital-to-analog converter 140.
  • the digital part 200 contains in the signal path on the input side a rectifier 210 which rectifies the input signal.
  • a low-pass filter 220 in which the signal is filtered.
  • the digital controller 130 in which the digital control signal is generated.
  • the analog-to-digital converter ADU according to the invention is suitable. Further, in systems which are not feedback, the invention provides the advantage of reducing the dead zones of the ADC.
  • An embodiment of the analog-to-digital converter ADU according to the invention includes that the gains of the ADC are deliberately scrambled. This means that the ADU operates for a given period of time with a constant gain and the corresponding locations of its quantization thresholds. At the end of this period, the gain in the ADC is changed by shifting the position of its quantization thresholds by a factor.
  • an inventive flash ADC is preferably used. With this gain setting, the ADU is again operated for a fixed period of time until its gain is switched again. This results in a sequence of reinforcements, which are present for a limited period of time. This sequence of gains will vary by an average and can be repeated at one frequency.
  • Fig. 3 shows an example of the variation of the gain by an analog-to-digital converter according to the invention.
  • the variation of the amplification can take place during normal operation of the analog-to-digital converter, in particular also outside of trimming operations for the preliminary adjustment of the analog-to-digital converter.
  • the three diagrams show how, for a constant input value at the ADU, a reduction of the quantization error and thus an increase in the resolution of the ADC is achieved by varying the gain of the converter. For this purpose, the digital output value ADU from above the analog input voltage U on is plotted.
  • FIG. 3 a shows, by way of example, the characteristic curve of the ADC for a mean amplification.
  • the digital output value of the ADC "ADU off” is plotted against the input voltage of the ADU "U on”.
  • the ADU responds with the same digital output value (5) for the three different input voltages Ua, Ub and Uc.
  • the gain of the ADC increases accordingly.
  • the resulting characteristic is shown in FIG. 3b.
  • the ADU reacts with the digital value 5 for the input voltages Ua and Ub and with the digital value 7 for the input voltage Uc.
  • Fig. 3c the converter characteristic is shown for a low gain of the ADC.
  • the ADU responds with the digital value 3 for the input voltage Ua and the digital value 5 for the input voltages Ub and Uc. If, for each of the three different input voltages (Ua, Ub and Uc), the mean value of the corresponding ADU output is formed, then the mean values (Ua: 4.33, Ub: 5, Uc: 5.66) differ due to the scrambled, ie the ADC gains modified in a suitable sequence, which reduces the average quantization error of the ADC, increases the resolution of the converter and thus can be used to suppress limit cycles in a control loop.
  • the high sampling rate of the ADU can be used to detect the signal form including the zero crossing.
  • Averaging over multiple periods of time with several different ADC gains increases the resolution in terms of amplitude. A change in the oscillator amplitude can thus be detected earlier and leads to an earlier change of the input signal of the controller which can already intervene before a limit cycle arises.
  • Another application for an analog-to-digital converter according to the invention is a digital tracking synchronization PLL as shown below.
  • the frequency with which the various gains of the ADC repeat must be sized to be above the bandwidth of the digital loop. This ensures that the scrambling of the ADC gains does not interfere with the analog quantity to be controlled.
  • a further embodiment of the invention is, as shown in FIG. 2, to use a digital filter in the regulator, which has a zero at the repetition frequency of the ADC gains in order to minimize the disturbing effect of the amplification scrambling on the analog signal to be controlled.
  • a further embodiment of the invention consists of deriving the clock frequency of this filter from the analog oscillation to be regulated, whereby the frequency of the zero point of the digital filter automatically adapts to the repetition frequency of the amplifications and the effect of the filter always remains optimal over temperature and also over life. This is very well suited for a digital PLL, for example, as explained below.
  • a further embodiment of the invention is to scramble the gains of the ADC not only with a single frequency to avoid limit cycles. The timing of the amplitudes of the ADC gain can also be determined by adding different sequences in which the gains at different frequencies are repeated. The resulting sequence of gains then constitutes a frequency mixture of
  • FIG. 4 shows an embodiment of the analog-to-digital converter according to the invention with comparators with variable reference voltage.
  • the exemplified analog-to-digital converter ADU consists of seven comparators
  • reference voltages represent the quantization thresholds with which the input signal U on of the converter is compared.
  • the reference voltages can be generated as follows.
  • the reference voltage of the middle comparator K4 is provided by a reference voltage source U ref.
  • a resistor network consisting of the resistors Rl to R6, is traversed by a current which is composed of the two partial currents I bias and I dice. These currents are provided by current sources which act on the resistor Rl.
  • U_refK2 Uref + (I bias + I_cube) * (R2 + R3).
  • the reference voltages and thus the gains of the ADU can be deliberately scrambled (changed) via the parameter I dc. This can be achieved with an input signal or an Iwc drive circuit (not shown). The input signal or the triggering circuit can be clocked.
  • the scrambling of the reference shown in FIG. voltage can also be used by means of a scrambling current I cube switchable resistors, which are also controllable by means of a drive circuit. After a certain sequence of ADC gains, the gain should average over this entire sequence.
  • This circuit principle is characterized by the very simple feasibility and the very small space requirement. Moreover, this circuit principle can also be applied to fully differential circuit realizations.
  • 5 shows an embodiment of the analog-digital converter according to the invention with comparators with variable reference voltage fully different. The switching elements are known from FIG. 4 and work analogously here.
  • the analog-to-digital converter according to the invention can be designed as a flash ADC and is then clocked as usual in the prior art (not shown) ).
  • Another way to change the gain of the ADC is to change the values of the resistors in the reference divider of the ADC. This can be done by using controlled resistors, such as field effect transistors. This constitutes one and therefore another embodiment of the invention.
  • FIG. 6 shows schematically a digital phase locked loop with an analog-to-digital converter according to the invention.
  • a flash ADC 600 detects at its input the voltage signal 650 of an analogue oscillation.
  • the phase-locked loop PLL further comprises a phase and frequency detector 610, a loop filter 620 a function group 630 with a digital-to-analogue converter (DAU) and a voltage-controlled oscillator (VCO), and a divider 640.
  • the voltage-controlled oscillator (VCO) generates a system clock 635 which is clocked down in divider 640 into a low frequency clock signal 645.
  • the clock signal 645 is supplied to the components of the phase locked loop PLL.
  • the flash ADC 600 is clocked with the clock signal 645, wherein the clock signal has a higher frequency than the voltage signal 650, so that the sampling theorem is satisfied.
  • the phase locked loop PLL synchronizes to the voltage signal 650 of the analog oscillation at the input of the ADC.
  • Digital filters such as the low-pass filter described in FIG. 2 are operated with the system clock 635 derived at the PLL. This changes all filter properties (such as zeros) with the analog vibration 650.
  • the flash ADU according to the invention is particularly suitable for constructing a phase-locked loop, as disclosed in German Offenlegungsschrift DE 10247 996 A1.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention concerne un convertisseur analogique-numérique (ADU) comprenant un signal d'entrée analogique (U_ein) et au moins un seuil de quantification. Cette invention est caractérisée en ce que le convertisseur analogique-numérique (ADU) présente des systèmes pour modifier ledit seuil de quantification.
PCT/EP2005/056670 2005-01-14 2005-12-12 Convertisseur analogique-numerique WO2006074847A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/795,430 US8188900B2 (en) 2005-01-14 2005-12-12 Analog-digital converter
JP2007550724A JP2008527869A (ja) 2005-01-14 2005-12-12 Ａ／ｄ変換器
EP05817220A EP1842289B1 (fr) 2005-01-14 2005-12-12 Convertisseur analogique-numerique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005001733.9 2005-01-14
DE102005001733A DE102005001733A1 (de) 2005-01-14 2005-01-14 Analog-Digital-Umsetzer

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WO2006074847A1 true WO2006074847A1 (fr) 2006-07-20

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EP (1) EP1842289B1 (fr)
JP (1) JP2008527869A (fr)
DE (1) DE102005001733A1 (fr)
WO (1) WO2006074847A1 (fr)

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JP2019169746A (ja) * 2016-07-05 2019-10-03 旭化成エレクトロニクス株式会社 Ｄａ変換装置、ｄａ変換方法、調整装置、および調整方法

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Also Published As

Publication number Publication date
JP2008527869A (ja) 2008-07-24
US8188900B2 (en) 2012-05-29
US20110102215A1 (en) 2011-05-05
EP1842289B1 (fr) 2013-03-13
EP1842289A1 (fr) 2007-10-10
DE102005001733A1 (de) 2006-07-27

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