Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
  • H03M1/1245—Details of sampling arrangements or methods
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking

Definitions

• the present invention relates to a sampling circuit and a test and test equipment for sampling an input force signal that is given.
• the present invention relates to a sampling preparatory ring that generates and generates a sampling preparatory ring using a step-prily cannidida diode.
• the circuit related to the circuit. .
• SSRRDD (Step Prily Canono Lilida Diioode) is used as a circuit circuit for pre-ringing input signal signals. ) Is known (for example, see, for example, patent patent literature reference 11). .
• the circuit circuit here generates a sampling prepa- ration by SSRRDD, and inputs the input by means of a diode bridge etc. This is a circuit that transmits the power signal to the signal. .
• FIG. 55 is a diagram showing an example of the configuration of the conventional sampling pre-ring circuit circuit 220000.
• the transmission line 220000 is a non-recessed circuit 221100, a connected circuit 222200, a transmission transmission path 223300, an SSRRDD 224400, and a daidio bridge. Can be equipped with Gigi 225500. .
• the Papal Lusser 221100 generates the Papal Luth signal in response to the input signal that should be input to the input signal. . .
• the SSRRDD 224400 receives and receives the Papallusus signal, and generates and generates a sampling signal based on the Papallusus signal. . Therefore, the DAIDIO ORDO BRIDGE 225500 receives the input power signal and the corresponding sun signal.
• the pulse signal generated by the pulser 210 is applied to the SRD 240 via the transmission path 230 with a delay amount of tpd, and the pulse signal reaching the SRD 240 is reflected by the SRD 240 and passes through the transmission path 230. Reach capacitor 220.
• the pulse signal reaching the capacitor 220 is inverted and reflected by the capacitor 220 and applied to the SRD 240 via the transmission path 230. That is, a pulse signal and an inverted signal of the pulse signal delayed by 2 tpd from the pulse signal are applied to SRD240.
• SRD240 A sampling pulse having a noise width corresponding to the delay time 2tpd is generated by the transmission path 230.
• Patent Document 1 Japanese Patent Application Laid-Open No. 2004-179912
• the timing at which the SRD outputs the sampling pulse generally depends on the temperature of the SRD.
• the period from when the SRD240 receives the pulse signal to when the sampling pulse is output depends on the temperature of the SRD240.
• the period from when the pulse signal is received until the sampling noise is output is the force determined by the so-called accumulation time ts of SRD240 (the time during which reverse current is flowing), because this accumulation time depends on the temperature of SRD240. is there.
• the temperature of the SRD 240 varies depending on the operating frequency, the surrounding environment, and the like. For this reason, in the conventional sampling circuit, an error occurs in the timing at which the SRD outputs the sampling pulse, and it is difficult to accurately sample the input signal.
• an object of the present invention is to provide a sampling circuit that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
• the dependent claims define further advantageous specific examples of the present invention.
• a sampling circuit that samples a given input signal, which generates a pulse signal according to the timing at which the input signal should be sampled, A step recovery diode that outputs a sampling pulse in response to a pulse signal, a detector that detects the value of the input signal in response to a sampling pulse, a temperature detection circuit that detects the temperature in the vicinity of the step recovery diode, and a temperature detection
• a sampling circuit includes a temperature compensation unit that controls the timing at which the step-cancelling diode outputs a sampling pulse based on the temperature detected by the circuit.
• the temperature compensation unit may control the bias voltage applied to the step recovery diode based on the temperature detected by the temperature detection circuit.
• the temperature compensation circuit detects the temperature compensation circuit
• the bias voltage applied to the step recovery diode can be decreased when the measured temperature becomes high, and the bias voltage applied to the step recovery diode can be increased when the temperature detected by the temperature detection circuit becomes low. .
• the temperature compensation unit includes a temperature table indicating a relationship between the temperature of the step recovery diode and the phase of the sampling pulse output from the step recovery diode, a bias voltage applied to the step recovery diode, and a step recovery diode. Store in advance a bias table indicating the relationship with the phase of the sampling pulse output by the diode.
• the force recovery terminal of the step recovery diode is grounded, and the sampling circuit has one end connected to the pulsar and connected to the anode terminal of the multi-end force S-step Ricano diode, and a transmission path having a fixed delay time.
• the sampling circuit has one end connected to the pulsar and connected to the anode terminal of the multi-end force S-step Ricano diode, and a transmission path having a fixed delay time.
• a capacitor provided between one end of the transmission path and the ground potential!
• the sampling circuit further includes a transformer that transmits the sampling panel to the detector, and the detector includes a diode bridge that detects the value of the input signal using the normal output and the inverted output of the transformer as sampling pulses. Oh ,.
• a test apparatus for testing a device under test, a pattern generation unit for generating a test pattern for testing the device under test, and a test signal corresponding to the test pattern.
• a waveform shaping unit that generates a signal and a determination unit that determines pass / fail of the device under test based on an output signal output from the device under test.
• the determination unit includes a sampling circuit that samples the output signal. The sampling circuit detects the value of the output signal according to the pulser that generates the pulse signal according to the timing at which the output signal should be sampled, the stepped cannula diode that outputs the sampling pulse according to the pulse signal, and the sampling pulse.
• Detector a temperature detection circuit that detects the temperature in the vicinity of the step recovery diode, and a temperature detection circuit. Based on the out temperature, the step recovery diode to provide a test apparatus and a temperature compensating unit for controlling the timing of outputting the sampling Bruno Angeles.
• the invention's effect [0017] According to the present invention, it is possible to compensate for the phase shift of the sampling pulse due to temperature fluctuation and to sample the input signal with high accuracy.
• FIG. 1 is a diagram showing an example of a configuration of a sampling circuit 100 according to an embodiment of the present invention.
• FIG. 2 is a diagram showing an example of a waveform of a pulse signal input to the SRD 26 and a sampling pulse output from the SRD 26.
• Figure 2 (a) shows the waveform when there is no temperature fluctuation
• Figure 2 (b) shows the waveform when there is temperature fluctuation
• Figure 2 (c) shows the bias when there is temperature fluctuation. The waveform when the voltage is controlled is shown.
• FIG. 3 is a diagram for explaining the operation of a control unit 20.
• Fig. 3 (a) shows the relationship between the temperature of SRD26 and the phase of the sampling pulse output by SRD26
• Fig. 3 (b) shows the bias voltage applied to SRD26 and the phase of the sampling pulse output by SRD26. Shows the relationship.
• FIG. 4 is a diagram showing another example of the configuration of the temperature compensation unit 16.
• FIG. 5 is a diagram showing an example of a configuration of a conventional sampling circuit 200.
• FIG. 1 is a diagram showing an example of the configuration of the sampling circuit 100 according to the embodiment of the present invention.
• the sampling circuit 100 is a circuit that samples a given input signal.
• the sampling circuit 100, the capacitor 12, the temperature compensation unit 16, the capacitor 22, the transmission path 24, and A sampling head 30 is provided.
• the pulsar 10 generates a pulse signal according to the timing at which the input signal should be sampled.
• the capacitor 12 passes the high frequency component of the signal output from the pulser 10. That is, the capacitor 12 removes the DC component output from the pulser 10 and passes the pulse component.
• the transmission path 24 has one end connected to the capacitor 12 and the other end connected to the sampling head 30. That is, the transmission path 24 receives the Norse signal generated by the pulser 10 via the capacitor 12 and supplies it to the sampling head 30.
• the transmission path 24 has a transmission delay time tpd. That is, the transmission path 24 delays the pulse signal by the delay time tpd and supplies it to the sampling head 30.
• Capacitor 22 is provided between one end of transmission path 24 connected to capacitor 12 and the ground potential.
• the pulse signal supplied from the transmission path 24 to the sampling head 30 is reflected by the anode terminal of the step recovery diode (SRD) 26 and input to the capacitor 22 through the transmission path 24.
• the pulse signal is inverted and reflected by the capacitor 22 and supplied to the sampling head 30 via the transmission path 24. That is, the sampling head 30 is supplied with a composite wave of a pulse signal and a signal obtained by inverting the pulse signal by delaying it by 2tpd.
• the sampling head 30 has an SRD 26, a transformer 28, a detector 34, and a temperature detection circuit 32.
• the SRD 26 generates and outputs a sampling pulse based on the above synthesized wave.
• the detector 34 has, for example, a diode bridge circuit and the like, and detects the value of the applied input signal in accordance with the applied sampling pulse.
• the transformer 28 transmits the sampling pulse output from the SRD 26 to the detector 34.
• the detector 34 has a diode bridge circuit that detects the value of the input signal using the normal output and the inverted output of the transformer 28 as sampling pulses.
• the temperature detection circuit 32 is provided in the vicinity of the SRD 26, and detects the temperature in the vicinity of the SRD 26.
• the temperature detection circuit 32 may include an element having a temperature-dependent characteristic.
• the temperature detection circuit 32 includes, for example, a diode, an SRD, a thermistor, and the like.
• Temperature detection circuit 32 Has a diode or SRD the diode or SRD is provided in the vicinity of SRD26 and detects the temperature by detecting the forward voltage of the diode or the like.
• the temperature detection circuit 32 has a thermistor the thermistor is provided in the vicinity of the SRD 26 and detects the temperature by detecting the resistance of the thermistor.
• the temperature compensator 16 controls the timing at which the SRD 26 outputs the sampling pulse based on the temperature detected by the temperature detection circuit 32.
• the temperature compensator 16 may control the timing of the sampling pulse by controlling the bias voltage applied to the SRD 26 to control the timing of the sampling pulse.
• the timing of the sampling pulse may be controlled by controlling the phase of the pulse signal applied to SRD26.
• the temperature compensation unit 16 includes a power source 18 and a control unit 20.
• Power supply 18 applies a bias voltage to SRD26.
• the force sword terminal of the SRD 26 is grounded, and the power source 18 applies a bias voltage to the anode terminal of the SRD 26 via the transmission path 24.
• the control unit 20 controls the bias voltage generated by the power supply 18 based on the temperature detected by the temperature detection circuit 32. Since the timing at which the SRD 26 outputs the sampling pulse varies depending on the bias voltage applied, the control unit 20 generates the power supply 18 based on the temperature fluctuation that should compensate for the deviation in the sampling pulse output timing due to the temperature fluctuation. Control the bias voltage. For example, the control unit 20 reduces the bias voltage generated by the power supply 18 when the temperature detected by the temperature detection circuit 32 becomes high, and when the temperature detected by the temperature detection circuit 32 becomes high or low. The bias voltage generated by the power supply 18 is increased.
• FIG. 2 is a diagram illustrating an example of a pulse signal input to the SRD 26 and a sampling pulse waveform output from the SRD 26.
• Fig. 2 (a) shows the waveform when there is no temperature fluctuation
• Fig. 2 (b) shows the waveform when there is temperature fluctuation
• Fig. 2 (c) shows the bias when there is temperature fluctuation. The waveform when the voltage is controlled is shown.
• Fig. 2 (b) when temperature fluctuation occurs in SRD26, when there is no temperature fluctuation, On the other hand, the phase of the sampling pulse is shifted.
• the control unit 20 calculates the phase shift based on the temperature detected by the temperature detection circuit 32. Then, the bias voltage generated by the power supply 18 is controlled so as to compensate for the calculated phase shift. By such control, as shown in Fig. 2 (c), the phase shift of the sampling noise due to temperature fluctuation can be compensated.
• FIG. 3 is a diagram for explaining the operation of the control unit 20.
• Figure 3 (a) shows the relationship between the temperature of SRD26 and the phase of the sampling pulse output by SRD26
• Figure 3 (b) shows the bias voltage applied to SRD26 and the sampling pulse output by SRD26. It is a figure which shows the relationship with the phase of.
• the control unit 20 calculates the relationship between the temperature of the SRD26 and the phase of the sampling pulse output from the SRD26, the bias voltage applied to the SRD26, and the phase of the sampling pulse output from the SRD26.
• the bias table shown is preferably stored in advance.
• the control unit 20 detects the phase of the sampling pulse corresponding to the temperature detected by the temperature detection circuit 32 in the temperature table. Then, the phase shift amount of the sampling pulse at the temperature is calculated. In the bias table, a bias voltage for compensating the calculated shift amount is detected, and the bias voltage generated by the power supply 18 is controlled.
• the optimum bias for compensating the temperature of SRD26 and the amount of phase shift at the temperature is shown.
• the voltage is uniquely determined.
• the control unit 20 may store in advance the relationship between the temperature of the SRD 26 and the optimum bias voltage for compensating the amount of sampling pulse phase shift at that temperature.
• the control unit 20 may generate and store a temperature table and a bias table! /.
• control unit 20 has means for measuring the phase of the sampling pulse. Then, a temperature table is generated by measuring the phase of the sampling pulse with respect to each temperature, and a bias table is generated by measuring the phase of the sampling pulse with respect to each noise voltage. Good. As a result, for example, even if the characteristics of SRD26 vary, the phase of the sampling pulse can be compensated accurately. Can do.
• the temperature detection circuit 32 may notify the control unit 20 of a characteristic value such as a forward voltage measured through a diode, SRD, or the like. In this case, the control unit 20 calculates the temperature of S RD26 based on the characteristic value. At this time, it is preferable that the control unit 20 is given a relationship between the characteristic value and the temperature in advance.
• FIG. 4 is a diagram illustrating another example of the configuration of the temperature compensation unit 16.
• the temperature compensation unit 16 includes an analog digital converter (ADC) 36, an arithmetic circuit 38, a memory 40, and a digital analog converter (DAC) 42.
• ADC analog digital converter
• DAC digital analog converter
• the temperature compensation unit 16 receives a characteristic value such as a forward voltage measured by the temperature detection circuit 32.
• the ADC 36 converts the received characteristic value into digital data.
• the arithmetic circuit 38 calculates a bias voltage to be applied to the SRD 26 based on the digital data.
• the memory 40 stores in advance information indicating the relationship between the characteristic value and the bias voltage.
• the memory 40 shows the relationship between the characteristic value and the temperature of the SRD 26, the relationship between the temperature of the SRD 26 and the phase shift amount of the sampling pulse, and the relationship between the phase shift amount of the sampling pulse and the bias voltage.
• the arithmetic circuit 38 detects a bias voltage corresponding to the received characteristic value based on these relationships.
• the memory 40 may store in advance a correction function for calculating an inverse characteristic of the characteristic value.
• the arithmetic circuit 38 uniquely determines the relationship between the bias voltage to be applied to the SRD 26 and the characteristic value by correcting the characteristic value with the correction function.
• the DAC 42 generates a voltage according to the bias voltage value calculated by the arithmetic circuit 38 and applies it to the SRD 26. With such a configuration, a bias voltage corresponding to the detected temperature fluctuation can be applied to the SRD 26 to compensate for the phase shift of the sampling pulse.
• the sampling circuit 100 can be used in a test apparatus such as a semiconductor circuit.
• the test apparatus includes a pattern generation unit that generates a test pattern for testing the circuit under test, a waveform shaping unit that generates a test signal corresponding to the test pattern, and an output output by the circuit under test. And a determination unit that determines whether the circuit under test is good or bad based on the signal.
• the determination unit has a sampling circuit 100 for sampling the output signal, and compares the data sampled from the output signal with the expected value data given from the pattern generation unit. Judge the quality of the. According to such a test apparatus, since the output signal can be sampled with high accuracy, the quality of the circuit under test can be determined with high accuracy.
• the sampling circuit of the present invention it is possible to compensate for the phase shift of the sampling pulse due to temperature fluctuation and to sample the input signal with high accuracy.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Manipulation Of Pulses (AREA)
• Electronic Switches (AREA)
• Analogue/Digital Conversion (AREA)
• Tests Of Electronic Circuits (AREA)

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• 2004
  • 2004-11-11 JP JP2004328262A patent/JP4445836B2/ja not_active Expired - Fee Related
• 2005
  • 2005-10-27 WO PCT/JP2005/019806 patent/WO2006051694A1/ja not_active Ceased
  • 2005-10-27 KR KR1020077011546A patent/KR101174935B1/ko not_active Expired - Lifetime
  • 2005-10-27 CN CNA2005800382518A patent/CN101057402A/zh active Pending
  • 2005-10-27 EP EP05805332A patent/EP1816745A1/en not_active Withdrawn
  • 2005-11-09 TW TW094139224A patent/TWI369076B/zh active
  • 2005-11-10 US US11/271,132 patent/US7208982B2/en not_active Expired - Lifetime

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