WO2005109499A2 - Halbleiterbauteil mit einem umverdrahtungssubstrat und verfahren zur herstellung desselben - Google Patents
Halbleiterbauteil mit einem umverdrahtungssubstrat und verfahren zur herstellung desselben Download PDFInfo
- Publication number
- WO2005109499A2 WO2005109499A2 PCT/DE2005/000840 DE2005000840W WO2005109499A2 WO 2005109499 A2 WO2005109499 A2 WO 2005109499A2 DE 2005000840 W DE2005000840 W DE 2005000840W WO 2005109499 A2 WO2005109499 A2 WO 2005109499A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor
- semiconductor component
- rewiring
- external contact
- underside
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 233
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000463 material Substances 0.000 claims abstract description 10
- 150000001875 compounds Chemical class 0.000 claims abstract description 6
- 230000008901 benefit Effects 0.000 claims description 23
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 239000002131 composite material Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 description 49
- 230000008569 process Effects 0.000 description 4
- 239000011888 foil Substances 0.000 description 3
- YQOLEILXOBUDMU-KRWDZBQOSA-N (4R)-5-[(6-bromo-3-methyl-2-pyrrolidin-1-ylquinoline-4-carbonyl)amino]-4-(2-chlorophenyl)pentanoic acid Chemical compound CC1=C(C2=C(C=CC(=C2)Br)N=C1N3CCCC3)C(=O)NC[C@H](CCC(=O)O)C4=CC=CC=C4Cl YQOLEILXOBUDMU-KRWDZBQOSA-N 0.000 description 2
- 229940125844 compound 46 Drugs 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0101—Neon [Ne]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01052—Tellurium [Te]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Definitions
- the invention relates to a semiconductor component with a rewiring substrate, in particular the invention relates to a component arrangement for stacking semiconductor components with a rewiring substrate, which has an upper side for a semiconductor component to be stacked and a lower side for the attachment of external contacts.
- external contacts are arranged on the underside of the rewiring substrate, and at least one semiconductor chip, for example a memory component, such as a DRAM, is arranged on the top of the rewiring substrate in the center of the top of the rewiring substrate.
- a memory component such as a DRAM
- conventional semiconductor components with BGA or LGA housings are provided with additional flexible rewiring foils which are larger in area than the semiconductor components to be stacked and which protrude beyond the edge of the semiconductor components, so that they are bent and over towards a semiconductor component of a semiconductor component stack arranged underneath the flexible film can be electrically connected to the semiconductor component arranged underneath.
- a semiconductor module with semiconductor components stacked in this way has the disadvantage that the semiconductor components cannot be stacked with the smallest possible space requirement, especially since the bent redistribution foil also requires a bending radius that cannot be undercut without risking microcracks in the redistribution lines arranged on the redistribution foil.
- such a semiconductor module has the disadvantage that the thickness of each stacking stage is composed of the thickness of the semiconductor chip plus the not inconsiderable thickness of the rewiring substrate.
- the object of the invention is to provide a semiconductor component with rewiring substrate and a method for producing the same, which can be stacked on one another in any number to form a semiconductor module. Furthermore, it is an object of the invention that this stackable component can be combined with differently constructed basic components and with differently structured top semiconductor components to form a semiconductor module. In addition, it is an object of the invention to provide a semiconductor component with a rewiring Specify substrate with which a stack is not limited to a few predetermined patterns of semiconductor components, but in which the arrangement and assignment of connecting external contacts can be varied as desired. It is also an object of the invention to minimize the space requirement and the area requirement of a semiconductor module.
- a semiconductor component with a rewiring substrate as a stacking element for a semiconductor component stack is created.
- the rewiring substrate forms an underside and an upper side of the semiconductor component.
- external contact spots are arranged at least in an edge region of the rewiring substrate, which are electrically connected via vias through the rewiring substrate.
- the through contacts are arranged through the rewiring substrate in a first plastic mass and surround with this first plastic mass, a semiconductor chip arranged in the volume of the rewiring substrate and with its rear side and its edge sides embedded in a second plastic mass of the rewiring substrate.
- the underside of the rewiring substrate with its external contact pads and the active top side of the semiconductor chip with its contact areas have a common coplanar area.
- This semiconductor component has the advantage that, as a stacking element, it only has the thickness of a rewiring substrate with through contacts, since the semiconductor chip has the volume of Rewiring substrate is arranged.
- Another advantage results from the coplanar surface, which is formed by the active top side of the semiconductor chip and by the bottom side of the rewiring substrate composed of two plastic materials. Any wiring can thus be carried out on this underside by applying a correspondingly structured rewiring layer between the contact surfaces of the semiconductor chip and the external contact pads.
- the upper side of the semiconductor component which is formed by the upper side of the rewiring substrate and has external contact pads which can be connected to the contact areas of the semiconductor chip on the underside of the rewiring substrate via vias and via a U wiring structure.
- the upper external contact surfaces can be coated with a solder layer in order to stack further semiconductor components, as well as semiconductor components of the same type.
- an intermediate connection substrate or an intermediate connection film is provided in previous stacks in order to enable stacking of semiconductor components, such intermediate connection parts can be omitted in the stacking element according to the invention. This results in a higher complexity and a higher stack density.
- the function of such an interconnection substrate, or of such an interconnection film, is assumed here by the rewiring structure that can be attached to the coplanar surface on the underside of the rewiring substrate or the semiconductor component,
- the coplanar surface is initially covered by an insulation layer, the windows to the contact surfaces of the semiconductor chip and to the external pads on the underside of the rewiring substrate.
- an insulation layer has the advantage that it can bridge transitions from the semiconductor chip material of the active upper side of the semiconductor chip to the first and second plastic materials of the rewiring substrate in the plane of the coplanar surface and can increase the electrical dielectric strength.
- the windows to the contact areas and to the external contact spots can be introduced into the insulation layer by laser ablation or by photolithographic processes with subsequent dry or wet etching technology.
- the structured rewiring layer can be applied on the insulation layer and establish the connection to the outer contact areas of the semiconductor chip and the contact pads on the underside of the rewiring substrate.
- the structured rewiring layer can also be applied directly to the coplanar surface, especially since the top side of the semiconductor chip has an insulating passivation layer and the first and second plastic compounds are insulating.
- the structured rewiring layer either allows only the edge regions of the semiconductor component to be equipped with external contacts on the underside, or it is also possible to distribute external contacts over the entire underside of the semiconductor component. The same advantage also results for the upper side of the semiconductor component if a corresponding structured rewiring layer is provided there.
- Such a structured redistribution layer can finally be covered by a solder resist layer, which leaves access to the external contact pads on the underside of the redistribution substrate.
- the structuring of the solder stop layer can in turn be carried out using photoresist measures.
- a structured rewiring layer is provided on the upper side with an arrangement pattern of external contact patches in such a way that they are congruent with an arrangement pattern of external contact patches or external contacts of a semiconductor component to be stacked, in order to enable an electrical connection.
- the semiconductor component according to the invention thus has the advantage that any arrangement pattern for semiconductor components to be stacked can be provided on its upper side.
- a semiconductor component module can be realized which has a stack of the semiconductor components described above as stack elements.
- the stacking elements can be of completely identical design and have external contacts on the edge regions of the respective rewiring substrates, the bottom semiconductor component as the semiconductor base component having an arrangement pattern of external contacts on its underside which corresponds to the arrangement patterns of surface-mountable semiconductor components.
- the top side of the semiconductor component module can have a structured conversion have wire layer with which it is possible to arrange both passive and surface-mountable active components on the uppermost semiconductor component of the semiconductor component stack. These components are electrically connected to the semiconductor components of the semiconductor component module arranged underneath.
- a semiconductor component with an internal chip stack composed of two semiconductor chips as the uppermost stacked semiconductor component.
- this internal semiconductor chip stack at least one semiconductor chip is preferably provided with flip-chip contacts, while the second semiconductor chip with the plastic mass that surrounds the semiconductor chip stack forms a coplanar surface on which a correspondingly structured rewiring layer is provided.
- Another aspect of the invention relates to a benefit for a plurality of semiconductor components which are provided on the benefit in corresponding component positions, the component positions being arranged on a removable carrier film.
- Such a use for several semiconductor components of the same type, which can be used as stacking elements due to the structure according to the invention, can be manufactured and offered as a composite plate.
- This composite panel can, for example, be divided into individual stackable semiconductor components by the end user.
- a method for producing a benefit has the following method steps. First, a carrier film is provided on a carrier. This carrier can simultaneously be a mold half of a mold, if it is intended to realize the benefits by molding. A molded part of a dispensing process can also be provided as the carrier, the carrier film being inserted into the dispensing mold. A plastic frame that has already been prepared in a parallel process and has a first plastic mass is then applied to the carrier film. This plastic frame has a plurality of component positions arranged in rows and columns, and surrounds each of the component positions with a corresponding frame.
- the plastic frame encloses a free surface of the carrier film in the middle of the component positions.
- a semiconductor chip is applied to this area within the plastic frame while fixing its active top side to the carrier film.
- the plastic frame can then be filled in a second plastic compound by embedding the back and the edge sides of the semiconductor chip, so that a coplanar surface is created on the underside towards the carrier film and a flat surface forms the top of the panel.
- a structured rewiring layer can be applied to the coplanar surface, the contact surfaces of the active top of the half conductor chips with external contact patches of the plastic frame are connected.
- This method has the advantage that a benefit is created in the form of a composite plate, in which many semiconductor components are simultaneously available as stacking elements with the resulting benefit in a parallel production method.
- Another advantage is that the top of this panel, which only has external contact pads in the component positions, can be provided with a further rewiring structure in order to provide evenly distributed external contact pads on both the bottom and the top.
- stacking can not only create a connection between semiconductor components in the areas of the semiconductor components, but the entire surface of a component position is available for arranging external contacts, both on the bottom and on the top stands .
- the semiconductor chips are applied to the carrier film within the plastic frame by means of adhesive technology.
- the carrier film can have a corresponding adhesive layer.
- the external contact spots can also be reinforced in order to provide semiconductor components for surface mounting, or the external contacts in the form of solder balls are already applied to the respective external contact spots and only then is the benefit separated into individual semiconductor components.
- redistribution layers on the underside and / or on the top side can be used to create contact pad arrangements which make it possible to stack different semiconductor components with corresponding external contact patterns on this semiconductor component, which consists of a redistribution substrate.
- the invention enables stacking of semiconductor housings which are independent of one another.
- a housing technology is modified and a previously unstructured plastic frame material is provided with through contacts and external contact spots, so that a universal stacking element consisting of a rewiring substrate with a semiconductor chip housed in the volume is created.
- This stacking element is a fully-fledged semiconductor component and can also be sold as a semiconductor base component. Since this component has contact patches on both its top side and on its bottom side, it can be assembled with any other semiconductor components or housings to form a stack or a semiconductor module.
- the subject matter of the invention has the following advantages:
- the semiconductor components according to the invention have an improved electrical design, an improved form factor, a higher wiring density and reliable producibility of large-area use for several of the components according to the invention in corresponding semiconductor component positions.
- Figure 1 shows a schematic cross section through a semiconductor device according to the invention
- Figure 2 shows a schematic cross section of a plastic frame of a single component position of a panel
- FIG. 3 shows a schematic cross section of a plastic frame according to FIG. 1 with a semiconductor chip
- FIG. 4 shows a schematic cross section of a plastic frame according to FIG. 3 with a filled-out recess to form a composite panel
- FIG. 5 shows a schematic cross section of a composite panel according to FIG. 4 with a rewiring layer on its underside
- FIG. 6 shows a schematic cross section of a finished semiconductor component according to FIG. 1;
- FIG. 7 shows a schematic cross section through a semiconductor component module with two semiconductor components according to the invention in accordance with a first embodiment of the invention
- FIG. 8 shows a schematic cross section through a semiconductor component module with two stacked semiconductor components and a passive component according to a second embodiment of the invention
- FIG. 9 shows a schematic cross section through a semiconductor component module with two stacked semiconductor components according to a third embodiment of the invention.
- FIG. 10 shows a schematic cross section through a semiconductor component module with three stacked semiconductor components according to a fourth embodiment of the invention.
- FIG. 1 shows a schematic cross section through a semiconductor device 10 according to the invention.
- the semiconductor device 10 has a plastic frame 41 made of a first plastic mass 42 in an edge region 11 of the semiconductor component 10 and a central region 20 made of a second plastic mass 46.
- the thickness D of the component corresponds approximately to the thickness d of a rewiring substrate, which is formed by the plastic frame 41 and the central region 20.
- the rewiring substrate 1 has a coplanar surface 3, which is formed from the active top side 15 of a semiconductor chip 6 arranged in the central region 20 and the undersides of the plastic materials 42 and 46.
- the semiconductor chip 6 in the central region 20 of the semiconductor component 10 is surrounded by the second plastic compound 46 on its rear side 14 and on its edge sides 12 and 13. Only the active top side 15 with the contact surface 5 is free of plastic material, so that access to the contact surface 5 from the coplanar surface 3 is possible.
- a three-layer redistribution layer 18 is arranged on the underside of the redistribution substrate 1. These three layers are made up of three layers.
- an insulation layer 16 is applied as the first layer on the coplanar surface 3.
- the insulation layer 16 has windows 17. These windows 17 provide access to the contact area 5 on the active top side 15 of the semiconductor chip 6 and one Allow access to the external contact patches 9 of the plastic frame 41.
- a rewiring structure 21 Arranged on the insulation layer 16 as a second layer is a rewiring structure 21 which has U-wiring lines 19 which connect the external contact pads 9 to external contacts 22 and to the contact areas 5.
- the third and final layer of the rewiring layer 18 forms a solder stop layer 24, which enables external contacts 22 to access corresponding external contact spots of the rewiring structure via corresponding windows in the solder stop layer 24.
- Further semiconductor components can be stacked on this component 10 at least in the edge regions 11 by contacting the external contact pads.
- FIGS. 2 to 5 show schematic cross sections through components of individual process stages in the production of a semiconductor component 10 according to FIG. 1.
- FIG. 2 shows a schematic cross section of a plastic frame 41 of an individual component position 45 of a panel.
- a carrier 39 is equipped with a carrier film 38 and either individual plastic frames or a large-area plastic frame 41 with individual component positions 45 are glued onto this carrier film 38.
- These plastic frames 41 already have 2 external contact spots 9 on their undersides.
- Through-contacts 8 are embedded in their volume, which electrically connect the external contact patches 9 to the external contact patches 7 on the upper side 5 of the plastic frame 41 and thus form a three-dimensional first rewiring structure 43.
- FIG. 3 shows a schematic cross section of a plastic frame 41 according to FIG. 1 with a semiconductor chip 6.
- the central region 20 of the component position 45 shown in FIG. 2 is surrounded by the plastic frame 41 and allows access to an exposed surface 44 of the carrier film 38.
- a semiconductor chip 6 with its active upper side 15 is now glued onto the carrier film 38 in the central region 20, so that the contact surface 5 of the semiconductor chip 6 lies on the carrier film 38.
- the bottom 2 of the plastic frame 41 and the active top 15 of the semiconductor chip 6 are aligned coplanar.
- FIG. 4 shows a schematic cross section of a plastic frame 41 according to FIG. 3 with a filled-out recess to form a composite plate 47.
- the semiconductor chip 6 with its rear side 14 and its edge sides 12 and 13 embedded in a second plastic compound 46, which fills the central region 20. Since this filling is carried out not only in the component position 45 shown here, but simultaneously in all the component positions of a panel, a composite plate 47 is created which is dimensionally stable and self-supporting.
- the carrier film 38 is pulled off from this dimensionally stable and self-supporting composite plate 47, as shown in FIG. 4, so that the underside 2 now represents a coplanar surface 3 on which the external contact spots 9 and the contact surface 5 are arranged.
- FIG. 5 shows a schematic cross section of a composite plate 47 according to FIG. 4 with a redistribution layer 18 on its underside 2.
- This three-layer redistribution layer 18 is applied to the coplanar upper side 3 of the redistribution substrate 1 after the backing film has been pulled off.
- this redistribution layer 18 is a three-layer redistribution layer 18 composed of an insulation layer 16, a redistribution wiring structure 21 and a solder stop layer 24.
- FIG. 6 shows a schematic cross section of a finished semiconductor component 10 according to FIG. 1.
- the component position 45 shown in FIG. 5 is cut out of the composite plate and external contacts 22 are attached at the provided locations on the underside.
- An alternative possibility is to attach the external contacts 22 to each of the component positions 45 of the panel, as shown in FIG. 5, and then to split the panel into individual semiconductor components 10.
- This semiconductor component 10 shown in FIG. 6 can be used as the semiconductor base component 27 of a stack.
- FIG. 7 shows a schematic cross section through a semiconductor component module 37 with two semiconductor components 10 and 50 according to the invention in accordance with the first embodiment of the invention.
- the external contact pads 9 on the underside of the stacked semiconductor component 50 are reinforced by a solder layer 48 and then soldered onto the external contact pads 7 on the top side 4 of the semiconductor component 10. Since the external contact pads 9 are connected to the contact areas 5 of the semiconductor chip 6 of the stacked semiconductor component 50 via the redistribution layer 18 of the stacked semiconductor component 50, there is also a connection to the contact areas 5 of the semiconductor chip 6 of the semiconductor base component 27. While the external contacts 22 of the semiconductor base component 27 are uniformly over the underside is distributed, the coupling between the stacked semiconductor component 50 and the base semiconductor component 27 takes place only via the edge regions 11, which are formed by the plastic frame 41 of each semiconductor component 10 and 50.
- FIG. 8 shows a schematic cross section through a semiconductor component module 37 with freely stacked semiconductor components 10 and 51 of a second embodiment of the invention.
- both the semiconductor base component 27 and the stacked semiconductor component 51 have an upper rewiring structure 23 on the upper side 4 of the rewiring substrate 1. It is therefore possible to on the other hand, to provide the stacked semiconductor component 51 with external contacts 22, which are arranged distributed over the entire underside 2 of the rewiring substrate 1.
- passive components 29 and surface-mounted active components 31 can be arranged on the top side 28 of the semiconductor component stack 30, which require a completely different arrangement pattern for the external contact pads 7 on the top side 28 of the semiconductor module 30.
- FIG. 9 shows a cross section through a semiconductor component module 37 from a semiconductor stack 35 with two stacked semiconductor components 10 and 52 of a third embodiment of the invention.
- the base semiconductor component 27 corresponds to the semiconductor component 10 shown in FIG. 1
- the stacked semiconductor component 52 differs from the previously stacked semiconductor components 50 and 51 in the previous figures in that an internal chip stack 32 with a lower semiconductor chip 33, the passive semiconductor component Rear is arranged on a rewiring plate 49 is provided.
- This lower semiconductor chip 33 is connected to the rewiring structure of a rewiring plate 49 of the stacked semiconductor component 52 via bonding wires 55 and carries on its top side the stacked semiconductor chip 34, which is connected via flip chip contacts 36 to contact areas 5 of the lower semiconductor chip 33.
- This semiconductor chip module 37 shows how flexibly the stacking element or the semiconductor base component 27 can be used.
- FIG. 10 shows a schematic cross section through a semiconductor component module 37 from a semiconductor component stack 40 with three stacked semiconductor components 10, 53 and 54 according to a fourth embodiment of the invention.
- a semiconductor component stack 40 consisting of three almost identical half 1 has the advantage that each module capacity can be achieved relatively inexpensively. Especially since the stack can be supplemented with other semiconductor components.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/593,150 US7545047B2 (en) | 2004-05-06 | 2006-11-06 | Semiconductor device with a wiring substrate and method for producing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004022884.1 | 2004-05-06 | ||
DE102004022884A DE102004022884B4 (de) | 2004-05-06 | 2004-05-06 | Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/593,150 Continuation US7545047B2 (en) | 2004-05-06 | 2006-11-06 | Semiconductor device with a wiring substrate and method for producing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005109499A2 true WO2005109499A2 (de) | 2005-11-17 |
WO2005109499A3 WO2005109499A3 (de) | 2006-01-19 |
Family
ID=34969390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2005/000840 WO2005109499A2 (de) | 2004-05-06 | 2005-05-03 | Halbleiterbauteil mit einem umverdrahtungssubstrat und verfahren zur herstellung desselben |
Country Status (3)
Country | Link |
---|---|
US (1) | US7545047B2 (de) |
DE (1) | DE102004022884B4 (de) |
WO (1) | WO2005109499A2 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1703558A2 (de) * | 2005-03-15 | 2006-09-20 | Shinko Electric Industries Co., Ltd. | Leiterplatte mit eingebettetem Halbleiterchip, eingebetteter Verstärkung und Herstellungsmethode dafür |
EP2184777A1 (de) * | 2008-11-07 | 2010-05-12 | General Electric Company | Verbindungsstruktur |
Families Citing this family (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005043557B4 (de) * | 2005-09-12 | 2007-03-01 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite |
US20080258286A1 (en) * | 2007-04-23 | 2008-10-23 | Texas Instruments Incorporated | High Input/Output, Low Profile Package-On-Package Semiconductor System |
DE102007022959B4 (de) * | 2007-05-16 | 2012-04-19 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleitervorrichtungen |
US7863088B2 (en) | 2007-05-16 | 2011-01-04 | Infineon Technologies Ag | Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound |
US20080318054A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Low-temperature recoverable electronic component |
US9610758B2 (en) * | 2007-06-21 | 2017-04-04 | General Electric Company | Method of making demountable interconnect structure |
US20080318055A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Recoverable electronic component |
US9953910B2 (en) * | 2007-06-21 | 2018-04-24 | General Electric Company | Demountable interconnect structure |
US20080318413A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Method for making an interconnect structure and interconnect component recovery process |
US20080313894A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Method for making an interconnect structure and low-temperature interconnect component recovery process |
WO2009001280A2 (en) * | 2007-06-27 | 2008-12-31 | Koninklijke Philips Electronics N.V. | A method for the production of a microelectronic sensor device |
US20090028491A1 (en) | 2007-07-26 | 2009-01-29 | General Electric Company | Interconnect structure |
KR101519062B1 (ko) | 2008-03-31 | 2015-05-11 | 페어차일드코리아반도체 주식회사 | 반도체 소자 패키지 |
TWI573201B (zh) * | 2008-07-18 | 2017-03-01 | 聯測總部私人有限公司 | 封裝結構性元件 |
JP5568467B2 (ja) * | 2008-08-28 | 2014-08-06 | パナソニック株式会社 | 半導体装置 |
US7948064B2 (en) | 2008-09-30 | 2011-05-24 | Infineon Technologies Ag | System on a chip with on-chip RF shield |
US8889548B2 (en) | 2008-09-30 | 2014-11-18 | Infineon Technologies Ag | On-chip RF shields with backside redistribution lines |
US8063469B2 (en) | 2008-09-30 | 2011-11-22 | Infineon Technologies Ag | On-chip radio frequency shield with interconnect metallization |
US8178953B2 (en) | 2008-09-30 | 2012-05-15 | Infineon Technologies Ag | On-chip RF shields with front side redistribution lines |
US8169059B2 (en) | 2008-09-30 | 2012-05-01 | Infineon Technologies Ag | On-chip RF shields with through substrate conductors |
US20100133682A1 (en) | 2008-12-02 | 2010-06-03 | Infineon Technologies Ag | Semiconductor device |
US8354304B2 (en) * | 2008-12-05 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant |
US7642128B1 (en) | 2008-12-12 | 2010-01-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US9293401B2 (en) | 2008-12-12 | 2016-03-22 | Stats Chippac, Ltd. | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) |
US9064936B2 (en) | 2008-12-12 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US8592992B2 (en) | 2011-12-14 | 2013-11-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP |
US9082806B2 (en) | 2008-12-12 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
JP2010272734A (ja) * | 2009-05-22 | 2010-12-02 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8021930B2 (en) * | 2009-08-12 | 2011-09-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming dam material around periphery of die to reduce warpage |
US9230898B2 (en) * | 2009-08-17 | 2016-01-05 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US8143097B2 (en) | 2009-09-23 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
US9875911B2 (en) * | 2009-09-23 | 2018-01-23 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interposer with opening to contain semiconductor die |
US9679863B2 (en) | 2011-09-23 | 2017-06-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interconnect substrate for FO-WLCSP |
US8810024B2 (en) | 2012-03-23 | 2014-08-19 | Stats Chippac Ltd. | Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units |
US10049964B2 (en) | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
US9842798B2 (en) | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
US9837303B2 (en) | 2012-03-23 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units |
US9613917B2 (en) | 2012-03-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) device with integrated passive device in a via |
DE112013002672T5 (de) * | 2012-05-25 | 2015-03-19 | Nepes Co., Ltd | Halbleitergehäuse, Verfahren zum Herstellen desselben und Gehäuse auf Gehäuse |
KR101362715B1 (ko) * | 2012-05-25 | 2014-02-13 | 주식회사 네패스 | 반도체 패키지, 그 제조 방법 및 패키지 온 패키지 |
KR101362714B1 (ko) * | 2012-05-25 | 2014-02-13 | 주식회사 네패스 | 반도체 패키지, 그 제조 방법 및 패키지 온 패키지 |
KR101368793B1 (ko) * | 2012-05-25 | 2014-03-03 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
CN103632988B (zh) * | 2012-08-28 | 2016-10-19 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
US9165887B2 (en) | 2012-09-10 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with discrete blocks |
US9391041B2 (en) | 2012-10-19 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out wafer level package structure |
KR101494413B1 (ko) * | 2013-05-29 | 2015-02-17 | 주식회사 네패스 | 지지프레임 및 이를 이용한 반도체패키지 제조방법 |
US20150041993A1 (en) * | 2013-08-06 | 2015-02-12 | Infineon Technologies Ag | Method for manufacturing a chip arrangement, and a chip arrangement |
US9373527B2 (en) | 2013-10-30 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
US20150147845A1 (en) * | 2013-11-26 | 2015-05-28 | Texas Instruments Incorporated | Dual sided embedded die and fabrication of same background |
DE102014019635B4 (de) * | 2014-01-17 | 2024-01-11 | Taiwan Semiconductor Mfg. Co., Ltd. | Halbleiterpackage und Verfahren zu seiner Herstellung |
TWI566348B (zh) * | 2014-09-03 | 2017-01-11 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
WO2016048363A1 (en) * | 2014-09-26 | 2016-03-31 | Intel Corporation | Integrated circuit package having wire-bonded multi-die stack |
US9786623B2 (en) | 2015-03-17 | 2017-10-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming PoP semiconductor device with RDL over top package |
KR102065943B1 (ko) * | 2015-04-17 | 2020-01-14 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 및 그 제조 방법 |
KR101922874B1 (ko) * | 2015-12-21 | 2018-11-28 | 삼성전기 주식회사 | 전자 부품 패키지 |
KR102019351B1 (ko) * | 2016-03-14 | 2019-09-09 | 삼성전자주식회사 | 전자 부품 패키지 및 그 제조방법 |
KR101870153B1 (ko) * | 2016-11-28 | 2018-06-25 | 주식회사 네패스 | 절연 프레임을 이용한 반도체 패키지 및 이의 제조방법 |
US10283474B2 (en) | 2017-06-30 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure and method for forming the same |
TWI736780B (zh) | 2017-10-31 | 2021-08-21 | 台灣積體電路製造股份有限公司 | 晶片封裝及其形成方法 |
US11322449B2 (en) * | 2017-10-31 | 2022-05-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with fan-out structures |
EP3557608A1 (de) * | 2018-04-19 | 2019-10-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Verpackte integrierte schaltung mit zwischenschaltfunktionalität und verfahren zur herstellung solch einer verpackten integrierten schaltung |
US11121076B2 (en) | 2019-06-27 | 2021-09-14 | Texas Instruments Incorporated | Semiconductor die with conversion coating |
KR20210072984A (ko) * | 2019-12-10 | 2021-06-18 | 에스케이하이닉스 주식회사 | 인터포즈 브리지를 포함한 서브 패키지들이 수직하게 스택된 스택 패키지 |
KR20210082030A (ko) * | 2019-12-24 | 2021-07-02 | 에스케이하이닉스 주식회사 | 인터포즈 브리지를 포함한 서브 패키지들이 스택된 반도체 패키지 |
KR20210137275A (ko) * | 2020-05-07 | 2021-11-17 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020053730A1 (en) * | 2000-10-24 | 2002-05-09 | Naohiro Mashino | Semiconductor device and production process thereof |
US20030215993A1 (en) * | 2002-02-13 | 2003-11-20 | Nobuo Oshima | Electronic component and fabricating method |
US20040033673A1 (en) * | 2002-08-15 | 2004-02-19 | Cobbley Chad A. | Method of packaging semiconductor dice employing at least one redistribution layer |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5875859A (ja) * | 1981-10-30 | 1983-05-07 | Fujitsu Ltd | 半導体装置 |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
US6126482A (en) * | 1997-10-31 | 2000-10-03 | Thomas & Betts International, Inc. | Right angle coaxial cable connector |
US6038133A (en) | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
KR100347706B1 (ko) * | 2000-08-09 | 2002-08-09 | 주식회사 코스타트반도체 | 이식성 도전패턴을 포함하는 반도체 패키지 및 그 제조방법 |
WO2002015266A2 (en) | 2000-08-16 | 2002-02-21 | Intel Corporation | Direct build-up layer on an encapsulated die package |
DE10137184B4 (de) * | 2001-07-31 | 2007-09-06 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil |
DE10138278C1 (de) * | 2001-08-10 | 2003-04-03 | Infineon Technologies Ag | Elektronisches Bauteil mit aufeinander gestapelten elektronischen Bauelementen und Verfahren zur Herstellung derselben |
US20030153119A1 (en) * | 2002-02-14 | 2003-08-14 | Nathan Richard J. | Integrated circuit package and method for fabrication |
DE10224124A1 (de) * | 2002-05-29 | 2003-12-18 | Infineon Technologies Ag | Elektronisches Bauteil mit äußeren Flächenkontakten und Verfahren zu seiner Herstellung |
DE10320646A1 (de) * | 2003-05-07 | 2004-09-16 | Infineon Technologies Ag | Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben |
-
2004
- 2004-05-06 DE DE102004022884A patent/DE102004022884B4/de not_active Expired - Fee Related
-
2005
- 2005-05-03 WO PCT/DE2005/000840 patent/WO2005109499A2/de active Application Filing
-
2006
- 2006-11-06 US US11/593,150 patent/US7545047B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020053730A1 (en) * | 2000-10-24 | 2002-05-09 | Naohiro Mashino | Semiconductor device and production process thereof |
US20030215993A1 (en) * | 2002-02-13 | 2003-11-20 | Nobuo Oshima | Electronic component and fabricating method |
US20040033673A1 (en) * | 2002-08-15 | 2004-02-19 | Cobbley Chad A. | Method of packaging semiconductor dice employing at least one redistribution layer |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1703558A2 (de) * | 2005-03-15 | 2006-09-20 | Shinko Electric Industries Co., Ltd. | Leiterplatte mit eingebettetem Halbleiterchip, eingebetteter Verstärkung und Herstellungsmethode dafür |
EP1703558A3 (de) * | 2005-03-15 | 2010-01-20 | Shinko Electric Industries Co., Ltd. | Leiterplatte mit eingebettetem Halbleiterchip, eingebetteter Verstärkung und Herstellungsmethode dafür |
US7884484B2 (en) | 2005-03-15 | 2011-02-08 | Shinko Electric Industries Co., Ltd. | Wiring board and method of manufacturing the same |
EP2184777A1 (de) * | 2008-11-07 | 2010-05-12 | General Electric Company | Verbindungsstruktur |
Also Published As
Publication number | Publication date |
---|---|
DE102004022884B4 (de) | 2007-07-19 |
US20070126122A1 (en) | 2007-06-07 |
WO2005109499A3 (de) | 2006-01-19 |
US7545047B2 (en) | 2009-06-09 |
DE102004022884A1 (de) | 2005-12-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2005109499A2 (de) | Halbleiterbauteil mit einem umverdrahtungssubstrat und verfahren zur herstellung desselben | |
DE102005043557B4 (de) | Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite | |
DE10360708B4 (de) | Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben | |
DE102006001767B4 (de) | Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben | |
DE69838053T2 (de) | Elektronische Schaltung, insbesondere für implantierbare aktive medizinische Vorrichtung, wie ein Herzstimulator oder -defibrillator, und deren Herstellungsmethode | |
DE102006005645B4 (de) | Stapelbarer Baustein, Bausteinstapel und Verfahren zu deren Herstellung | |
DE102005030465B4 (de) | Halbleiterstapelblock mit Halbleiterchips und Verfahren zur Herstellung desselben | |
DE19747105A1 (de) | Bauelement mit gestapelten Halbleiterchips | |
DE19801312A1 (de) | Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes | |
DE10250538A1 (de) | Elektronisches Bauteil als Multichipmodul und Verfahren zu dessen Herstellung | |
WO2005091366A2 (de) | Halbleitermodul mit einem kopplungssubstrat und verfahren zur herstellung desselben | |
DE10352946A1 (de) | Halbleiterbauteil mit Halbleiterchip und Umverdrahtungslage sowie Verfahren zur Herstellung desselben | |
DE69509979T2 (de) | BGA Gehäuse für integrierte Schaltungen und Verfahren zu ihrer Herstellung | |
WO2006012846A1 (de) | Halbleiterbasisbauteil mit verdrahtungssubstrat und zwischenverdrahtungsplatte für einen halbleiterbauteilstapel sowie verfahren zu deren herstellung | |
DE102004009056B4 (de) | Verfahren zur Herstellung eines Halbleitermoduls aus mehreren stapelbaren Halbleiterbauteilen mit einem Umverdrahtungssubstrat | |
EP1620893B1 (de) | Verfahren zur herstellung eines nutzens und verfahren zur herstellung elektronischer bauteile mit gestapelten halbleiterchips aus dem nutzen | |
EP1060513B1 (de) | Halbleiterbauelement mit mehreren halbleiterchips | |
DE10334575B4 (de) | Elektronisches Bauteil und Nutzen sowie Verfahren zur Herstellung derselben | |
DE10142119A1 (de) | Elektronisches Bauteil und Verfahren zu seiner Herstellung | |
DE10124970B4 (de) | Elektronisches Bauteil mit einem Halbleiterchip auf einer Halbleiterchip-Anschlußplatte, Systemträger und Verfahren zu deren Herstellung | |
DE10136655C1 (de) | Multichipmodul in COB Bauweise, insbesondere CompactFlash Card mit hoher Speicherkapazität und Verfahren zur Herstellung desselben | |
DE102005051414B3 (de) | Halbleiterbauteil mit Verdrahtungssubstrat und Lotkugeln sowie Verfahren zur Herstellung des Halbleiterbauteils | |
DE10142117A1 (de) | Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung | |
DE19800928B4 (de) | Gehäuse, insbesondere stapelbares Gehäuse, zur Aufnahme von Bauelementen und Verfahren zu dessen Herstellung | |
DE19821916A1 (de) | Gehäusekonstruktion einer Halbleitereinrichtung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 11593150 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 11593150 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |