Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
  • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/051—Manufacture or treatment of isolation region based on field-effect
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/50—Isolation regions based on field-effect

Definitions

• the present invention relates to RF isolation in integrated circuits.
• wireless communication devices use high-frequency signals such as 900 MHz to 1900 MHz for cellular phones, and higher frequencies (up to 6 GHz or more) for other applications such as wireless LANs and fiber optic transceivers .
• RF signals at such frequencies are difficult to generate and control. These signals also have a tendency to interfere with one other because they are easily coupled by parasitic properties present in all electronic components, including integrated circuits.
• Si0 2 trench isolation and conductive guard rirrgs are isolation techniques that have been employed (such a.s with SOI processes) to isolate devices of an integrated circuit. Dielectric trench isolation structures provide lateral barriers between circuit devices . Conductive guard rings are used to enclose the area to be isolated.
• U.S. Patent No. 6,355,537 discloses a double ring approach where two isolation trenches (usually rectilinear) are formed around a device to be isolated. The silicon between the two isolation trenches is doped to form a conductive guard ring region, and a grounded contact is applied to the conductive guard ring region.
• the isolation trenches may be filled with a dielectric such as silicon oxide or oxide/polysilicon. This grounded guard ring region, the use of SOI on which the integrated circuit is formed, and the use of a high resistivity material for the substrate of the SOI greatl ⁇ y improves RF isolation.
• the process disclosed in the 537 patent is primarily for thick SOI where the epitaxial layer is on the order of one micron. Moreover, the process disclosed in the 537 patent relies on an n + buried layer that forms a low resistivity RF signal path. Also, the process disclosed in the ⁇ 537 patent is BiCMOS (bipolar CMOS) dependent.
• U.S. Patent No. 5,661,329 discloses the use of a separation groove around active regions of an integrated circuit. One disadvantage of this separation groove is that external RF power can still pass through the separation groove to the active region. Moreover, this separation groove appears to be intended primarily for yield improvement and not for RF isolation. Therefore, the ⁇ 329 patent does not appear to address the problem of RF isolation and appears to show no intent to terminate electric fields created by RF power.
• an integrated circuit comprises a semiconductor substrate, a buried insulation layer over the semiconductor substrate, a semiconductor mesa over the buried insulation layer, and a guard ring substantially surrounding the semiconductor mesa.
• the guard ring is in contact with the semiconductor substrate, and the guard ring is arranged to provide RF isolation for the semiconductor mesa.
• an integrated circuit comprises a semiconductor substrate, a buried insulation layer over the semiconductor substrate, a first semiconductor mesa over the buried insulation layer, a second semiconductor mesa over the buried insulation layer, a first guard ring substantially surrounding the first semiconductor mesa, and a second guard ring substantially surrounding the second semiconductor mesa.
• the first guard ring is in contact with the semiconductor substrate, and the first guard ring is arranged to provide RF isolation for the first semiconductor mesa.
• the second guard ring is in contact with the semiconductor substrate, and the second guard ring is arranged to provide RF isolation for the second semiconductor mesa.
• a method of isolating a semiconductor feature of an integrated circuit from RF signals comprises the following: forming a buried insulation layer over a semiconductor substrate; forming a semiconductor feature in one or more semiconductor layers so that the semiconductor feature is formed over a portion of the buried insulation • layer, wherein the buried insulating layer has a trench therethrough down to the semiconductor substrate that substantially encloses the portion of the buried insulation layer, wherein the one or more semiconductor layers has a trench therethrough that substantially encloses the semiconductor feature, and wherein the trench through the one or more semiconductor layers substantially aligns with the trench through the buried insulating layer; and, filling the trench through the one or more semiconductor layers and the trench through the buried insulating layer with conducting material having low resistivity so that a conductive guard ring substantially surrounds the semiconductor feature.
• an integrated circuit comprises a semiconductor substrate, a semiconductor feature, and a guard ring.
• the semiconductor substrate forms a first semiconductor layer.
• the semiconductor feature is formed in a second semiconductor layer, and the second semiconductor layer is over the first semiconductor layer.
• the guard ring substantially surrounds the semiconductor feature, the guard ring is in contact with the semiconductor substrate, and the guard ring is arranged to provide RF isolation for the semiconductor feature .
• Figure 1 is a top plan view illustrating a semiconductor integrated circuit in accordance with the present invention
• Figure 2 is a sectional view illustrating the semiconductor integrated circuit of Figure 1 taken along line 2-2
• Figure 3 is a sectional view illustrating the semiconductor integrated circuit of Figure 1 taken along 1 ine 3—3
• Figures 4-6 are sectional views illustrating a method of manufacturing the semiconductor integrated circuit as shown in Figure 2
• Figure 7 is a top view of an exemplary layout of an integrated circuit incorporating the present invention.
• a semiconductor integrated circuit 10 in accordance with one embodiment of the present invention includes a single SOI substrate 12.
• Tlie SOI substrate 12 typically includes a silicon handle wafer, a buried oxide layer over the silicon handle wafer, and one or more silicon layers that are over t ie buried oxide layer and that are processed to form electronic devices of the integrated circuit.
• the present invention can be applied to non-SOI substrates, such as bulk silicon, and to other SOI substrates, such as SOS (silicon-on-sapphire) substrates.
• the SOI substrate 12 includes a first isolation guard xing 14 that isolates a first device mesa 16 and a second isolation guard ring 18 that isolates a second device mesa 20.
• first dielectric ring 22 may be provided between the first isolation guard ring 14 and the first device mesa 16
• second dielectric ring 24 may be provided between the second isolation guard ring 18 and the second device mesa 20.
• the dielectric in the first and second dielectric rings 22 and 24 may be silicon oxide or some other material, such as, for example, oxide/silicon nitride .
• the first and second device mesas 16 and 20 may each comprise many different types of devices such as, for example, one or more transistors, and/or one or more diodes, and/or one or more capacitors, and/or one or more resistors, etc.
• any type of semiconductor element or elements may be formed in each of the first and second device mesas 16 and 20.
• each of the first and second device mesas 16 and 20 may comprise one, two, or more such elements forming a single element or a sub- circuit.
• the semiconductor element or elements may be active, passive, or a combination of both.
• any number of devices, device mesas, and isolation guard rings may be included on the SOI substrate 12.
• the SOI substrate 12 includes a silicon handle wafer 40 and a buried insulating layer 42 that separates the first device mesa 16 from the silicon handle wafer 40.
• the silicon handle wafer 40 may be formed of p- single crystal silicon, and the buried insulating layer 42 may be formed of a silicon oxide film.
• the silicon handle wafer 40 is preferably a high resistivity (or high Z) substrate having a high ohm per centimeter rating such
• the first isolation guard ring 14 surrounds the first device mesa 16. During formation of the first isolation guard ring 14, all of the layers (including any shallow trench isolation oxide) above the buried insulation layer 42 and the buried insulation layer 42 selectively removed so as to form a trench that will be processed as described below in order to fabricate the first isolation guard ring 14.
• the portion of the silicon handle wafer 40 that is exposed by the trench may be doped, such as by ion implantation. This doping improves to the ohmic contact between the first isolation guard ring 14 and the silicon handle wafer 40.
• the trench is filled with a low resistivity material to form the first isolation guard ring 14.
• the low resistivity material may be a conductive metal such as tungsten, aluminum, or copper.
• conductive materials other than metals can be used for the low resistivity material.
• An exemplary resistivity of such a low resistivity material is 5x10 ⁇ 3 Ohm-cm.
• the first dielectric ring 22 may be formed down to the buried insulation layer 42.
• the first isolation guard ring 14 surrounds the first device mesa 16, and the first isolation guard ring 14 also isolates the first device mesa 16 from a surrounding field n " layer 44.
• One or more metal contacts 48 are applied to first isolation guard ring 14 to provide a low resistance RF ground along one or more corresponding conductors 50.
• the one or more conductors 50 may be coupled to local ground through on-chip metal or, for better isolation, to an off-chip ground. Accordingly, the first isolation guard ring 14 forms a low resistivity RF path to a metal layer which is connected to ground potential level . As shown in Figures 1 and 3 , the second isolation guard ring 18 surrounds the second device mesa 20. The second isolation guard ring 18 also contacts the silicon handle wafer 40, and the silicon handle wafer 40 may be doped where it contacts the second isolation guard ring 18 so as to improve the ohmic contact between the second isolation guard ring 18 and the silicon handle wafer 40.
• One or more metal contacts 62 are applied to the second isolation guard ring 18 to provide a low resistance RF ground along one or more corresponding conductors 6 .
• the first and second isolation guard rings 14 and 18 provide excellent RF isolation because electric fields created by RF power are terminated to ground through the first and second isolation guard rings 14 and 18 and the conductors 50 and 64. Having these RF grounded terminations around the first and second device mesas 16 and 20 greatly improves RF isolation.
• the use of the buried insulating layer 42 of the SOI substrate 12 provides additional RF isolation, and the use of the high resistivity (or high Z) silicon handle wafer 40 of the SOI substrate 12 improves RF isolation by making the silicon handle wafer 40 a high resistance path for RF power.
• any leaking RF power will prefer the path of least resistance which will not be the silicon handle wafer 40 if a high Z substrate is used therefor.
• the present invention means that thin SOI can be used for advanced mixed (analog and digital) signal/RF CMOS technology.
• the n- type layer 44 may be on the order of 0.16 micron instead of the 1 micron layer that is used in BiCMOS.
• the buried insulation layer 42 is completely removed in the trenches within which the first and second isolation guard . rings 14 and 18 are formed to allow direct contact of the first and second isolation guard rings 14 and 18 to the silicon handle wafer 40 thus resulting in better RF isolation.
• the material used to contact the silicon handle wafer 40 has a significantly lower resistivity than in prior devices resulting in better RF isolation.
• the present invention is not limited to the use of metals in the formation of the first and second isolation guard rings 14 and 18. Instead, in-situ doped low resistivity material/SEG (Selective Epitaxial Growth) can also be used to fill the trenches during formation of the first and second isolation guard rings 14 and 18.
• SEG Selective Epitaxial Growth
• the buried insulating layer 42 may be formed, for example, by high energy high dose ion implantation of oxygen into the silicon handle wafer 40.
• the buried insulating layer 42 may be formed, for example, by using a bonded wafer process.
• the n " layer 44 is grown by epitaxial growth over the surface of the buried insulating layer 42.
• the trenches for the first isolation guard ring 14 and the first dielectric ring 22 are formed by anisotropic etching, such as, for example, by RIE. Specifically, the trench for the first isolation guard ring 14 extends from the main surface of the n " layer 44 to the silicon handle wafer 40.
• the trench for the first dielectric ring 22 extends from the main surface of the n " layer 44 to the buried insulating layer 42.
• a photoresist 70 may be used as a mask for the etching. Alternatively, a hard mask may be used as a mask for the etching in place of the photoresist 70.
• the trench for the first isolation guard ring 14 is filled with a conductive material such as, for example, metal, and the trench for the first dielectric ring 22 is filled with an insulator such as, for example, a silicon oxide.
• This insulator may be formed, for example, by depositing a silicon oxide film over the main surface of the n " layer 44 by the CVD method and by etching back the silicon oxide ilm.
• the silicon oxide film may be over-etched off exicept from the inside of the trench that is used to form tle first dielectric ring 22.
• the trench that is used to form the first dielectric ring 22 could alternatively be filled with other materials, such as, for example, oxide/silicon nitride.
• Figure 7 is a top view of an exemplary layout of an integrated circuit 80.
• the integrated circuit 80 has two sub-circuits 82 and 84, although the integrated circuit 80 may have additional sub-circuits (not shown) .
• the su-b-circuit 82 may be a low noise amplifier and the sub-circuit 84, for exiample, may be a voltage controlled oscillator.
• the sub-circuit 82 includes one or more device mesas such as the device mesas 86, 88, and 90.
• the device mesa 86 is surrounded by an isolation guard ring 92
• the device mesa 88 is surrounded by an isolation guard ring 94
• the device mesa 90 is surrounded by an isolation guard ring 96.
• the isolation guard rings 92, 94, and 96 may be arranged as shown in Figures 1-6 such that ttiey contact corresponding doped areas of a semiconductor substrate 98 over which the integrated circuit 80 is formed.
• a chip metal 100 of the integrated circuit 80 couples the isolation guard rings 92, 94, and 96 together and to a ground lead 102.
• the sub-circuit 84 includes one or more device mesas such as the device mesas 104, 106, and 108.
• the device mesa 104 is surrounded by an isolation guard ring 110
• the device mesa 106 is surrounded by an isolation guard ring 112
• the device mesa 108 is surrounded by an isolation guard ring 114.
• the isolation guard rings 110, 112, and 114 also may be arranged as shown in Figures 1-6 such that they contact corresponding doped areas of the semiconductor substrate 98 over which the integrated circuit 80 is formed.
• a chip metal 116 of the integrated circuit 80 couples the isolation guard rings 110, 112, and 114 together and to a ground lead 118.
• the isolation guard rings 92, 94, and 96 may be considered to be a first isolation guard ring, and the isolation guard rings 110, 112, and 114 may be considered to be a second isolation guard ring.
• the integrated circuit 80 includes a third isolation guard- ring 120 that surrounds the sub-circu.it 82 and that isolates the sub-circuit 82 from the sub-circuit 84.
• the third isolation guard ring 120 may be arranged as shown in Figures 1-6 such that its contacts a corresponding doped area of the semiconductor substrate 98 over which the integrated circuit 80 is formed.
• a chip metal 122 of the integrated circuit 80 couples the third isolation guard ring 120 to a bond pad 124 that may be coupled to an o f-chip ground.

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• Semiconductor Integrated Circuits (AREA)
• Element Separation (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Bipolar Transistors (AREA)

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• 2004
  • 2004-03-26 US US10/811,207 patent/US7851860B2/en not_active Expired - Fee Related
• 2005
  • 2005-03-23 DE DE602005026918T patent/DE602005026918D1/de not_active Expired - Lifetime
  • 2005-03-23 WO PCT/US2005/009643 patent/WO2005098937A1/en not_active Ceased
  • 2005-03-23 JP JP2007505127A patent/JP5209301B2/ja not_active Expired - Fee Related
  • 2005-03-23 EP EP05726078A patent/EP1728275B1/en not_active Expired - Lifetime
  • 2005-03-25 TW TW094109387A patent/TWI364091B/zh not_active IP Right Cessation
• 2010
  • 2010-11-04 US US12/939,770 patent/US8058689B2/en not_active Expired - Fee Related

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