Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L23/142—Metallic substrates having insulating layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/02—Containers; Seals
  • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
  • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/153—Connection portion
  • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
  • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/153—Connection portion
  • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/161—Cap
  • H01L2924/1615—Shape
  • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Definitions

• the present invention generally relates to a substrate for a semiconductor device and a semiconductor device, and more specifically, to a heat sink, a heat dissipation substrate, and a housing constituting a semiconductor device on which a semiconductor element such as an MPU (Micro Processing Unit) is mounted.
• the present invention relates to a substrate used for, for example, the present invention.
• FIG. 7 is a cross-sectional view showing a schematic configuration of a semiconductor device equipped with a conventional MPU.
• a nickel plating layer 2 is formed on the outer peripheral surface of a base material 1 having a copper-tungsten alloy having high thermal conductivity.
• a semiconductor chip 5 as a semiconductor element is adhered and fixed via a conductive resin layer 4 containing metal having high thermal conductivity.
• a ceramic package 6 is arranged so as to cover the semiconductor chip 5, and is adhered and fixed on the surface of the plating layer 2 via a conductive resin layer 4.
• Patent Document 1 discloses that a metal plate is made of Al 2 O 3 as a substrate for a semiconductor device having a thermal expansion coefficient close to that of a mounted semiconductor element and having excellent heat dissipation.
• Patent Document 2 discloses that, as a substrate for mounting a semiconductor element, which has a low thermal resistance and a small effect on a high-frequency signal, a metal substrate is made of diamond or pseudo diamond-like carbon. It has been proposed to form a film or an electric insulating layer made of a mixture thereof.
• Patent Document 3 discloses a copper-tungsten alloy or a copper-molybdenum alloy in order to solve the problem of pinholes and cracks generated in an electrically insulating coating layer.
• a substrate for mounting a semiconductor element comprising a plate has been proposed.
• Patent Document 4 discloses copper-tungsten or copper-molybdenum.
• a substrate material that also has an alloying force such as tungsten and / or a substrate that also has a tungsten and / or molybdenum-copper alloy force and a surface of the substrate to which the resin is to be bonded
• a semiconductor device substrate having an aluminum coating layer formed as described above and an oxidation layer having a thickness of 10 to 800 angstroms by natural oxidation of the surface of the aluminum coating layer.
• Patent Document 1 JP-A-58-15241
• Patent Document 2 JP-A-60-128625
• Patent Document 3 JP-A-61-194842
• Patent document 4 JP-A-10-284643
• an object of the present invention is to provide a configuration of a semiconductor device substrate that can further stabilize a driving voltage of a semiconductor element to be mounted.
• a substrate for a semiconductor device includes a base material and an electric insulating film formed on at least a part of the surface of the base material.
• the base material is an alloy containing copper and tungsten, an alloy containing copper and molybdenum, an alloy containing copper, tungsten, and molybdenum, and aluminum.
• the electrical insulating film includes a plurality of layers made of at least one film selected from the group consisting of a diamond-like carbon film, an oxidized aluminum film, and an oxidized silicon film.
• the diamond 'like' carbon (DLC), natural thereto and SP 2 bond the same carbon as the SP 3 bond with graphite of the same carbon diamond carbon including the binding of hydrogen allotrope or amorphous Quality hydrocarbons.
• the thickness of the electric insulating film is preferably equal to or greater than the surface roughness of the base material.
• the surface roughness of the substrate is preferably not less than 0.1 m and not more than 20 ⁇ m in Rmax.
• the depth of the defective portion is not more than 2Z3 of the thickness of the electric insulating film.
• the electric insulating film is preferably formed on the surface of the base material on which the semiconductor element is mounted.
• the alloy containing copper and tungsten, the alloy containing copper and molybdenum, and the alloy containing copper, tungsten, and molybdenum contain 5% by mass or more of copper. It is preferred that the content is not more than mass%.
• the composite material containing aluminum and silicon carbide preferably contains aluminum in an amount of 20% by mass to 90% by mass.
• the composite material containing silicon and silicon carbide preferably contains silicon in an amount of 10% by mass to 35% by mass.
• a semiconductor device includes a base, an electric insulating film formed on at least a part of the surface of the base, and a semiconductor element adhered on the electric insulating film.
• the base material is made of an alloy containing copper and tungsten, an alloy containing copper and molybdenum, an alloy containing copper, tantalum, and molybdenum, a composite material containing aluminum and silicon carbide, and a composite material containing silicon and silicon carbide.
• Material strength One kind of material strength selected from the group.
• the electrical insulating film includes a plurality of layers of at least one film selected from the group consisting of a diamond 'like' carbon film, an oxidized aluminum film, and an oxidized silicon film.
• the electric insulating film is a diamond-like carbon film, an oxide film. It may be a multi-layer composed of two or more films selected from the group consisting of a aluminum film and an silicon oxide film.
• the electrical insulating film formed on at least a part of the surface of the base material includes the diamond 'like' carbon film, the silicon oxide aluminum film and the silicon oxide silicon film. Since it is configured to include a plurality of layers made of at least one kind of film selected from the group consisting of the capacitor film, even if the semiconductor element is fixed on the electric insulating film, the gap between the semiconductor element and the base material is not increased. Thus, higher electrical insulation can be maintained, and the driving voltage of the semiconductor element to be mounted can be further stabilized.
• FIG. 1 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device as one embodiment of a substrate for a semiconductor device of the present invention.
• FIG. 2 As reference examples of the present invention, cross-sectional views (A) and (B) showing schematic cross-sectional structures when a single layer of diamond-like carbon film is formed as an electric insulating film on the surface of a substrate. ).
• FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure when two diamond-like carbon films are formed as an electric insulating film on the surface of a base material as one embodiment of the present invention (A) And (B).
• FIG. 4 As another reference example of the present invention, a cross-sectional view showing a schematic cross-sectional structure when a single layer of diamond 'like' carbon film is formed as an electric insulating film on the surface of a base material (A ) And (B).
• FIG. 5 As another embodiment of the present invention, a cross-sectional view showing a schematic cross-sectional structure in the case where three layers of diamond-like carbon films are formed as an electrical insulating film on the surface of a base material ( A) and (B).
• FIG. 6 is a schematic view schematically showing a method for evaluating the electrical insulation of a semiconductor device substrate in an example of the present invention.
• FIG. 7 is a cross-sectional view showing a schematic cross-sectional structure of a conventional semiconductor device.
• FIG. 1 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device as one embodiment of a semiconductor device substrate of the present invention.
• the base material 1 is a base material such as a heat sink, a heat radiating substrate, and a housing that constitute the semiconductor device, and has a concave portion in the center of one surface.
• the material constituting the base material 1 is a copper-tungsten alloy, a copper-molybdenum alloy, a copper-tungsten-molybdenum alloy, a composite material in which silicon carbide is dispersed in an aluminum or aluminum alloy, or a silicon or silicon Any of composite materials in which silicon carbide is dispersed in an alloy. These materials have both a coefficient of thermal expansion close to that of materials for semiconductor devices and packages, and a high thermal conductivity.
• Coefficient of thermal expansion preferably in order to achieve consistency with the thermal expansion coefficient of the semiconductor element to be mounted is 13 X 10- 6 Z ° C or less, more preferably 3 X 10- 6 - 8 X 10- 6 Z ° C.
• the thermal conductivity is preferably at least 150 WZm'K, more preferably at least 200 WZm'K.
• a nickel plating layer 2 is formed so as to cover the outer peripheral surface of the substrate 1.
• the electric insulating film 3 is formed on a part of the surface of the base material 1 on which the plating layer 2 is formed, including the surface of the concave portion.
• the electrical insulating film 3 is composed of a plurality of layers of a diamond-like carbon film, an oxidized aluminum film, or an oxidized silicon film.
• an adhesion layer of titanium, chromium, nickel-chromium alloy, tantalum, silicon, a compound thereof, or the like may be formed as a base layer.
• the thickness of the adhesion layer is preferably 0.01-1.
• the electric insulating film 3 formed on the surface of the concave portion of the base 1 is adhered and fixed via a conductive resin layer 4.
• a ceramic package 6 is arranged so as to cover the semiconductor chip 5, and is adhered and fixed via a conductive resin layer 4 on an electric insulating film 3 formed on the surface of the base 1.
• a plastic package may be used instead of the ceramic package 6.
• the semiconductor device is configured in this manner.
• the electric insulating film 3 formed on the surface of the concave portion of the base material 1 on which the semiconductor chip 5 is mounted is formed of a diamond-like carbon film, It is composed of a plurality of shifted layers of the aluminum film or the silicon oxide film.
• FIG. 2 is a cross-sectional view showing a schematic cross-sectional structure when a single layer of a diamond-like carbon film is formed as an electric insulating film on the surface of a base material as a reference example of the present invention (A ) And (B).
• an adhesion layer 7 made of titanium or the like is formed as a base layer on the surface of the substrate 1.
• an electrical insulating film 3 made of one layer of diamond-like carbon film is formed on the adhesion layer 7.
• a concave portion P that exposes the surface of the adhesive layer 7 is formed on a part of the surface of the electric insulating film 3 as a minute film defect caused by the surface condition of the substrate 1 or the like.
• FIG. 2 (B) when the conductive resin layer 4 is formed on the electric insulating film 3 to fix the semiconductor element, the conductive resin layer 4 and the adhesion layer 7 are electrically connected. As a result, a dielectric breakdown portion Q that can be electrically connected to the substrate 1 is formed.
• FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure when two diamond-like carbon films are formed as an electric insulating film on the surface of a base material as one embodiment of the present invention.
• an adhesion layer 7 made of titanium or the like is formed as a base layer on the surface of the substrate 1.
• two insulating layers 31 and 32 made of a diamond-like carbon film are formed on the adhesion layer 7.
• the fineness caused by the surface condition of the substrate 1 etc. As a small film defect, even if a concave portion exposing the surface of the adhesion layer 7 is formed in a part of the surface of the insulating layer 31, the insulating layer 32 formed thereon fills the concave portion and complements it.
• FIG. 4 is a cross-sectional view showing a schematic cross-sectional structure in the case where one diamond 'like' carbon film is formed as an electric insulating film on the surface of a base material as another reference example of the present invention. (A) and (B).
• an adhesion layer 7 made of titanium or the like is formed as a base layer on the surface of the substrate 1.
• an electrical insulating film 3 made of one layer of diamond-like carbon film is formed on the adhesion layer 7.
• two concave portions P exposing the surface of the adhesive layer 7 are formed on a part of the surface of the electric insulating film 3 as minute film defects caused by the surface condition of the substrate 1 and the like.
• FIG. 4 (B) when the conductive resin layer 4 is formed on the electric insulating film 3 to fix the semiconductor element, the conductive resin layer 4 and the adhesion layer 7 are electrically contacted. As a result, a dielectric breakdown portion Q that can conduct with the substrate 1 is formed.
• FIG. 5 shows a schematic cross-sectional structure of another embodiment of the present invention in which three diamond 'like' carbon films are formed as electric insulating films on the surface of a base material. Sectional views (A) and (B).
• an adhesion layer 7 made of titanium or the like is formed as a base layer on the surface of the substrate 1.
• this adhesion layer 7 three layers of insulating layers 31, 32 and 33 made of diamond-like carbon film are formed.
• the formed insulating layers 32 and 33 complement and fill the recesses complementarily. For this reason, as shown in FIG.
• the material forming the base 1 is a copper-tungsten alloy containing 5 to 40% by mass of copper, - molybdenum alloy or copper - tungsten - molybdenum alloy, aluminum contained in the range of a 20-90 mass 0/0, composite silicon carbide to aluminum or aluminum alloy are dispersed, or a silicon 10- 35 wt%
• a composite material containing silicon carbide or silicon carbide dispersed in silicon or a silicon alloy it is possible to more preferably match the coefficient of thermal expansion with the semiconductor chip 5 to be mounted. In addition, the heat dissipation of the semiconductor chip 5 can be improved.
• the coefficient of thermal expansion of the copper-tungsten alloy is 5 X
• 10 6 - is a 12 X 10 6 / ° about C.
• silicon, germanium, gallium constituting the general-purpose semiconductor chips - thermal expansion coefficient such as arsenic 3 X 10- 6 - Ru 4 X 10- 6 / ° C of about der.
• the thermal expansion coefficient of the material constituting the general-purpose ceramic package 4 X 10- 6 - is a 10 X 1 0- 6 Z ° about C. From the relationship between these coefficients of thermal expansion, the content of copper is preferably in the range of 5 to 40% by mass.
• the thermal expansion coefficient of the copper-tungsten alloy becomes small. A problem arises in that the substrate warps due to the difference in the rate and the semiconductor chip is distorted. If the copper content exceeds 40% by mass, the coefficient of thermal expansion of the copper-tungsten alloy increases, so that when joined to a ceramic package of silicon oxide or a semiconductor chip of silicon, the difference in the coefficient of thermal expansion is reduced. This causes a problem that the substrate is warped and the semiconductor chip is distorted. More preferably, the copper content is in the range of 7-20% by mass.
• the content of aluminum is less than 20% by mass, the amount of aluminum becomes relatively small, so that it becomes difficult to densify the composite material. If the aluminum content exceeds 90% by mass, the coefficient of thermal expansion of the composite material increases, and when bonded to a plastic package, there is a problem that the substrate warps due to the difference in the coefficient of thermal expansion. More preferably, the aluminum content is in the range of 40-70% by mass.
• the thermal expansion of the composite silicon carbide are dispersed in silicon or silicon alloy is at 5 X 10 6 or less, a thermal conductivity of 20 OWZm'K or higher.
• silicon constituting the general-purpose semiconductor chip, gate Rumaniumu, gallium - thermal expansion coefficient such as arsenic 3 X 10- 6 - is a 4 X 10- 6 Z ° about C.
• the thermal expansion coefficient of the material constituting the general-purpose ceramic package 4 X 10- 6 - is a 10 X 10- 6 Z ° about C. From the relationship between these coefficients of thermal expansion, the silicon content is preferably in the range of 10 to 35% by mass. If the content is not within this range, it is difficult to produce a composite material in which silicon or silicon carbide is dispersed in silicon alloy.
• the silicon content is less than 10% by mass, it is difficult to impregnate the silicon by the infiltration method, and nests are formed in the composite material, and the thermal conductivity of the composite material becomes low immediately. If the silicon content exceeds 35% by mass, the mechanical strength of the silicon carbide molded body before silicon infiltration is low, and it becomes difficult to produce a composite material that is difficult to handle. Also, since the content of silicon carbide is reduced, the thermal conductivity of the composite material is reduced. More preferably, the silicon content is in the range of 15 to 25% by mass.
• the thickness of the electric insulating film 3 is preferably equal to or more than the surface roughness (Rmax) of the substrate 1.
• the thickness of the electric insulating film 3 is smaller than the surface roughness of the base material 1, the electric insulating film 3 becomes partially thin, so that high electric insulation cannot be maintained. More preferably, the thickness of the electric insulating film 3 is at least twice the surface roughness of the substrate 1.
• the surface roughness of the substrate 1 is preferably in the range of 0.1 to 20 ⁇ m in Rmax.
• the surface roughness of the substrate 1 exceeds 20 m in Rmax, the thickness of the electric insulating film 3 formed on the surface of the substrate 1 becomes uneven, and a thin portion is formed, or the electric insulating film 3 Since pinholes occur in 3, high electrical insulation cannot be maintained. Further, in this case, when the conductive resin layer 4 is formed, a gap is easily generated between the conductive resin layer 4 and the surface of the plating layer 2, and the conductive resin layer 4 Variations in bonding strength increase. If the surface roughness of the substrate 1 is less than Rmax 0: Lm, it is difficult to obtain a sufficient anchor effect when forming the conductive resin layer 4. The adhesion between the substrate and the substrate 1 is reduced.
• the surface roughness of the substrate 1 is more preferably 0.1 to 8 ⁇ m in Rmax.
• the electric insulating film 3 has no defect.
• the depth of the defective portion is preferably equal to or less than 2Z3 of the thickness of the electric insulating film 3. If the depth of the defect exceeds 2Z3, which is the thickness of the electric insulating film 3, the thickness of the electric insulating film 3 is partially thinned, and a portion where high electric insulation cannot be maintained may be generated.
• the electric insulating film 3 is formed of a plurality of layers, but is preferably formed of 2-4 layers. If the number of layers exceeds 5, the number of steps for film formation increases, the cost required for film formation increases, and productivity decreases.
• the electrical insulating film 3 is more preferably formed from three or four layers.
• the diamond 'like' carbon film constituting the electrical insulating film 3 is preferably formed by a CVD method, a sputtering method, or the like.
• the aluminum oxide film is preferably formed by a method of performing anodizing treatment after evaporating aluminum.
• the silicon oxide film is preferably formed by a CVD method or the like.
• the electric insulating film 3 is a multiple layer composed of two or more films selected from the group consisting of a diamond 'like' carbon film, an oxidized aluminum film and an oxidized silicon film. Good embodiment
• FIG. 6 shows the conditions (substrate surface roughness Rmax, electric insulating film material, film thickness per layer, number of layers, total film thickness, and defect depth) shown in Tables 1 and 2.
• a substrate for a semiconductor device of Experimental Example No. 1-36 was fabricated by forming an electric insulating film 3 on the surface of the base material 1.
• As a base material a square plate having a thickness of 1.5 mm and a side of 41 mm was used.
• Tungsten-copper alloy containing 90 mass% of tungsten and 10 mass% of copper in Experimental Examples 16 and 11-118, and 95 mass% of tungsten and 5 mass% of copper in Experimental Example 7
• Example 8 tungsten-copper alloy containing 85% by mass of tungsten and 15% by mass of copper in Experimental Example 8, and tungsten containing 80% by mass of tungsten and 20% by mass of copper in Experimental Example 9 - copper alloy, 60 wt% tungsten
• a tungsten-copper alloy base material containing 90% by mass of tungsten and 10% by mass of copper was prepared by manufacturing by an infiltration method as follows.
• tungsten powder having an average particle diameter of 5 ⁇ m 0.2 mass% of nickel powder was added and mixed.
• This mixed powder was put into a stirring mixer, an acrylic binder was added in an amount of 1% by mass based on the total mass, and the mixture was further mixed for 1 hour using alcohol as a mixing medium, and the average particle size was about 100 / zm.
• Secondary particles were prepared.
• This powder was molded by a powder press to produce a square plate-like compact having a thickness of 2 mm and a side of 46 mm. The obtained molded body was heated in a hydrogen stream at a temperature of 400 ° C. for 1 hour, and subsequently heated at a temperature of 900 ° C. for 1 hour to remove a binder component.
• the compact was sintered at a temperature of 1300 ° C. in a hydrogen stream.
• a copper plate sufficient to fill the amount of pores in the obtained sintered body is prepared, and the sintered body is placed on the copper plate and heated to 1200 ° C in a stream of hydrogen to obtain tungsten.
• tungsten-copper alloy containing 90% by mass and 10% by mass of copper was obtained.
• Excessive copper adhering to the upper and lower surfaces and the outer peripheral surface of the alloy is removed by grinding, milling, and NC processing, and the surface roughness is adjusted to 3 m, 5 m, 10 m, and 20 m at Rmax.
• a nickel layer with a thickness of 2 m was formed on the surface of the substrate by electrolysis and electroless nickel plating, and used as a substrate sample.
• a composite material in which silicon carbide is dispersed in aluminum is manufactured by a sintering method as follows. We prepared and prepared.
• Aluminum powder having an average particle diameter of 25 ⁇ m and silicon carbide powder having an average particle diameter of 50 ⁇ m are blended so that silicon carbide becomes 70% by mass, and the mixture is placed in a stirring mixer and mixed for 1 hour.
• an aluminum silicon carbide raw material powder was obtained.
• the obtained raw material powder is molded by a powder press using a sample-shaped mold, and a flat plate-shaped compact having a thickness of 1.5 mm and a side of 41 mm, having a recess in the center of one surface.
• This compact was sintered in a nitrogen stream at a temperature of 700 ° C for 2 hours to obtain a composite material in which 70% by mass of silicon carbide was dispersed in 30% by mass of aluminum, and the surface roughness was blasted.
• the surface of the composite material was processed so that the surface was 3 m in Rma X, and a flat plate-like base material having a thickness of 1.5 mm and a side of 41 mm with a concave portion in the center of one surface was prepared.
• a composite material in which silicon carbide was dispersed in silicon was prepared by an infiltration method as follows.
• a powder obtained by mixing silicon carbide powder having an average particle diameter of 70 m and 5 m in a mass ratio of 3: 1 was added with a paraffin binder at 3% based on the total mass, and added in ethanol.
• the mixture was mixed using a ball mill.
• the obtained slurry is spray-dried into granules, molded using a sample-shaped mold by a powder press, and a square with a concave portion in the center of one surface and having a thickness of 2.Omm and a side of 41 mm Was produced.
• the obtained molded body was heated to a temperature of 400 ° C.
• a pre-sintered body was prepared by pre-sintering for 1 hour, and then a silicon powder having an average particle diameter of 3 m was formed into a square plate with a thickness of lmm and a side of 42 mm by a powder press. Titanium nitride powder was placed in ethanol on all surfaces other than the surface of the pre-sintered body (surface opposite to the surface with concave portions) to be brought into contact with the infiltration agent in a later step.
• the dispersed material was applied and dried to form a layer of an anti-elution agent, which also had the power of titanium nitride powder, and then contacted with an infiltrant on the surface of the pre-sintered body on which the anti-elution agent layer was not formed. And infiltrated in an argon gas atmosphere at a temperature of 1600 ° C. After infiltration, the melt was coated with an anti-elution agent. Not eluted in the plane eluted, by only eluted on the surface in contact with the infiltrant, 80 wt% of silicon carbide in 20 wt% silicon down to obtain a composite material dispersed. By blasting Remove the inhibitor and remove the leached material by grinding.Also, process the surface of the composite material so that the surface roughness is 3 ⁇ m Rmax. A square flat substrate of 1.5 mm and a side of 41 mm was prepared.
• the aluminum oxide (Al 2 O 3) film constituting the electric insulating film is made of aluminum under the following conditions.
• the temperature of the substrate was set to 250 ° C., and argon bombardment was performed on the surface of the substrate in a vacuum of 13.3 Pa (0.1 LTorr) for 20 minutes.
• An aluminum vapor-deposited film was formed on the surface of the substrate in a vacuum of 65 ⁇ 10 Pa (5 ⁇ 10 ′′ 5 Torr). after generating an acid aluminum film under the conditions of density LOOAZm 2, it was immersed in boiling water was subjected to sealing treatment. in addition, repeat the above steps to form a laminated film of Sani ⁇ aluminum film.
• the diamond 'like' carbon (DLC) film constituting the electric insulating film was formed on the surface of the base material by the plasma CVD method under the following conditions.
• a DLC film was formed, a titanium film was formed in a thickness of 0.1 ⁇ m on the surface of the substrate in advance as a lower layer by a sputtering method.
• the base material was attached to a plasma CVD apparatus, and further, attached matter on the surface of the base material was removed by nitrogen blowing.
• Pressure chamber in one of the plasma CVD apparatus is evacuated to a 2 X 10- 3 Pa, while heating the substrate to a temperature 200 ° C, it was carried out for 20 minutes with argon bombardment on the surface of the substrate, A titanium film was formed on the surface of the substrate to a thickness of 0 .: L m by sputtering.
• form the shape of the DLC film is supplied into the chamber one acetylene gas flow 3 X 10- 4 m 3 Zmin ( 300ccZmin).
• a degassing treatment was performed. Further, the steps up to the degassing treatment from the nitrogen broker were repeated to form a DLC film laminated film.
• the silicon oxide (SiO 2) film constituting the electrical insulating film is subjected to the plasma CVD method under the following conditions.
• the substrate was attached to a plasma CVD apparatus, and attached matter on the surface of the substrate was removed by nitrogen blowing. Vacuum exhaust until the pressure inside the chamber of the plasma CVD device reaches 1 ⁇ 10 _1 Pa, and heat the substrate to 350 ° C 3 ⁇ 10 ” 5 mVmi TEOS (Tetra-ethoxy Silane: Si (OC H)) gas
• n (30ccZmin), to form a Sani ⁇ silicon film is fed into the chamber one oxygen gas flow 9 X 10- 4 m 3 min ( 900ccZmin). After cooling the substrate on which the silicon oxide film was formed, a degassing treatment was performed. Further, the steps from the nitrogen blowing to the degassing treatment were repeated to form a laminated film of a silicon oxide film.
• FIG. 6 is a schematic view schematically showing a method for evaluating the electrical insulation of a semiconductor device substrate.
• a conductive metal plate 8 was bonded and fixed on an electric insulating film 3 formed on the surface of the substrate 1 via a conductive resin layer 4.
• the composition of the conductive resin layer 4 used is a thermosetting resin containing a silver filler.
• the material of the conductive metal plate 8 used is copper.
• a voltage was applied between the base material 1 and the conductive metal plate 8, and the dielectric breakdown voltage was measured with an insulation resistance measuring instrument. As a result, those having a dielectric breakdown voltage value of 2 V or more were regarded as good products.
• “Evaluation of electrical insulation” in Tables 1 and 2 shows the ratio of non-defective products to the number of measurement samples.
• the semiconductor device substrate of the present invention is used for a heat sink, a heat dissipation substrate, a housing, and the like that constitute a semiconductor device on which a semiconductor element such as an MPU (Micro Processing Unit) is mounted.
• MPU Micro Processing Unit

Landscapes

• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=34993971

Family Applications (1)

Country Status (4)

Cited By (1)

Families Citing this family (13)

Citations (6)

Family Cites Families (5)

• 2004
  • 2004-03-24 JP JP2004085969A patent/JP4382547B2/ja not_active Expired - Fee Related
• 2005
  • 2005-03-07 EP EP05720118A patent/EP1732128A4/en not_active Withdrawn
  • 2005-03-07 US US10/593,819 patent/US7470982B2/en not_active Expired - Fee Related
  • 2005-03-07 WO PCT/JP2005/003846 patent/WO2005091360A1/ja not_active Ceased

Patent Citations (6)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events