WO2004101867A1 - シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法 - Google Patents
シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法 Download PDFInfo
- Publication number
- WO2004101867A1 WO2004101867A1 PCT/JP2004/004872 JP2004004872W WO2004101867A1 WO 2004101867 A1 WO2004101867 A1 WO 2004101867A1 JP 2004004872 W JP2004004872 W JP 2004004872W WO 2004101867 A1 WO2004101867 A1 WO 2004101867A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- angle
- silicon
- single crystal
- main surface
- crystal substrate
- Prior art date
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 137
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 136
- 239000010703 silicon Substances 0.000 title claims abstract description 136
- 238000000034 method Methods 0.000 title description 7
- 239000013078 crystal Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 239000012808 vapor phase Substances 0.000 claims abstract description 15
- 238000000407 epitaxy Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 235000012431 wafers Nutrition 0.000 description 23
- 238000010586 diagram Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
- C30B23/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
Definitions
- the present invention relates to a silicon epitaxy wafer in which a silicon epitaxy layer is formed on a main surface of a silicon single crystal substrate, and a method of manufacturing the same.
- silicon epitaxial wafers have been manufactured by, for example, chamfering, slicing, lapping, etching, mirror polishing, etc. on a silicon single crystal ingot pulled up by the CZ (Czochralski) method to obtain a silicon single crystal substrate.
- CZ Czochralski
- a silicon epitaxy layer is vapor-phase grown on the main surface.
- voids minute voids
- COP Crystal Originated Particle
- the silicon epitaxial layer 2 is vapor-phase grown on the main surface 11 of the silicon single crystal substrate 1 on which the COP 100 has been formed, the surface of the silicon epitaxial layer 2 is As shown in FIGS.
- a pit 101 having a diameter of several ⁇ and a depth of several nm due to COP 100 may be formed (see, for example, JP-A-2001-684). 20 publication).
- the pit 101 is detected as an LPD (Light Point Defect) by a laser silicon surface inspection device.
- LPD 101 Light Point Defect
- FIG. 7C The width and depth of the LPD 101 are measured along the dotted line in FIG. 7B.
- Japanese Patent Application Laid-Open No. 62-226891 discloses suppression of the occurrence of tear drops, but does not disclose suppression of the occurrence of LPD caused by COP.
- the pits due to COP are generated on the surface of the silicon epitaxial layer, the pits are counted as LPD by the laser surface inspection system like crystal defects and particles.
- An object of the present invention is to provide a silicon epitaxy wafer in which generation of LPD caused by COP is suppressed, and a method of manufacturing a silicon epitaxy wafer capable of suppressing generation of LPD caused by COP. That is.
- FIG. 8 shows a position where the LPD 101 is generated when the silicon epitaxial layer 2 is grown by vapor phase. From this figure, it can be seen that the LPD 101 generation position has a high correlation with the COP 100 position, and that the LPD 101 is formed by transferring the COP 100 to the surface of the silicon epitaxial layer 2.
- the main surface of the silicon single crystal substrate was From this, it was found that by adjusting the inclination to be substantially constant only in a specific direction, it is possible to prevent the transfer of COP to the surface of the silicon epitaxial layer and, as a result, to suppress the occurrence of LPD.
- the inclination was substantially constant only in a specific direction, it is possible to prevent the transfer of COP to the surface of the silicon epitaxial layer and, as a result, to suppress the occurrence of LPD.
- the silicon epitaxial wafer of the present invention comprises:
- the main surface is inclined at an angle 0 from the (100) plane in the [011] or [0 -1-1] direction with respect to the [100] axis, and in the [01_1] or [0—11] direction. Inclined by an angle ⁇ , and
- At least one of the angle 0 and the angle 0 is not less than 0 ° and not more than 15 ′.
- the [0-1-1] direction, the [01-1] direction, and the [0-11] direction are the directions shown in FIGS. 1A to 1C.
- the main surface of the silicon single crystal substrate is off-angled by an angle of 0 from the (100) plane in the [011] direction or the [0-11] direction with respect to the [100] axis. 01 °] direction or [0—11] direction by angle ⁇ , and
- the COP of the main surface can be reduced when the silicon epitaxial layer is vapor-phase grown on the main surface of the silicon single crystal substrate. Can be prevented from being transferred to the surface of the silicon epitaxial layer. Therefore, it is possible to suppress the generation of LPD due to COP.
- the reason why at least one of the off-angle angles 0 and ⁇ is 0 ° or more and 15 or less is that the off-angle angle with respect to the (100) plane has a COP on the main surface of the silicon single crystal substrate. If both 0 and the off-angle angle ⁇ are larger than 15 ', COP is likely to be transferred to the surface of the silicon epitaxial layer, and LPD caused by COP becomes remarkable.
- the silicon epitaxial wafer of the present invention has an angle 0 ° ⁇ ⁇ 5 °, 0 ° ⁇ ⁇ 15 f
- a method for producing a silicon epitaxial wafer of the present invention comprises:
- the main surface is angled from the (100) plane in the [0 1 1] or [0—1 1] direction with respect to the [100] axis. Incline by ⁇ degrees, and incline by an angle ⁇ in the [0 1—1] or [0—1 1] direction, and
- the main surface of the silicon single crystal substrate is inclined at an angle of 0 from the (100) plane to the [011] direction or the [0-11] direction with respect to the [100] axis.
- a silicon unit that is inclined at an angle 1 in the [0 1—1] or [0—1 1] direction and at least one of the off-angle 0 and the off-angle ⁇ is 0 ° or more and 15 ′ or less.
- FIG. 1A is a diagram showing the [0—1-1] direction.
- FIG. 1B is a diagram showing the [01-1] direction.
- FIG. 1C is a diagram showing the [0-11] direction.
- FIG. 2 is a longitudinal sectional view showing a silicon epitaxial wafer according to the present invention.
- FIG. 3 is a diagram for explaining the inclination (off-angle) of the main surface of the silicon single crystal substrate.
- FIG. 4 is a diagram showing a tilt range of a main surface of a silicon single crystal substrate.
- FIG. 5 is a diagram showing the relationship between the off-angle of the main surface of the silicon single crystal substrate and the number of LPDs detected on the main surface of one silicon epitaxial wafer.
- FIG. 6 is a longitudinal sectional view showing the relationship between COP and LPD.
- FIG. 7A to 7C are diagrams showing pits detected as LPD
- FIG. 7A is a plan view of the LPD
- FIG. 7B is a perspective view of the LPD
- FIG. 7C is a longitudinal sectional view of the LPD. is there.
- FIG. 8 is a diagram showing the correlation between the position of the COP and the position of the LPD.
- FIG. 2 is a longitudinal sectional view showing the silicon epitaxial wafer W.
- silicon epitaxial wafer A A silicon single crystal substrate 1 on which a reconepitaxial layer 2 is vapor-phase grown is provided.
- COP 100 is formed on main surface 11 of silicon single crystal substrate 1.
- the main surface 11 of the silicon single crystal substrate 1 is adjusted to have a constant inclination (off-angle) substantially only in a specific direction from the (100) plane.
- off-angle the off-angle of the main surface 11 of the silicon single crystal substrate 1 will be described with reference to FIG.
- (100) plane 3 be point O.
- the crystal axes [01 1], [0-1-1], [01-1] and [0-11] passing through the O point are taken in the (100) plane 3.
- the rectangular parallelepiped 4 is arranged on the (100) plane 3. More specifically, one of the vertices of the rectangular parallelepiped 4 is placed at the point O, and the three sides gathering at this vertex are aligned with the [01 1], [01-1], and [100] axes, and the rectangular parallelepiped 4 is arranged.
- the diagonal lines OA and OB of the side surfaces 5 and 6 of the rectangular parallelepiped 4 are inclined at angles ⁇ and ⁇ with respect to the [100] axis, and the diagonal OC of the rectangular parallelepiped 4 is assumed to be silicon.
- the single crystal substrate 1 has its main surface 11 inclined at an angle of 0 from the (100) plane in the [011] direction with respect to the [100] axis and at an angle ⁇ in the [01-1] direction. Become. As shown in FIG. 4, at least one of these angles ⁇ and ⁇ is between 0 ° and 15 ′. Therefore, as shown in FIG. 2, the LPD 101 due to the transfer of the COP 100 is not generated on the surface of the silicon epitaxial layer 2.
- a silicon single crystal ingot (not shown) is pulled up by the CZ method. At this time, voids are generated in the ⁇ portion of the silicon single crystal ingot.
- the silicon single crystal ingot is sliced. More specifically, while the main surface 11 of the silicon single crystal substrate 1 to be formed is inclined at an angle 0 from the (100) plane to the [01 1] direction with respect to the [100] axis, the [01-1] Direction at an angle ⁇ , and at least one of these angles 0 and ⁇ is 0 ° or more 15 ' Slice the silicon single crystal ingot as follows. Further, surface treatment such as lapping, etching, mirror polishing and cleaning is performed to prepare a silicon single crystal substrate 1. At this time, voids appear on the main surface 11 of the silicon single crystal substrate 1, so that COP 100 is formed on the main surface 11.
- a silicon epitaxy layer 2 is vapor-phase grown on the main surface 11 of the silicon single crystal substrate 1. Then, since COP 100 on main surface 11 of silicon single crystal substrate 1 is not transferred to the surface of silicon epitaxial layer 2, it is possible to suppress the generation of LPD 101 due to COP.
- the main surface 11 of the silicon single crystal substrate 1 is in the [01 1] direction and the [01-1] direction from the (100) plane with respect to the [100] axis. Although described as being inclined, it may be inclined in the [0 1 1] and [0—1 1] directions, or in the [0—1—1] and [0—1 1] directions. It may be tilted in the [0-1-1] and [0 1-1] directions.
- a silicon epitaxial layer was vapor-phase grown on the main surface of a silicon single crystal substrate having COP and satisfying the above conditions.
- the diameter of the silicon single crystal substrate used was 200 mm.
- a silicon epitaxial layer was vapor-phase grown on the main surface of a silicon single crystal substrate having COP and satisfying the above conditions.
- the diameter of the silicon single crystal substrate used was 200 mm.
- FIG. 5 shows the number of LPDs detected on the main surface of the silicon epitaxial wafer manufactured according to the above Example 1 and Comparative Example, that is, the surface of the silicon epitaxial layer.
- the number of LPDs detected on the main surface of one silicon epitaxy laser is 100 or less, and the number of LPDs is 100 It was less than the comparative example which exceeded. In other words, generation of LPD due to COP on the main surface of the silicon single crystal substrate could be suppressed.
- Three silicon single crystal substrates (No. 1 to No. 1) whose main surface is inclined by an angle ⁇ in the [011] direction and an angle ⁇ in the [0-11] direction from the (100) plane with respect to the [100] axis. 3) was prepared.
- Table 1 shows the values of the angle 0 and the angle ⁇ of these three silicon single crystal substrates.
- the silicon epitaxial wafer and the method of manufacturing the silicon epitaxial wafer according to the present invention are suitable for suppressing the generation of LPD due to COP.
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04725526A EP1632591A1 (en) | 2003-05-15 | 2004-04-02 | Silicon epitaxial wafer, and silicon epitaxial wafer producing method |
US10/556,429 US20060281283A1 (en) | 2003-05-15 | 2004-04-02 | Silicon epitaxial wafer, and silicon epitaxial wafer manufacturing method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-137727 | 2003-05-15 | ||
JP2003137727A JP2004339003A (ja) | 2003-05-15 | 2003-05-15 | シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004101867A1 true WO2004101867A1 (ja) | 2004-11-25 |
Family
ID=33447264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/004872 WO2004101867A1 (ja) | 2003-05-15 | 2004-04-02 | シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20060281283A1 (ja) |
EP (1) | EP1632591A1 (ja) |
JP (1) | JP2004339003A (ja) |
KR (1) | KR20060016777A (ja) |
CN (1) | CN1791705A (ja) |
TW (1) | TW200500508A (ja) |
WO (1) | WO2004101867A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4508000B2 (ja) * | 2005-06-22 | 2010-07-21 | 株式会社Sumco | エピタキシャル膜の製造方法 |
TWI402896B (zh) | 2006-02-02 | 2013-07-21 | Nippon Mining Co | Substrate semiconductor growth substrate and epitaxial growth method |
TWI298209B (en) * | 2006-03-27 | 2008-06-21 | Epistar Corp | Semiconductor light-emitting device and method for fabricating the same |
JP5023900B2 (ja) * | 2006-09-05 | 2012-09-12 | 株式会社Sumco | エピタキシャルシリコンウェーハ |
JP4928494B2 (ja) * | 2008-05-02 | 2012-05-09 | 信越化学工業株式会社 | ペリクルおよびペリクルの製造方法 |
JP4934099B2 (ja) * | 2008-05-22 | 2012-05-16 | 信越化学工業株式会社 | ペリクルおよびペリクルの製造方法 |
JP5544986B2 (ja) | 2010-04-01 | 2014-07-09 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法、及び貼り合わせsoiウェーハ |
US9129823B2 (en) * | 2013-03-15 | 2015-09-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon recess ETCH and epitaxial deposit for shallow trench isolation (STI) |
JP6474048B2 (ja) * | 2015-12-25 | 2019-02-27 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
JP7103210B2 (ja) * | 2018-12-27 | 2022-07-20 | 株式会社Sumco | シリコンエピタキシャルウェーハの製造方法及びシリコンエピタキシャルウェーハ |
JP7063259B2 (ja) * | 2018-12-27 | 2022-05-09 | 株式会社Sumco | シリコンエピタキシャルウェーハの製造方法 |
DE102020000701A1 (de) * | 2020-02-03 | 2021-08-05 | Siltronic Ag | Quarzglastiegel zur Herstellung von Siliciumkristallen und Verfahren zur Herstellung von Quarzglastiegel |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62226891A (ja) * | 1986-03-28 | 1987-10-05 | Shin Etsu Handotai Co Ltd | 半導体装置用基板 |
JPH05347256A (ja) * | 1992-06-12 | 1993-12-27 | Toshiba Corp | 半導体装置用基板 |
JPH07172990A (ja) * | 1993-12-20 | 1995-07-11 | Nec Corp | 半導体基板及び半導体装置 |
JP2004091234A (ja) * | 2002-08-30 | 2004-03-25 | Sumitomo Mitsubishi Silicon Corp | エピタキシャルウェーハとその製造方法 |
-
2003
- 2003-05-15 JP JP2003137727A patent/JP2004339003A/ja active Pending
-
2004
- 2004-04-02 EP EP04725526A patent/EP1632591A1/en not_active Withdrawn
- 2004-04-02 CN CNA2004800132518A patent/CN1791705A/zh active Pending
- 2004-04-02 KR KR1020057021363A patent/KR20060016777A/ko not_active Application Discontinuation
- 2004-04-02 WO PCT/JP2004/004872 patent/WO2004101867A1/ja not_active Application Discontinuation
- 2004-04-02 US US10/556,429 patent/US20060281283A1/en not_active Abandoned
- 2004-04-12 TW TW093110127A patent/TW200500508A/zh unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62226891A (ja) * | 1986-03-28 | 1987-10-05 | Shin Etsu Handotai Co Ltd | 半導体装置用基板 |
JPH05347256A (ja) * | 1992-06-12 | 1993-12-27 | Toshiba Corp | 半導体装置用基板 |
JPH07172990A (ja) * | 1993-12-20 | 1995-07-11 | Nec Corp | 半導体基板及び半導体装置 |
JP2004091234A (ja) * | 2002-08-30 | 2004-03-25 | Sumitomo Mitsubishi Silicon Corp | エピタキシャルウェーハとその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1632591A1 (en) | 2006-03-08 |
CN1791705A (zh) | 2006-06-21 |
US20060281283A1 (en) | 2006-12-14 |
JP2004339003A (ja) | 2004-12-02 |
KR20060016777A (ko) | 2006-02-22 |
TW200500508A (en) | 2005-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2004101867A1 (ja) | シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法 | |
JP4691911B2 (ja) | Iii−v族窒化物系半導体自立基板の製造方法 | |
US9145622B2 (en) | Manufacturing method of silicon carbide single crystal | |
JP2007204286A (ja) | エピタキシャルウェーハの製造方法 | |
JP2006054428A (ja) | ウェーハの製造方法 | |
JP2008044078A (ja) | サファイア基板の研磨方法 | |
JP5212472B2 (ja) | シリコンエピタキシャルウェーハの製造方法 | |
TWI291724B (en) | Semiconductor wafer and method of manufacturing the same | |
WO2016136552A1 (ja) | C面GaN基板 | |
US11505878B2 (en) | Diamond crystal substrate, method for producing diamond crystal substrate, and method for homo-epitaxially growing diamond crystal | |
JP6722578B2 (ja) | SiCウェハの製造方法 | |
JP6647040B2 (ja) | 種結晶、種結晶の製造方法、SiCインゴットの製造方法及びSiCウェハの製造方法 | |
JP2009302140A (ja) | シリコンエピタキシャルウェーハ及びその製造方法 | |
JP6319598B2 (ja) | Ramo4基板およびその製造方法 | |
US10350725B2 (en) | RAMO4 substrate and manufacturing method thereof | |
WO2007088958A1 (ja) | 化合物半導体成長用基板およびエピタキシャル成長方法 | |
US20200406420A1 (en) | Method for polishing diamond crystal, and diamond crystal | |
US20080166891A1 (en) | Heat treatment method for silicon wafer | |
JP2019147726A (ja) | 窒化物結晶基板の製造方法、窒化物結晶基板および結晶成長用基板 | |
CN114423891B (zh) | 氮化物半导体衬底、层叠结构体和氮化物半导体衬底的制造方法 | |
EP3098839B1 (en) | Method for transferring a layer from a single-crystal substrate | |
JP6319597B2 (ja) | Ramo4基板およびその製造方法 | |
JP5810762B2 (ja) | Iii族窒化物結晶の成長方法 | |
US20170239773A1 (en) | Ramo4 substrate and manufacturing method thereof | |
KR20190126076A (ko) | Ⅲ족 질화물 반도체 기판의 제조방법, ⅲ족 질화물 반도체 기판 및 벌크 결정 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2006281283 Country of ref document: US Ref document number: 10556429 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057021363 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 20048132518 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004725526 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057021363 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2004725526 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 10556429 Country of ref document: US |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2004725526 Country of ref document: EP |