WO2004056113A1 - 映像信号処理システム、映像信号処理装置および方法、記録媒体、並びにプログラム - Google Patents
映像信号処理システム、映像信号処理装置および方法、記録媒体、並びにプログラム Download PDFInfo
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- WO2004056113A1 WO2004056113A1 PCT/JP2003/015645 JP0315645W WO2004056113A1 WO 2004056113 A1 WO2004056113 A1 WO 2004056113A1 JP 0315645 W JP0315645 W JP 0315645W WO 2004056113 A1 WO2004056113 A1 WO 2004056113A1
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- video signal
- frames
- encrypted
- processing
- encryption
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 230000005540 biological transmission Effects 0.000 claims description 24
- 238000003672 processing method Methods 0.000 claims description 9
- 238000004891 communication Methods 0.000 claims description 4
- 238000011084 recovery Methods 0.000 abstract 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 11
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000926 separation method Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000005236 sound signal Effects 0.000 description 2
- 241000233855 Orchidaceae Species 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4408—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/4367—Establishing a secure communication between the client and a peripheral device or smart card
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/4104—Peripherals receiving signals from specially adapted client devices
- H04N21/4122—Peripherals receiving signals from specially adapted client devices additional display device, e.g. video projector
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/4104—Peripherals receiving signals from specially adapted client devices
- H04N21/4135—Peripherals receiving signals from specially adapted client devices external recorder
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4405—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream decryption
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/16—Analogue secrecy systems; Analogue subscription systems
- H04N7/162—Authorising the user terminal, e.g. by paying; Registering the use of a subscription channel, e.g. billing
- H04N7/163—Authorising the user terminal, e.g. by paying; Registering the use of a subscription channel, e.g. billing by receiver means only
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/16—Analogue secrecy systems; Analogue subscription systems
- H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
- H04N7/1675—Providing digital key or authorisation information for generation or regeneration of the scrambling sequence
Definitions
- Video signal processing system video signal processing device installation method, recording medium, and program
- the present invention relates to a video signal processing system, a video signal processing apparatus and method, a recording medium, and a program, and particularly to a state where decoding of an encrypted video signal becomes impossible due to a synchronization error.
- the present invention relates to a video signal processing system, a video signal processing device and method, a recording medium, and a program capable of recovering a video more quickly.
- connection method using digital signals which is currently the mainstream connection between a PC (Personal Computer) and a liquid crystal display, be used in consumer devices such as television receivers.
- each of the transmitting side and the receiving side holds, for example, a number 10 set of a number 10-bit secret number string as a common secret number key.
- the public key selects an arbitrary half of the numerical sequence, and a new random sequence is generated.
- the transmitting device examines this numerical sequence to determine whether the other receiving device has the right to receive the signal to be transmitted, and determines that the receiving device has been properly certified. I do.
- the transmitting device circulates this sequence of numerical values with a random number generation circuit using horizontal and vertical synchronization signals serving as references for synchronizing the video signals, and converts the digital video signal using the random number sequences. It is inverted and encrypted at random and transmitted.
- the receiving side generates a random number sequence using the same numerical value sequence, inverts the video signal again, decodes the encrypted signal, and displays the original correct video signal.
- the transmitting side and the receiving side generate an encryption key from the same numerical value sequence, and generate a random number sequence using this key for the number of 10 clocks of the vertical synchronization signal period by the pixel clock of the video signal.
- the value is stored as a frame key value.
- the random number sequence is similarly cycled and stopped in the number of 10 clocks of the horizontal synchronization signal period for each next incoming video line. After that, the value is 2003/015645
- the starting point of the display period of the effective video signal is the ESD (Electro-Static
- the transmitting side has a secret value used as a reference value for random number generation in order to confirm that the connected device on the receiving side continues to be valid at intervals of about 128 frames. Is always checked, and since the reference value for random number generation is reset, the decoding error will be within 2 seconds (128 frames) at most.
- broadcasting called “dappled broadcasting”, in which signals are switched from high-resolution signal broadcasting to normal signal broadcasting or in the opposite direction, may be performed. Even in such a case, there is a problem that the "mottled broadcast” is not displayed when the decryption processing of the encryption is sent.
- the cable for digital connection may be as long as about 5 m, but the noise component in the vertical synchronization signal is incorrect due to momentary external noise such as ESD.
- ESD momentary external noise
- An object of the present invention is to make it possible to quickly recover from an undecryptable state due to a synchronization error in encryption and decryption of a video signal.
- the video signal processing system comprises: an encrypting means for encrypting a first frame number indicating a video signal and a frame number of a video signal to be transmitted based on a numerical sequence; and a first unencrypted frame number.
- a transmitting means for transmitting the video signal encrypted by the encrypting means, and the first number of frames encrypted by the encrypting means; and an unencrypted video signal transmitted by the transmitting means.
- Receiving means for receiving the number of frames of 1, the encrypted video signal, and the number of encrypted first frames, the number of encrypted first frames received by the receiving means, and encryption Decoding means for decoding the encrypted video signal based on the numerical sequence, and a second means representing the number of frames on the receiving side, generated by decoding the first number of encrypted frames by the decoding means.
- Frey The number, based on the first frame number that is not encrypted is received by the receiving means, and generating means for generating an initializing pulse, decoding means, generating T JP200 hired 5645
- the numerical sequence is initialized based on the initialization pulse generated by the means.
- the encryption unit may initialize the numerical sequence based on the initialization pulse generated by the generation unit.
- the generation unit may generate an initialization pulse when the number of frames decrypted by the decryption unit is different from the number of unencrypted frames received by the reception unit.
- the encryption unit and the transmission unit may be configured by a first video signal processing device, and the reception unit, the decryption unit, and the generation unit may be configured by a second video signal processing device. .
- the communication by the transmitting means and the receiving means can be performed via a digital interface.
- the transmitting means may further transmit a synchronization pulse for synchronizing the generation of the numerical sequence, and the receiving means may further receive the synchronization pulse.
- the video signal processing method, the program recorded on the first recording medium, and the first program according to the present invention include a video signal and a first frame number representing a frame number of a video signal to be transmitted, based on a numerical sequence. And the number of first frames that have not been encrypted, the video signal that has been encrypted by the processing of the encryption step, and the first frame that has been encrypted by the processing of the encryption step Transmitting a number, and receiving the first number of unencrypted frames, the encrypted video signal, and the first number of encrypted frames transmitted by the processing of the transmitting step. And a decryption step for decrypting the encrypted video signal received based on the number sequence, based on the numerical sequence.
- the decryption step comprising: The numerical sequence is initialized based on the initialization pulse generated by the generation step.
- the first video signal processing device of the present invention includes: an encryption unit that encrypts a video signal and a first frame number representing a frame number of a video signal to be transmitted based on a numerical sequence; Transmitting means for transmitting the number of frames, the video signal encrypted by the encryption means, and the first number of frames encrypted by the encryption means.
- the transmitting means may further transmit a synchronization pulse for synchronizing the generation of the numerical sequence.
- the second video signal processing method, the program recorded on the second recording medium, and the second program according to the present invention include a video signal and a first frame number representing a frame number of a video signal to be transmitted.
- the second video signal processing device of the present invention is configured to calculate a first frame number representing the number of frames of an unencrypted video signal, an encrypted video signal, and an encrypted first frame number.
- Receiving means for receiving, decoding means for decoding the first number of encrypted frames received by the receiving means, and the encrypted video signal based on a numerical sequence, and encryption by the decoding means A second frame number representing the number of frames on the receiving side, which is generated by decoding the first number of frames, and a first unencrypted frame number received by the receiving means.
- Generating means for generating an initialization pulse wherein the decoding means initializes the numerical sequence based on the initialization pulse generated by the generating means.
- the generation unit may generate an initialization pulse when the number of frames decrypted by the decryption unit is different from the number of unencrypted frames received by the reception unit.
- the transmitting device for transmitting an initialization pulse may be further provided to the other party that has transmitted the encrypted video signal and the first number of frames.
- the third video signal processing method of the present invention the program recorded on the third recording medium, and the third program are a first frame number representing a frame number of an unencrypted video signal, A receiving step of receiving the encrypted video signal and the number of encrypted first frames; the number of encrypted first frames received in the processing of the receiving step; A decoding step of decoding the video signal to be decoded based on the numerical sequence, and a second step representing the number of frames on the receiving side, generated by decoding the first number of frames that have been encrypted by the processing of the decoding step.
- the video signal and the first number of frames representing the number of frames of the video signal to be transmitted are encrypted based on a numerical sequence, and the first number of unencrypted frames
- the transmitted video signal and the first number of encrypted frames are transmitted and received.
- the receiving side frame generated by decoding the first number of encrypted frames and the encrypted video signal based on the numerical sequence and decoding the first number of encrypted frames.
- An initialization pulse is generated based on the second number of frames representing the number and the first number of unencrypted frames.
- the decoding numerical sequence is initialized based on the initialization pulse.
- the video signal and the first frame number representing the number of frames of the video signal to be transmitted are encrypted based on a numerical sequence, and the first unencrypted first frame number is encoded.
- the number of frames, the encrypted video signal, and the first number of encrypted frames are transmitted.
- the first number of frames representing the number of frames of an unencrypted video signal, the encrypted video signal, and the first number of encrypted frames are received.
- the encrypted first frame number and the encrypted video signal are decrypted based on the numerical sequence.
- Pulsing is generated.
- the decoding numerical sequence is initialized based on the initialization pulse.
- FIG. 1 is a block diagram showing a configuration example of a video signal processing system to which the present invention is applied.
- FIG. 2 is a flowchart illustrating a video display process in the video signal processing system of FIG.
- FIG. 3 is a flowchart illustrating a video display process in the video signal processing system of FIG.
- FIG. 4 is a block diagram showing a functional configuration of the encryption processing unit and the decryption processing unit in FIG.
- FIG. 5 is a flowchart illustrating the encryption processing in the encryption processing unit in FIG.
- FIG. 6 is a flowchart illustrating the encryption processing in the encryption processing unit in FIG.
- FIG. 7 is a flowchart illustrating a decoding process in the decoding processing unit in FIG.
- FIG. 8 is a block diagram showing the basic configuration of the LFSR.
- FIG. 9 is a diagram showing a random number sequence output from each flip-flop of the LFSR in FIG.
- FIG. 10 is a block diagram showing a basic configuration example of the encryption random number generation unit in FIG.
- FIG. 11 is a flowchart for explaining a random number generation process in the encryption random number generation unit in FIG.
- FIG. 12 is a flowchart for explaining a random number generation process in the encryption random number generation unit in FIG.
- FIG. 13 is a block diagram illustrating a basic configuration example of the decoding random number generation unit in FIG.
- FIG. 14 is a block diagram illustrating a configuration example of the correction unit in FIG.
- FIG. 15 is a flowchart illustrating a load pulse generation process in the correction unit in FIG.
- FIG. 16 is a flowchart illustrating the load pulse generation processing in the correction unit in FIG. ⁇
- FIG. 17 is a block diagram illustrating a configuration example of a personal computer. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 shows a configuration example of a video signal processing system 1 to which the present invention is applied.
- the transmitting device 11 transmitting side
- the transmitting device 11 includes a DTV (Digital 'Television) tuner 21, It is composed of an encryption processing unit 22, a DVD (Digital Versatile Disc) player 23, and an encryption processing unit 24.
- the display device 1 2 (reception side) has a selector 31 and a decryption processing unit. 32, a correction section 33, a video signal processing section 34, a video signal driving section 35, a scanning section 36, and a display panel 37.
- the symbols representing the steps represent the processing steps in the flowcharts of FIGS. 2 and 3 described later.
- the DTV tuner 21 receives an MPEG-2 digital broadcast signal received by an antenna (not shown), demodulates the signal, and supplies the demodulated video signal to the encryption processing unit 22. I do. Difficult 15645
- the DVD player 23 reproduces a DVD (not shown) and supplies the obtained digital video signal (video signal) to the encryption processing section 24.
- the encryption processing unit 22 and the encryption processing unit 24 encrypt the video signal supplied by the DTV tuner 21 or the video signal supplied by the DVD player 23, respectively. This encryption processing will be described later with reference to FIGS.
- the encryption processing unit 22 and the encryption processing unit 24 are configured to transmit the number of frames TX (vertical synchronization signal of the video signal) in the cycle. Is the number of frames obtained by counting the number of frames, and is, for example, any one of 1 to 128).
- the digital interface 2 5 is connected to the selector 3 1 of the display device 1 2, the encrypted video signal, encrypted number of frames not T x
- the HZV control signal, described later, and the number of decoded frames TX are supplied to the selector 31 via the digital interface 25.
- the digital video signal and the audio signal superimposed during the blanking period are encrypted.
- illegal copying to a VTR (Video Tape Recorder) or the like via this line is performed. (It cannot be used because it cannot be decrypted by copying).
- the encryption processing section 22 and the encryption processing section 24 determine the number of unencrypted frames T x (of course, the same number of frames as the number of encrypted frames ⁇ ⁇ ) and H /
- the V control signal is transmitted together with the encrypted video signal and the number of frames ⁇ X.
- the former two are not encrypted, but the latter two are encrypted.
- the selector 31 selects one of the signal from the encryption processing unit 22 and the signal from the encryption processing unit 24 based on an instruction from the user, and supplies the selected signal to the decryption processing unit 32.
- the decryption processing unit 32 decrypts the number of encrypted frames ⁇ .
- the number of decoded frames ⁇ X is set as the number of frames RX.
- the decryption processing unit 32 outputs the H / V control signal and the number of unencrypted frames among the input signals.
- x and the currently set number of frames R x (the number of frames TX encrypted by the encryption processing unit 22 or the encryption processing unit 24 and decrypted by the decryption processing unit 32) are corrected by the correction unit 3 Supply to 3.
- the correction unit 33 includes the number of frames TX (the number of unencrypted frames Tx) supplied from the decryption processing unit 32 and the number of frames Rx (the number of frames on the receiving side) set by the decryption processing unit 32. ) The count error is detected by comparing.
- the compensating unit 33 converts the vertical control pulse supplied from the decoding processing unit 32 into the 128 frames when the number Rx of frames on the receiving side does not match the number TX of frames on the transmitting side. Is counted as one cycle, and a load pulse is generated when the number of counted frames returns from 1 28 (about 2 seconds) to 1.
- the correction unit 33 transmits the generated load pulse to the encryption processing unit 22 or the encryption processing unit 24 (the encryption processing unit 22 or the encryption processing unit 24 of the encryption processing unit 24) via the cable 40.
- the supplied video signal is supplied to the encryption processing unit that has supplied the video signal) and the decryption processing unit 32.
- the decryption processing unit 32 performs decryption processing of the encrypted video signal based on the vertical control pulse, and when a load pulse is supplied from the correction unit 33, the encryption random number in FIG. The generator 51 is reset.
- the encryption processing unit 22 or the encryption processing unit 24 resets an internal random number generation circuit 41 (FIG. 4) described later.
- the transmission line (the transmission path of the vertical synchronization signal) between the transmission device 11 and the display device 12 is mixed with the disturbance noise signal due to, for example, ESD, and the vertical synchronization of the reception side (the display device 12) is caused.
- the correction unit 33 loads the pulse so that the encryption processing unit 22 or the encryption processing unit 24 and the decryption processing unit 32 are reset.
- a state in which decoding cannot be performed due to a synchronization error in decoding can be quickly recovered, and a decoded image can be displayed stably.
- the video signal processing section 34 processes the decoded video signal, and controls the brightness (brightness), color, hue (hue), and contrast (color) based on an instruction from the user. In addition to the adjustment of color, the white balance is adjusted.
- the signal level is converted to the optimal signal level for the display panel (display element) 37 and supplied to the video signal drive unit 35 in the horizontal (line) direction.
- the video signal drive unit 35 drives the display panel 37 based on the video signal supplied from the video signal processing unit 34.
- the video signal processing unit 34 acquires a horizontal synchronization signal and a vertical synchronization signal for synchronizing from the decoded video signal, and supplies them to the scanning unit 36 of the display panel 37.
- the scanning unit 36 sequentially controls the number of lines in the vertical direction for each drive in the horizontal line direction, and controls so as to display an image corresponding to a video signal for one frame.
- the display panel 37 performs display based on the supplied video signal under the control of the video signal drive unit 35 and the scanning unit 36.
- step S1 the DTV tuner 21 receives and demodulates an MPEG-2 digital broadcast signal received by an antenna (not shown), and converts the demodulated video signal into an encryption signal. 2 Feed to 2.
- step S2 the encryption processing unit 22 counts the vertical synchronization signal of the video signal supplied from the DTV tuner 21 to generate the number of frames Tx, and encrypts the number of frames ⁇ ⁇ and the video signal. .
- the encryption processing unit 22 sends the number of encrypted frames ⁇ ⁇ , the encrypted video signal, the HZV control signal, and the number of unencrypted frames Tx to the selector 31 via the digital interface 25. Supply. The details of this encryption processing will be described later with reference to the flowcharts of FIGS.
- step S3 the 00 player 23 reproduces a DVD (not shown) and supplies the obtained digital video signal (video signal) to the encryption processing unit 24.
- step S4 the encryption processing section 24 counts the vertical synchronization signal of the video signal supplied from the DVD player 23, generates the number of frames TX, and encrypts the number of frames TX and the video signal.
- the encryption processing unit 24 converts the number of encrypted frames Tx, the number of encrypted video signals, the H / V control signal, and the number of unencrypted frames ⁇ X into the selector 31 via the digital interface 25. To supply.
- the number of encrypted frames ⁇ can be transmitted, for example, during a horizontal blanking period.
- Step S1 and Step S2 the processing of Step S1 and Step S2 or the processing of Step S3 and Step S4 which is instructed by the user is executed.
- step S5 the selector 31 selects one of the signal from the encryption processing unit 22 and the signal from the encryption processing unit 24 based on an instruction from the user.
- step S6 the decryption processing unit 32 determines the number of encrypted frames ⁇ ⁇ ⁇ ⁇ selected by the selector 31, the encrypted video signal, the HZV control signal, and the unencrypted frame. Obtain the number ⁇ X, decrypt the number of encrypted frames ⁇ ⁇ , and set the value to the number of frames R x (the number of frames on the receiving side).
- the decryption processing unit 32 supplies the correction unit 33 with the H / V control signal, the number of unencrypted frames Tx, and the number of frames RX obtained by decryption.
- step S7 the correction unit 33 sets the number of frames R x supplied from the decryption processing unit 32 (the number of frames R x is encrypted in the encryption processing unit 22 or 24, and the decryption processing unit 3 2) and the number of frames associated with each frame of the video signal supplied from the encryption processing unit 22 or the encryption processing unit 24 ⁇ X Then, it is determined whether or not it is necessary to generate a load pulse.
- the correction unit 33 determines whether the number of frames ⁇ X does not match the number of frames RX by a predetermined number of times (for example, 16 consecutive times), or the number of supplied frames R X and T If x is the same and the number of frames (T x and R x) returns from 1 28 (about 2 seconds) to 1 (ie, about once every 2 seconds), it is necessary to generate a load pulse. judge. If it is determined in step S7 that a load pulse needs to be generated, the process proceeds to step S8, and the correction unit 33 generates a load pulse. The details of the load pulse generation processing by the correction unit 33 will be described later with reference to FIGS. 13 and 14.
- step S9 the correction unit 33 transmits the generated load pulse to the decryption processing unit 32 and the encryption processing unit 22 or 2 4 (in the processing in step S5, the encryption processing unit selected by the selector 31). Processing unit). By supplying this load pulse, the encryption processing section 22 or the encryption processing section 24 and the decryption processing section 32 are reset.
- step S7 when it is determined that the load pulse is not generated (when it is determined that the number of frames RX and the number of frames TX match), or after step S9, the process proceeds to step S10.
- the decryption processing unit 32 decrypts the encrypted video signal based on the H / V control signal supplied in the process of step S5. Note that details of the processing executed by the decoding processing unit 32 in step S6 and step S10 will be described later with reference to the flowchart in FIG.
- step S11 the decoding processing unit 32 supplies the decoded video signal to the video signal processing unit 34.
- step S12 the video signal processing unit 34 performs predetermined signal processing on the supplied video signal. Specifically, the video signal processing section 34 applies a brightness (luminance), a color, a hue (hue), and a contrast to the video signal.
- Adjustments are made based on user controls such as (color) and white balance, and converted to the optimal signal level for the display panel (display element) 37.
- step S13 the video signal processing unit 34 supplies the processed video signal to the video signal driving unit 35.
- step S14 the video signal processing unit 34 obtains a horizontal synchronization signal and a vertical synchronization signal for synchronizing from the video signal that has undergone the video signal processing, and sends them to the scanning unit of the display panel 37.
- step S15 the video signal driving section 35 drives the display panel 37 based on the video signal processed and supplied from the video signal processing section 34.
- step S16 based on the supplied horizontal synchronization signal and vertical synchronization signal, the scanning unit 36 sequentially reduces the number of lines in the vertical direction for each drive in the horizontal line direction, and Control is performed to display an image corresponding to the video signal.
- step S17 the display panel 37 displays an image based on the supplied image signal based on the control of the image signal driving unit 35 and the scanning unit 36, and ends the processing.
- the correction unit 33 is composed of the transmission side (the encryption processing unit 22 or the encryption processing unit 24 of the transmission device 11) and the reception side (the decryption processing unit 32 of the display device). If the synchronization is out of sync, or if the number of frames returns from 128 frames to one frame (every cycle of 128 frames), a load pulse is generated, and the generated load pulse is transmitted to the transmitting side (transmitting The encryption (transmission side) and decryption (reception side) are simultaneously supplied to the encryption processing section 22 or the encryption processing section 24) of the device 11 1 and the reception side (the decryption processing section 32 of the display device). It can be reset and synchronized.
- the encryption processing unit 22 includes an encryption random number generation unit 41 and an exclusive OR circuit 42.
- the decryption processing unit 32 includes a decryption random number generation unit 51 and an exclusive OR circuit. It is composed of 52.
- the decryption random number generation unit 51 decrypts the number of encrypted frames Tx, and sets the value as the number of frames RX on the receiving side.
- the decryption random number generation unit 51 transmits the vertical control pulse, the number of unencrypted frames ⁇ ⁇ ⁇ ⁇ , and the number of decrypted frames RX to the correction unit 33.
- the compensator 33 compares the number of frames TX and the number of frames RX to detect a synchronization deviation between the transmission side and the reception side, and a synchronization deviation has occurred (that is, it is necessary to generate a load pulse). ), Or generates an input pulse every 128 frames, and supplies the generated load pulse to the decryption random number generation unit 51 and the encryption random number generation unit 41.
- the decryption random number generation unit 51 and the encryption random number generation unit 41 receive the load pulse and reset the generation of the encryption or decryption random number. .
- step S2 in FIG. 2 This process is started when a video signal is supplied from the DTV tuner 21 to the encryption processing unit 22.
- step S51 the encryption random number generation unit 41 acquires a video signal to be encrypted (for example, stream data of a video signal).
- step S52 the encryption random number generation unit 41 generates a vertical control pulse, a horizontal control pulse, and a pixel clock in synchronization with the vertical synchronization signal and the horizontal synchronization signal included in the obtained video signal. I do.
- step S53 the encryption random number generation unit 41 counts the number of frames T by counting the vertical synchronization signal included in the video signal acquired in the process of step S52 as 128 frames as one cycle. Calculate X.
- step S54 the encryption random number generation unit 41 sends the secret key of the transmission side (transmission device 11) to the secret key (the encryption random number generation unit 41 holds the secret key of the transmission side).
- step S55 the random number generator for encryption 41 encrypts the number of frames T X based on the generated random number sequence.
- step S56 the encryption random number generation unit 41 supplies the generated random number sequence (the random number sequence generated by the processing in step S54) to the exclusive OR circuit 42.
- the random number sequence generation processing in steps S51 to S56 will be described later with reference to the flowcharts in FIGS. 11 and 12.
- step S57 the exclusive OR circuit 42 acquires the video signal to be encrypted, and acquires the random number sequence supplied from the encryption random number generation unit 41 by the processing in step S54.
- step S58 the exclusive-OR circuit 42 generates the random number sequence supplied from the encryption random number generation unit 41 (generated by the encryption random number generation unit 41 by the process of step S54). By calculating the exclusive OR of the random number sequence and the video signal, the bit information of the video signal to be encrypted is encrypted.
- step S59 the encryption random number generation unit 41 generates the HZV control signal including the vertical control pulse and the horizontal control pulse of the video signal and the pixel clock of the video signal, and generates the HZV control signal in step S53.
- the number of frames Tx and the number of frames Tx encrypted by the processing in step S55 are supplied to the decryption random number generation unit 51 of the decryption processing unit 32.
- step S60 the exclusive OR circuit 42 converts the video signal encrypted by the processing in step S58 into an exclusive OR circuit of the decryption processing unit 32 of the receiving side (display device 12). 5 to 2
- step S61 the encryption random number generator 41 determines whether a load pulse has been transmitted from the detector 33.
- the correction unit 33 is used when the transmission side (the encryption processing unit 22 or the encryption processing unit 24 of the transmission device 11) and the reception side (the decryption processing unit 3 2 of the display device) are out of synchronization, or
- the number of frames is 1 from 2 8 frames PC orchid 003/015645
- step S62 the encryption random number generation unit 41 receives the load pulse and resets the LFSR module 111 described later. The above processing is executed until all video signals are transmitted. If it is determined in step S61 that the load pulse has not been transmitted, the process of step S62 is skipped.
- step S6 and step S10 in FIG. 2 explains the processing of step S6 and step S10 in FIG. 2 described above in detail.
- the encrypted video signal, the HZV control signal, the number of frames Tx, and the number of encrypted frames ⁇ X are supplied from the encryption processing unit 22 to the decryption processing unit 32. It starts when it comes.
- step S101 the decryption random number generation unit 51 outputs the H / V control signal (vertical control pulse, horizontal control signal) supplied by the encryption processing unit 22 (processing of step S59 in FIG. 6).
- the control pulse and the signal consisting of the pixel clock of the video signal), the number of unencrypted frames ⁇ ⁇ , and the number of encrypted frames ⁇ X are obtained.
- step S102 the decryption random number generation unit 51 generates a random number sequence based on the received vertical control pulse and the held key. Similar to the encryption random number generation unit 41 described above, the decryption random number generation unit 51 holds a key corresponding to the secret key on the transmitting side, and stores the same initial value generated from this key in the video.
- a random number sequence is generated by cyclic driving based on the vertical control pulse of the signal, the horizontal control pulse, and the pixel clock of the video signal. At this time, the generated random number sequence is the same as the random number sequence generated by the encryption random number generation unit 41 on the transmission side.
- step S103 the decryption random number generation unit 51 decrypts the number of encrypted frames ⁇ X based on the random number sequence generated by the processing of step S102, and Set to number RX. Number of encrypted frames ⁇ X is decrypted 3 015645
- the number of frames becomes Rx on the receiving side (display device 12).
- step S104 the decryption random number generation unit 51 converts the number of unencrypted frames Tx, the number of frames Rx generated by the processing in step S103, and the HZV control signal into a correction unit. Supply 3 to 3.
- step S105 the decoding random number generation unit 51 supplies the random number sequence generated by the processing in step S102 to the exclusive OR circuit 52.
- step S106 the exclusive OR circuit 52 is supplied by the exclusive OR circuit 42 of the encryption processing unit 22 (the processing of step S60 in FIG. 5). Get the video signal that is
- step S107 the exclusive OR circuit 52 generates the encrypted video signal and the random number sequence supplied from the decryption random number generation unit 51 (generated by the processing in step S102).
- the bits of the encrypted video signal are decrypted (the random number sequence generated by the random number generation unit for encryption 41 and the random number generation unit for decryption 51) Since the random number sequence generated by is the same, it can be returned to the video signal before encryption.) As a result, the encrypted data can be decrypted.
- the exclusive OR circuit 52 transmits the decoded video signal to the video signal processing unit 34.
- step S108 the decoding random number generation unit 51 determines whether the load pulse has been transmitted from the correction unit 33.
- the correcting unit 33 determines whether it is necessary to generate a load pulse based on the number of frames Tx and the number of frames Rx transmitted by the decoding random number generation unit 51 (step S104). If it is determined that a load pulse needs to be generated (if YES is determined in step S7 of FIG. 2), a load pulse is generated and the decryption random number generation unit 51 and the encryption are generated. It is transmitted to the random number generator for use 41 (step S9 in FIG. 2). If it is determined that the load pulse has been transmitted, the process proceeds to step S109, and the decoding random number generation unit 51 resets an LFSR 'module 301 described later. In step S108, load If it is determined that no message has been transmitted, the process of step S109 is skipped. The above processing is executed until all the video signals are decoded.
- the LFSR 80 in FIG. 8 includes flip-flops 81 to 84 and, in addition, an exclusive OR circuit 90.
- the flip-flops 81 to 84 are cascaded so that the output is supplied to the subsequent stage, and the output 81Q of the flip-flop 81 and the output 84Q of the flip-flop 84 are exclusive. Input to OR circuit 90.
- the output of the exclusive OR circuit 90 is output as a random number sequence and is input to the flip-flop 81 via the switch 91.
- the LFSR & 0 is a circuit that generates an M-sequence (linear maximum periodic sequence) random number. For example, as shown in FIG. 8, when generating a 4-bit random number, the first (flip-flop 8 By inputting the latch outputs of 1) and the fourth (flip-flop 84) to the exclusive OR circuit 90, 2 4, that is, 15 clocks, based on the equation of x 4 + x + 1 It is possible to generate a random number sequence with a period.
- FIG. 9 shows a random number sequence output in each flip-flop (the flip-flops 81 to 84) of the LFSR 80 at this time.
- the vertical axis indicates the number of clocks
- the horizontal axis indicates the output of each flip-flop. That is, 81Q is the output of flip-flop 81, 82Q is the output of flip-flop 82, 83Q is the output of flip-flop 83, and 84Q is the output of flip-flop 83.
- the values of 81Q to 84Q are all set to 1, every time the clock is input, The outputs 81 Q to 84 Q of the flip-flops 81 to 84 output the values shown in FIG.
- each time a clock is input the value output by the exclusive OR circuit 90 becomes a random number.
- This value is latched by the flip-flop 81, and subsequently transferred to the subsequent flip-flops 82 to 84, so that the output of each flip-flop 81 to 84 (for example, flip-flop 8 Output of 1 8 1 Q) 1 It becomes a random number sequence.
- the cycle of the random number sequence can be lengthened. For example, when 10 latch circuits (flip-flops) are used, it is possible to generate a random number of 2 to the 10th power, that is, a cycle of 1023 clocks.
- an arbitrary initial value can be set to the flip-flops 81 to 84.
- a set / reset type latch circuit is used as the flip-flops 81 to 84, the initial value of an arbitrary random number sequence can be loaded. This makes it possible to generate an output random number sequence starting at an arbitrary timing in one cycle.
- FIG. 10 is a diagram illustrating an example of a basic configuration of the encryption random number generation unit 41.
- the random number generator for encryption 41 shuffles various bits to generate a random number with higher randomness, but the description of that part is omitted.
- the encryption random number generation unit 41 includes a plurality of LFSR modules having LFSRs having a configuration as shown in FIG. 8 (in the example of FIG. 10, the LFSR modules 11 1, 11 2 And LFSR modules 1 1 3).
- the LFSR module 1111 is supplied from the initialization numerical sequence generating unit 131.
- a numerical sequence (random number) is generated every time the vertical control pulse is input as a clock in the frame period from the vertical control pulse generator 132. It is generated and supplied to the LFSR module 112 as an initial value and to the encryption unit 180.
- the LFSR module 1 1 2 Each time the horizontal control pulse is input as a clock in the horizontal scanning period from the horizontal control pulse generator 151, the LFSR module 1 1 2 Generates a sequence (random number) and supplies it to the LFSR module 113 as an initial value.
- the AND circuit 15 3 conducts when an enable signal is input from the vertical display area enable signal generation unit 15 2, and outputs the horizontal control pulse generated by the horizontal control pulse generation unit 15 1 to the LFSR.
- Supply module 1 1 2
- the LFSR module 113 is provided with a numerical sequence supplied from the LFSR module 112 every time a pixel clock is input at a pixel cycle from the pixel clock generator 171 via the AND circuit 173. Generates a numerical sequence (random number) with as the initial value and outputs it to the exclusive OR circuit 42.
- the AND circuit 173 conducts when an enable signal is input from the horizontal display area enable signal generator 172, and outputs the pixel clock output from the pixel clock generator 171 to the LFSR module 111. Supply to 3.
- the vertical control pulse generator 1332 generates a vertical control pulse in synchronization with a vertical synchronization signal included in a video signal (video signal to be transmitted) input from the DTV tuner 21.
- the vertical control pulse generated by the vertical control pulse generator 1 32 is supplied to the LFSR module 111, the HZV control signal generator 133, and the vertical display area enable signal generator 1 '52 Input to 2.
- the HZV control signal generator 1 3 3 counts the vertical control pulses supplied from the vertical control pulse generator 1 32 as 128 cycles as one cycle, and calculates the number of frames T x (1 to 1 28 And the vertical control pulse, the horizontal control pulse generated by the horizontal control pulse generator 151, and the pixel clock generated by the pixel clock generator 171, are synthesized. Generate HZV control signal.
- the H / V control signal generator 1 3 3 calculates the number of generated frames ⁇ ⁇
- the H / V control signal is supplied to the correction unit 33, and the number of frames TX is supplied to the encryption unit 180.
- the encryption unit 180 encrypts the number of frames TX supplied from the HZV control signal generation unit 133 based on the numerical sequence supplied for each frame from the LFSR module 111, and encrypts the correction unit 3. Supply to 3.
- the vertical display area enable signal generator 152 generates a vertical display area enable signal corresponding to a valid vertical display area based on the vertical control pulse supplied from the vertical control pulse generator 132. Is generated and supplied to the AND circuit 15 3.
- the horizontal control pulse generator 15 1 generates a horizontal control pulse in synchronization with a horizontal synchronization signal included in the video signal (video signal to be transmitted) input from the DTV tuner 21.
- the horizontal control pulse generated by the horizontal control pulse generator 15 1 is supplied to the LFSR module 1 12 via the AND circuit 15 3, the HZV control signal generator 13 3 and the horizontal display
- the signal is input to the area enable signal generation unit 172.
- the horizontal display area enable signal generation unit 1772 generates a horizontal display area enable signal corresponding to an effective horizontal display area based on the horizontal control pulse, and supplies the generated horizontal display area enable signal to the AND circuit 173.
- the pixel clock generation unit 171 generates a pixel clock in synchronization with a vertical synchronization signal and a horizontal synchronization signal included in a video signal (video signal to be transmitted) input from the DTV tuner 21.
- a vertical control pulse, a horizontal control pulse, and a pixel clock are generated from the same video signal input from the DTV tuner 21. Therefore, in all of the vertical control pulse, the horizontal control pulse, and the pixel clock, Synchronization can be achieved, so that the random number sequence generated by the LFSR module 113 can be synchronized with this video signal.
- the process is started when the video signal to be encrypted is input to the encryption random number generation unit 41 (after the process of step S1 or step S3 in FIG. 2).
- step S151 the vertical control pulse generator 1332 synchronizes with the vertical synchronization signal included in the video signal (video signal to be transmitted) input by the DTV tuner 21 to generate a vertical control pulse.
- the vertical control pulse generator 1332 supplies the generated vertical control pulse to the LFSR module 111, HZV control signal generator 133, and vertical display area enable signal generator 152. .
- step S152 the horizontal control pulse generation unit 1551 synchronizes with a horizontal synchronization signal included in the video signal (video signal to be transmitted) input by the DTV tuner 21 to generate a horizontal control pulse.
- the horizontal control pulse generator 15 1 supplies the generated horizontal control pulse to the AND circuit 15 3, the H / V control signal generator 13 3, and the horizontal display area enable signal generator 17 2 I do.
- step S153 the pixel clock generation unit 1771 generates a pixel clock so as to synchronize with a pixel signal included in the video signal (video signal to be transmitted) input by the DTV tuner 21.
- step S154 the H / V control signal generation unit 133 transmits the vertical control pulse supplied from the vertical control pulse generation unit 132 in the processing of step S151 for one cycle of 128 frames. And calculate the number of frames Tx. Further, the ZV control signal generator 133 combines the vertical control pulse, the horizontal control pulse, and the pixel clock to generate an HZV control signal. Then, the H / V control signal generation unit 133 transmits the calculated number of frames ⁇ X and the H / V control signal to the decoding random number generation unit 51 of the decoding unit 32, and calculates the number of frames ⁇ X Sent to encryption section 180. Note that the number of frames ⁇ is further supplied from the decoding random number generation unit 51 to the correction unit 33.
- step S155 the LFSR module 111 receives the input pulse from the correction unit 33.
- Correction unit 3 3 includes a number of frames counted vertical control pulses 1 2 8 frames as one cycle returns to 1 frame from 1 2 8 frame 1564S
- a load pulse is generated and supplied to the LFSR module 111 (Ste S210 of FIG. 14 described later). At the start of the random number generation process, a load pulse is always input.
- step S156 the initialization numerical sequence generation unit 1311 generates an initialization numerical sequence based on the secret key preset in the encryption random number generation unit 41. Supply to the LFSR module 1 1 1
- step S157 the LFSR module 111 is supplied from the initialization numerical sequence generator 131 when a load pulse is input from the corrector 33 by the processing of step S155.
- Step S156 The initial values are loaded.
- step S158 the LFSR module 111 generates a numerical sequence (random number) based on the initial value loaded by the processing in step S157. Thereafter, the LFSR module 111 generates a numerical sequence (random number) every time a vertical control pulse is input as a clock from the vertical control pulse generator 1332 at a frame period. This numerical sequence is a numerical sequence generated for each frame.
- step S159 the LFSR module 111 supplies the generated numerical sequence to the LFSR module 112 and also supplies the encryption unit 180.
- step S160 the encryption unit 180 converts the numerical sequence supplied from the LFSR module 111 (step S159) into the frame supplied from the H / V control signal generation unit 133. Obtain the number T x (step SI54) and encrypt the frame number T x based on the numerical sequence.
- the encryption section 180 transmits the number of encrypted frames ⁇ to the correction section 33.
- step S161 the vertical display area enable signal generating unit 152, based on the vertical control pulse supplied from the vertical control pulse generating unit 132 by the processing of step S151, A vertical display area enable signal is generated. Specifically, based on the position of the input vertical control pulse, it is determined whether or not the target line is an effective vertical display area, and if it is within the vertical display area, logic An H (1) signal is output, and a logic L (0) signal is output when the signal is not within the vertical display area.
- the vertical display area enable signal generator 152 supplies the generated vertical display area enable signal to the AND circuit 153.
- step S162 the AND circuit 1553 conducts when the vertical display area enable signal supplied from the vertical display area enable signal generation section 152 is logic H (1), and the logic ( At 0), it becomes non-conductive. That is, the AND circuit 153 is turned on when the enable signal (logic H (1)) is input from the vertical display area enable signal generator 152, and the horizontal control pulse generator 153 is turned on. The generated horizontal control pulse (step S 15 2) is supplied to the LFSR module 112. When an enable signal (a logical (0) enable signal) is input, the AND circuit 153 becomes non-conductive and does not output the horizontal control pulse to the LFSR module 112.
- step S163 the LFSR module 111 is supplied from the LFSR module 111 when the horizontal control pulse is input as a clock from the horizontal control pulse generator 151 (step S152).
- a numerical sequence (random number) is generated with the numerical sequence (the process of step S159) as an initial value.
- the LFSR module 112 generates a numerical sequence (random number) each time a horizontal control pulse is input as a clock from the horizontal control pulse generator 151. This numerical sequence is a numerical sequence generated for each line.
- step S164 the LFSR module 112 supplies the generated numerical sequence to the LFSR module 113.
- step S165 the horizontal display area enable signal generation unit 1772 performs the processing in step S152, based on the horizontal control pulse supplied from the horizontal control pulse generation unit 151.
- a horizontal display area enable signal is generated. Specifically, based on the position of the input horizontal control pulse, the H (1) signal is output when the timing is within the valid horizontal display area, and the timing is not valid for the valid horizontal display area. At this time, a signal of L (0) is output.
- the horizontal display area enable signal generating section 172 supplies the generated horizontal display area enable signal to the AND circuit 173. 3 015645
- step S166 the AND circuit 173 is turned on based on the horizontal display area enable signal supplied from the horizontal display area enable signal generation unit 172. That is, the AND circuit 173 becomes conductive when the enable signal (logic H (1)) is input from the horizontal display area enable signal generator 172, and the pixel clock generator 171 generates the signal.
- the pixel clock (step S153) is supplied to the LFSR module 113.
- an AND enable signal (a logical (0)) enable signal is input, the AND circuit 173 is turned off, and the pixel clock is not supplied to the LFSR module 113.
- step S167 the LFSR module 113 receives the pixel clock as a clock from the pixel clock generator 171 (step S153 and step S166), and the LFSR module 113 A numerical sequence (random number) is generated using the numerical sequence supplied from 2 (processing in step S164) as an initial value. Thereafter, the LFSR module 113 generates a numerical sequence (random number) each time the pixel clock is input as a clock from the pixel clock generation unit 171. This numerical sequence is a numerical sequence generated for each pixel.
- step S168 the LFSR module 113 outputs the generated numerical sequence (random number) to the exclusive OR circuit 42.
- the LFSR module 113 generates a numerical sequence (random number) each time the pixel clock is input as a clock from the pixel clock generation unit 171.
- the initial value that is, the numerical sequence of the leftmost (leading) pixel of each line is set based on the numerical sequence (random number) output by the LFSR module 112.
- the LFSR module 1 13 finishes generating a line of numerical values for one line based on the pixel crop from the pixel crop generator 171
- the LFSR module 1 1 2 returns the left end of the next line.
- the initial value of the (top) pixel is input.
- the LFSR module 113 again generates a numerical sequence each time the pixel clock is input as a clock from the pixel clock generation unit 171.
- the LFSR module 1 12 finishes generating the numerical sequence at the left end (head) of each line for one frame based on the horizontal control pulse from the horizontal control pulse generator 15 1, the LFSR module generates a vertical control pulse.
- the initial value of the first line (head) of the next frame is input.
- the LFSR module 112 Based on the initial value, the LFSR module 112 generates a numerical sequence each time a horizontal control pulse is input as a clock from the horizontal control pulse generator 151.
- the LFSR module 1 1 1 uses the value output from the initialization value sequence generation unit 13 1 as an initial value and generates a value sequence (random number) every time a vertical control pulse is input as a clock from the vertical control pulse generation unit 13 2 Generate Then, the LFSR module 1 1 1 generates a load pulse from the correction unit 3 3 when the transmission side and the reception side are out of synchronization (the number of frames T x and R x are different) or every 128 frames. Since it is input, the initial value supplied from the initialization value sequence generator 1 3 1 is loaded again.
- the initial value is set for each line, every frame, or every 128 frames, and the random number is initialized every line, every frame, or every 128 frames. Therefore, the propagation of the error backward is suppressed.
- the capture unit 33 if an error occurs in the generated random numbers, the capture unit 33 generates an input pulse (temporary load pulse other than every 128 frames) for initialization (reset), and the random numbers are initialized. Therefore, it is possible to prevent an error from occurring even if 128 frames have not elapsed since the last initialization.
- the random number generator 41 for encryption on the transmitting side updates the random number sequence at each starting point of each line, at each starting point of each frame, and every 128 frames.
- the receiving-side decryption random number generator 51 also performs synchronization at each line start point, at each frame start point, and at every 128 frames in the same manner. And generate the exact same random number sequence.
- the load pulse from the correction unit 33 is supplied to both the encryption random number generation unit 41 on the transmission side and the decryption random number generation unit 51 on the reception side. 4 1 and decoding disturbance on the receiving side JP2003 / 015645
- the number generator 51 generates the same random number sequence.
- the configuration of the correction unit 33 will be described later with reference to FIG.
- the decoded video signal output from the exclusive OR circuit 42 of the transmitting side is output to the exclusive OR circuit 5 of the receiving side (display device 12). 2 received by Also, the H / V control signal composed of the vertical control pulse, the horizontal control pulse, and the pixel clock output from the encryption random number generator 41 on the transmitting side, the number of unencrypted frames Tx, and The number Tx of encrypted frames is received by the decryption random number generation unit 51 on the receiving side. The decryption random number generation unit 51 decrypts the number Tx of encrypted frames and generates the number RX of frames on the receiving side.
- the decoding random number generation unit 51 supplies the number of frames Rx on the receiving side, the vertical control pulse, and the number of frames Tx on the transmitting side to the correction unit 33.
- the correction unit 33 generates a word pulse as necessary, and supplies it to the decryption random number generation unit 51 (and the encryption random number generation unit 41).
- FIG. 13 is a diagram showing a basic configuration example of the decoding random number generation unit 51. As shown in FIG. As is apparent from a comparison of FIG. 13 with FIG. 10, the decryption random number generator 51 of FIG. 13 has basically the same configuration as the encryption random number generator 41 of FIG. Have been.
- the random number generation unit 51 for initialization includes a numerical sequence generation unit for initialization 3 31, LFSR modules 301 to 303, a horizontal control pulse generation unit 351, a vertical display area enable signal generation unit 35 2 A pixel clock generation section 371, a horizontal display area enable signal generation section 372, AND circuits 3553, 3733, and a decoding processing section 380. Those with corresponding names have corresponding functions.
- the encryption unit 180 of the random number generator for encryption 41 encrypts the number of frames TX based on the random number sequence from the LFSR module 111, whereas the random number generator for decryption 51
- the decoding processing unit 380 of the frame decodes the number of frames Tx based on the random number sequence from the LFSR module 301.
- a separation unit 3 3 2 that separates the H / V control signal supplied from the HZV control signal generation unit 13 3 of the encryption random number generation unit 41 into a vertical control pulse, a horizontal control pulse, and a pixel clock Is provided.
- the separation unit 332 outputs the vertical control pulse to the vertical control signal generation unit 3333, outputs the horizontal control pulse to the horizontal control pulse generation unit 351, and outputs the pixel clock to the pixel clock generation unit 3. 7 Output to 1 to generate a vertical sync pulse, horizontal control pulse, or pixel clock on the receiving side, respectively.
- Separating section 3332 also separates the number of frames ⁇ ⁇ and outputs the result to correction section 33.
- step S151 the generated vertical control pulse is output not to the H / V control signal generation unit 133 but to the correction unit 33.
- step S154 the H / V control signal generation unit 133 does not execute the generation and transmission of the H / V control signal and the number of frames. Instead, the separation unit 33 outputs the number of separated frames ⁇ ⁇ to the correction unit 33.
- step S160 the number of frames by the encryption unit 180 in the encryption unit ⁇ X is determined by the number of frames encrypted by the decryption processing unit 380 ⁇ The number of frames by the decryption of X This is replaced with the process of generating Rx and outputting it to the correction unit 33.
- FIG. 14 is a diagram illustrating a detailed configuration example of the correction unit 33 of FIG.
- the comparison unit 201 has a function of a comparator and a counter, and is output from the encryption random number generation unit 41 and supplied through the decryption random number generation unit 51 (see step S1 in FIG. 11). 1 54 and the processing of step S 16 0 and the corresponding processing performed by the decoding random number generation unit 51 1)
- the number of frames TX and the number of frames RX are compared, and the values of T x and R X are calculated. If does not match, it is counted. Note that this The count is reset when the values of the frame numbers Tx and Rx match (that is, they are counted only when there is a continuous mismatch).
- the comparing unit 201 determines that the synchronization between the transmitting side and the receiving side is out of synchronization, and performs a logical operation.
- the control signal of (0) is transmitted to the CPU 202.
- the CPU (Central Processing Unit) 202 is a pseudo load that resets the random number generation on the sending side and the receiving side when it receives a control signal of logic L (0) from the comparing section 201. Generate a pulse (ie, a temporary load pulse that is not a 128 frame period) and provide it to the OR circuit 204.
- a pulse ie, a temporary load pulse that is not a 128 frame period
- the load pulse generation unit 203 synchronizes with the vertical control pulse output from the encryption random number generation unit 41 (the process of step S 15 1 in FIG. 11) to generate the decryption random number generation unit 51.
- the vertical control pulse output from the vertical control pulse generator 3 3 3 (process corresponding to step S 15 1 in FIG. 11)
- the vertical control pulses are counted as 1 cycle of 128 frames, and the number of counted frames is 1 2 When returning from 8 to 1 (when one cycle (about 2 seconds) elapses), a load pulse is generated and supplied to the OR circuit 204.
- the OR circuit 204 uses the pseudo load pulse supplied from the CPU 202 or the load pulse supplied from the load pulse generation unit 203 as the load pulse generated by the correction unit 33. It is supplied to the encryption random number generator 41 of the encryption processor 22 or the encryption processor 24 and the decryption random number generator 51 of the decryption processor 32.
- step S201 the comparison unit 201 determines the number of frames TX and the number of frames RX (the number of frames TX and the number of frames supplied from the decoding random number generation unit 51 by the processing of step S104 in FIG. 7). RX) is determined. If it is determined that the number of frames TX and the number of frames Rx have not been received, the process proceeds to step S202. 03 015645
- the load pulse generation unit 203 determines whether a vertical control pulse has been received. If it is determined that the vertical control pulse has not been received, the process returns to step S201, and the process is repeated.
- step S203 the processing proceeds to step S203, where the load pulse generation unit 203 outputs the vertical control pulse for one cycle of 128 frames. And count (count).
- step S204 the load pulse generator 203 determines whether or not the value counted (counted) by the process in step S203 is 128. If the count value is not 128, the process returns to step S201, and the subsequent processes are repeated.
- step S205 the load pulse generation unit 203 generates a load pulse. That is, the load pulse generation unit 203 generates a load pulse when the number of vertical control pulses counted from 128 frames as one cycle returns to 1 from 128 (about 2 seconds).
- step S206 the load pulse generator 203 supplies the generated load pulse to the OR circuit 204.
- step S207 the OR circuit 2.04 supplies the load pulse supplied from the load pulse generation unit 203 to the encryption processing unit 22 and the decryption processing unit 32. Returning to 201, the same processing is repeated.
- step S201 determines the number of received frames Tx and It is determined whether the number of frames Rx is the same.
- the number of frames Tx is a value obtained by counting the vertical synchronization pulses by the H / V control signal generation unit 133 and transmitted without being encrypted, and the value is encrypted and transmitted.
- the value that has been decoded by the decoding unit 380 is the number of frames Rx. Therefore, the number of frames TX and Rx usually coincide. However, for example, when the channel is switched or the playback video signal is switched, the synchronization signal is discontinuous, and thus the synchronization is disturbed.
- step S208 If it is determined in step S208 that the number of frames T X and the number of frames RX are not the same (different), in step S209, the comparing unit 201 adds 1 to the power counter. In this case, the counter value is 1.
- step S210 the comparing section 201 determines whether or not the value of the counter is 16.
- the value of the counter is incremented each time the number of frames TX and the number of frames RX are different, and is reset when the number of frames TX and the number of frames RX match (step S214 described later). Indicates the number of times that the value of the number of frames RX does not match continuously. If it is determined that the value of the counter is not 16, the process returns to step S201, and the subsequent processes are repeated. That is, the same processing is repeated until the counter value becomes 16.
- step S210 when it is determined that the counter value is 16 (when it is determined that the number of frames T x and the number of frames R x do not match 16 consecutive times), the channel It is determined that the synchronization has been disturbed due to switching or signal switching, and the processing proceeds to step S211.
- step S211 the comparing section 201 outputs a control signal of logic L (0) to the CPU 202.
- the synchronization may be erroneously detected due to noise, etc., and the mismatch is detected multiple times (in this example, 16 times). It is determined that a synchronization disorder has occurred.
- the pseudo load pulse (that is, the temporary port other than the 128 frame period) Pulse).
- the CPU 202 supplies the generated pseudo load pulse to the OR circuit 204.
- step S213 the OR circuit 204 supplies the pseudo load pulse to the encryption processing unit 22 and the decryption processing unit 32, returns to step S201, and the same processing is repeated. It is.
- step S214 the comparison unit 201 resets the counter (sets the counter value to 0). To).
- the counter is reset so that the counter can indicate the number of times that the number of frames ⁇ ⁇ and the number of frames RX do not match continuously. Thereafter, the process returns to step S201.
- the transmitting side the number of frames ⁇ ⁇ representing the number of frames of the video signal to be transmitted, the number of encrypted frames ⁇ ⁇ , and the H comprising the vertical control pulse, the horizontal control pulse, and the pixel block / V control signal is transmitted, and the receiving side decrypts the number of encrypted frames ⁇ X to generate the number of frames R x on the receiving side, and compares the number of frames T x with R x
- Won 15645 since a pseudo-pulse is generated as needed, even if the transmission side and the reception side are out of synchronization, it can be quickly corrected.
- a video signal processing system can be constructed so that decryption is always performed in a stable manner so that the correction is automatically performed and the synchronization between encryption and decryption is not lost.
- the random number generation unit (the random number generation unit for encryption 41 and the random number generation unit for decryption 51) is reset every 128 frame periods (load pulse generation unit 203). Eight frames are counted as one cycle, and a load pulse is generated when the counted frame number returns from 128 to 1). Therefore, the encryption processing unit 22 and the decoding processing unit 32 are periodically switched. Synchronization can be achieved, so that in the decryption of an encrypted video signal, it is possible to periodically recover a state where decryption cannot be performed due to synchronization deviation. .
- a pseudo load pulse is generated when the number of frames T x and R x do not match for 16 consecutive times. It can be the number of times.
- Fig. 17 The program stored in the CPU (Central Processing Unit) 601 and the ROM (Read Only Memory) 602 or the storage unit 608 Random Access Memory) Executes various processes in accordance with the program loaded in 603.
- the RAM 603 also appropriately stores data necessary for the CPU 601 to execute various processes.
- the CPU 601, R0M 602, and RAM 603 are interconnected via an internal bus 604.
- the internal bus 604 is also connected to an input / output interface 605. 15645
- the input / output interface 605 has an input section 606 consisting of a keyboard, mouse, etc., a display consisting of a CRT, LCD (Liquid Crystal Display), etc., an output section 607 consisting of speakers, etc., a hard disk, etc.
- a storage unit 609 composed of a modem and a terminal adapter is connected.
- the communication unit 609 performs communication processing via various networks including a telephone line and CATV.
- a drive 61 is connected to the input / output interface 605 as necessary, and a removable medium 621 made of a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is appropriately mounted.
- the read computer program is installed in the storage unit 608 as necessary.
- the programs that make up the software are installed on a computer that is built into dedicated hardware, or by installing various programs, It is installed from a network or a recording medium to a general-purpose personal computer, for example, capable of executing a function.
- this recording medium is constituted by a package medium consisting of a removable medium 621 on which the program is recorded, which is distributed to provide the user with the program, separately from the computer. Not only that, it is also provided with a ROM 602 in which programs are stored and a hard disk including a storage unit 608, which is provided to the user in a state of being incorporated in the apparatus main body in advance.
- steps to describe a computer program are not only processes performed in chronological order according to the order described, but also processes performed in parallel or individually even if not necessarily performed in chronological order. Is also included.
- the term “system” refers to an entire device including a plurality of devices.
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/503,695 US7649993B2 (en) | 2002-12-13 | 2003-12-08 | Video-signal processing system, video-signal processing apparatus and method, recording medium, and program |
EP03777331A EP1473938A4 (en) | 2002-12-13 | 2003-12-08 | Video signal processing system, video signal processing apparatus and method, recording medium and program |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002361690A JP4214454B2 (ja) | 2002-12-13 | 2002-12-13 | 映像信号処理システム、映像信号処理装置および方法、記録媒体、並びにプログラム |
JP2002-361690 | 2002-12-13 |
Publications (1)
Publication Number | Publication Date |
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WO2004056113A1 true WO2004056113A1 (ja) | 2004-07-01 |
Family
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Family Applications (1)
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PCT/JP2003/015645 WO2004056113A1 (ja) | 2002-12-13 | 2003-12-08 | 映像信号処理システム、映像信号処理装置および方法、記録媒体、並びにプログラム |
Country Status (6)
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US (1) | US7649993B2 (ja) |
EP (1) | EP1473938A4 (ja) |
JP (1) | JP4214454B2 (ja) |
KR (1) | KR100983939B1 (ja) |
CN (1) | CN100358362C (ja) |
WO (1) | WO2004056113A1 (ja) |
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JP5442661B2 (ja) * | 2011-03-30 | 2014-03-12 | 株式会社三共 | 遊技用システムおよび遊技用装置 |
JP5442662B2 (ja) * | 2011-03-30 | 2014-03-12 | 株式会社三共 | 遊技用システムおよび遊技用装置 |
JP2013046364A (ja) * | 2011-08-26 | 2013-03-04 | Thine Electronics Inc | 送信装置、受信装置および送受信システム |
US10171710B2 (en) | 2012-04-04 | 2019-01-01 | Mitsubishi Electric Corporation | Device and method for digital data distribution, device and method for digital data reproduction, synchronized reproduction system, program, and recording medium |
USD711959S1 (en) | 2012-08-10 | 2014-08-26 | X6D Limited | Glasses for amblyopia treatment |
CN104065995B (zh) * | 2013-03-22 | 2017-09-22 | 晨星半导体股份有限公司 | 信号取样方法、数据加解密方法以及使用这些方法的电子装置 |
TWI547134B (zh) * | 2014-07-09 | 2016-08-21 | 瑞昱半導體股份有限公司 | 解密引擎以及解密方法 |
KR102406186B1 (ko) * | 2020-11-16 | 2022-06-10 | 주식회사 바이오로그디바이스 | 지문 이미지 데이터 암호화를 위한 지문 센싱 시스템 |
CN114697463B (zh) * | 2020-12-31 | 2023-11-21 | 思特威(上海)电子科技股份有限公司 | 加密传输方法及图像传感器 |
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2002
- 2002-12-13 JP JP2002361690A patent/JP4214454B2/ja not_active Expired - Fee Related
-
2003
- 2003-12-08 CN CNB2003801002165A patent/CN100358362C/zh not_active Expired - Fee Related
- 2003-12-08 WO PCT/JP2003/015645 patent/WO2004056113A1/ja active Application Filing
- 2003-12-08 KR KR1020047011858A patent/KR100983939B1/ko not_active IP Right Cessation
- 2003-12-08 EP EP03777331A patent/EP1473938A4/en not_active Withdrawn
- 2003-12-08 US US10/503,695 patent/US7649993B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
US20050213759A1 (en) | 2005-09-29 |
CN1692649A (zh) | 2005-11-02 |
JP2004194143A (ja) | 2004-07-08 |
JP4214454B2 (ja) | 2009-01-28 |
EP1473938A4 (en) | 2009-03-25 |
US7649993B2 (en) | 2010-01-19 |
CN100358362C (zh) | 2007-12-26 |
KR100983939B1 (ko) | 2010-09-27 |
KR20050084769A (ko) | 2005-08-29 |
EP1473938A1 (en) | 2004-11-03 |
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