WO2004032223A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2004032223A1 WO2004032223A1 PCT/JP2002/010177 JP0210177W WO2004032223A1 WO 2004032223 A1 WO2004032223 A1 WO 2004032223A1 JP 0210177 W JP0210177 W JP 0210177W WO 2004032223 A1 WO2004032223 A1 WO 2004032223A1
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- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor chip
- semiconductor device
- wire
- resin
- solder
- Prior art date
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a semiconductor manufacturing technology, and more particularly to a technology effective when applied to a high-frequency module.
- a module product semiconductor device on which chip components such as chip capacitors and chip resistors and semiconductor chips for bear chip mounting are mounted
- a high-frequency module also called RF module or RF power module
- the so-called chip chip and semiconductor chip are mounted on the module board by solder connection, and both are covered and protected by insulating resin.
- Japanese Patent Laid-Open No. 2000-223623 discloses that the elastic modulus of the first resin covering the wire-bonded semiconductor chip and the wire is made larger than the elastic modulus of the second resin covering the outside. A technique is described in which the first resin is harder than the second resin, and as a result, the deformation of the first resin due to thermal stress is suppressed to prevent the wire from being disconnected.
- a surface-mounted component to be soldered and its solder connection part are covered with a low elastic resin having a modulus of elasticity of 20 OMPa or less at a temperature of 150 ° C. or more, Even if the internal solder joints are remelted when mounting the semiconductor device with the secondary mounting reflow, the pressure due to the melt expansion is relieved by the low-elasticity resin, to the interface between the surface mount component and the resin. It describes a technology that prevents the solder from flowing out and prevents the occurrence of shorts between terminals of surface-mounted components.
- the present inventor has found the following problems regarding a semiconductor device having a structure in which the above-described chip component (surface-mounted component) and a semiconductor chip are mounted and both are covered with a resin.
- the present inventor found that the wire breakage has a correlation with the loop height and length of the wire, but Japanese Patent Application Laid-Open No. 2002-208668 has no description of the wire breakage.
- Japanese Patent Laid-Open No. 2000-223623 discloses a technique for preventing wire breakage, but does not describe wire loop height or length.
- the object of the present invention is to prevent bonding wire breakage. It is to provide a semiconductor device.
- Another object of the present invention is to provide a semiconductor device that can improve reliability.
- the present invention includes a semiconductor chip, a wiring board on which the semiconductor chip is mounted, a plurality of bonding wires that connect surface electrodes of the semiconductor chip and corresponding terminals of the wiring board, the semiconductor chip, and the semiconductor chip
- a plurality of bonding wires are encapsulated with resin and sealed with an insulating elastic resin, and the elastic resin has an elastic modulus of 1 to 200 MPa at a temperature of 150 ° C or higher.
- the height from the main surface of the semiconductor chip to the apex of the bonding wire is 0.2 mm or less.
- the present invention also includes a semiconductor chip, and a wiring board on which the semiconductor chip is mounted.
- a plurality of surface electrodes of the semiconductor chip connected to the corresponding terminals of the wiring board, and a height from the main surface of the semiconductor chip to the top of the wire is 0.2 mm or less.
- the formed sealing portion is connected to the mounting substrate with solder.
- FIG. 1 is a plan view showing the structure of a high-frequency module as an example of a semiconductor device according to an embodiment of the present invention
- FIG. 2 is a side view showing the structure of the high-frequency module shown in FIG. 1
- FIG. 3 is the high-frequency module shown in FIG. 4 is a side view showing the structure of the high-frequency module shown in FIG. 1 as viewed from A
- FIG. 5 is an example of the arrangement of each surface-mounted component mounted on the high-frequency module shown in FIG.
- Fig. 6 is a partial cross-sectional view showing the structure of a cross section taken along the line B-B shown in Fig. 5, and Fig.
- FIG. 7 is a cross-sectional view showing an example of the allowable range of the bonding wire in the high-frequency module shown in Fig. 1.
- Fig. 8 is an enlarged partial sectional view showing an example of the solder connection structure of the chip component shown in Fig. 6, and
- Fig. 9 shows an example of temperature characteristics of the low elastic resin used in the sealing portion of the high frequency module shown in Fig. 1.
- Figure 10 shows the characteristics shown in Figure 1
- FIG. 11 is an evaluation result diagram showing an example of the number of occurrences of cracks in the evaluation of the wire height of the high-frequency module.
- FIG. 11 is an evaluation result diagram showing an example of the number of occurrences of disconnection in the evaluation of the wire height of the high-frequency module shown in FIG. Fig.
- FIG. 12 is a partially enlarged view showing an example of a wire crack in the high-frequency module shown in Fig. 1.
- Fig. 13 is a distribution diagram showing an example of wire crack in the high-frequency module shown in Fig. 1.
- Fig. 14 Is a partially enlarged view showing an example of wire breakage in the high-frequency module shown in FIG. 1.
- FIG. 15 is a partially enlarged side view showing an example of a mounting structure of the high-frequency module shown in FIG. 1 on a mounting board. 22 is a partially enlarged cross-sectional view showing the structure of a high-frequency module according to a modification of the embodiment of the present invention.
- the semiconductor device of the present embodiment shown in FIGS. 1 to 4 is a module product called a high-frequency module 1, and the mounting component is solder-mounted on the module substrate 4, and the mounting component Has a structure that is covered with a sealing resin, and is mainly incorporated in small portable electronic devices such as portable telephones.
- the configuration of the high-frequency module 1 includes a main surface 2 and a semiconductor chip 2 that is a mounting component in which a plurality of pads (surface electrodes) 2 a are formed, and connection terminals at both ends.
- Chip component 3 which is a mounting component on which 3d is formed
- module substrate 4 which is a wiring board on which semiconductor chip 2 and chip component 3 are mounted
- chip component 3 and terminal 4 a of module substrate 4 And the semiconductor chip 2 and the module board 4 are connected by soldering, and the solder connection part 5 shown in FIG. 6 is connected to the pad 2a of the semiconductor chip 2 and the terminal 4a of the module board 4 corresponding thereto.
- the chip component 3 that is solder-connected to the module substrate 4 is covered with a low elasticity elastic tree such as silicone resin, so that secondary reflow (reflow to the mounting substrate at the shipping destination) is performed. Reducing the expansion pressure due to solder remelting of the solder connection part 5 that occurs, prevents the interface between the chip part 3 and the sealing part ⁇ and the interface between the sealing part 7 and the module substrate 4 from peeling. It is possible to prevent outflow to the interface.
- low-elastic elastic resin prevents the elastic resin stress generated in the thermal cycle test of the high-frequency module 1 from breaking the gold wire 8.
- the elastic resin that forms the sealing part 7 is a low-elasticity that combines the protective strength (mechanical strength) that protects internal components and the flexibility to relieve the expansion pressure when the internal solder remelts.
- Insulating resin with silicone elasticity (silicone rubber) A and low elastic epoxy resins B, C, and D having the elastic modulus characteristics shown in Fig. 9 are preferred, and conventional high elasticity epoxy resin T is not compatible It is.
- the allowable range of the elastic modulus of the elastic resin of this embodiment is a high temperature, that is, a secondary reflow temperature (generally about 2300 ° C) and temperature cycle test (for example, 1-40 to + 1 2 5 ° C), taking into account the conditions at high temperature application, at a temperature of 1550 ° C or higher with a modulus of elasticity of 20 OMPa or lower It is preferable.
- a secondary reflow temperature generally about 2300 ° C
- temperature cycle test for example, 1-40 to + 1 2 5 ° C
- the elastic resin has an elastic modulus of 1 MPa or more at a temperature of 1550 ° C or higher. As shown in FIG. This is based on the result of a test to protect the surface-mounted components inside the sealing part 7 and, if it has an elastic modulus of at least IMP a, it can be protected. Is.
- a more preferable elastic modulus is 5 to 1 OMPa at a temperature of 1550 ° C or higher.
- the temperature at the time of actual use (room temperature: 25 ° C) is also required to have an elastic modulus of at least IMPa as described above.
- resins A, B, C , D is in range. .
- resins B, C and D are within the range, but resin A is out of the range.
- resin A also has an elastic modulus greater than I MP a, there is no problem.
- the solder flow rate for each tree is the number of defects when the electrical short test for chip part 3 is performed and the rate of occurrence when reflow is performed at 2600 ° C.
- the denominator represents the number of tests
- the numerator represents the number of defects.
- the non-conforming resin T has a very high defect occurrence rate of 70%.
- the elastic modulus is determined by comprehensively considering the reflow temperature margin and mechanical strength (protective power) of the high-frequency module 1. 2-4MPa is the best range ⁇
- the rubber hardness of the high-frequency module 1 is shore hardness A 70 when considering the reflow temperature margin and mechanical strength (protective power) of the high-frequency module 1 comprehensively.
- ⁇ 80 is the best range.
- area P indicates the optimum area in the splitting property of the elastic resin when the multi-piece substrate is divided into individual pieces in the assembly of the high-frequency module 1.
- region Q indicates the safe region of reflow resistance of elastic resin.
- the low-elasticity epoxy resins B, C, and D shown in Fig. 9 have different contents, such as silica, for example, and the characteristics are slightly different.
- wire height the loop height (hereinafter referred to as wire height) and length (hereinafter referred to as wire length) of the gold wire 8 in the high-frequency module 1 of the present embodiment
- wire length the length of the gold wire 8 in the high-frequency module 1 of the present embodiment
- the pad 2a of the semiconductor chip 2 and the corresponding terminal 4a of the module substrate 4 are connected by a gold wire 8, and a wire loop 8a is formed on each gold wire 8. Yes.
- the wire height (H) is the distance from the main surface 2 of the semiconductor chip 2 to the apex of the wire loop 8a (to the outline of the gold wire 8).
- the wire height (H) is the apex of the wire loop 8a from the bonding start point (Ist bonding point). Up to.
- the wire length (L) is the projected distance (wire horizontal distance) of the gold wire 8 from the bonding start point (1st bonding point) to the bonding end point (2nd bonding point) on the horizontal plane. This is the projection distance on the horizontal plane from the wire center at the start point to the wire center at the end point.
- Fig. 10 and Fig. 11 show the state of the gold wire 8 by the temperature cycle test (155 to 150 ° C), and Fig. 10 shows the crack 6 (see Fig. 12). Figure 11 shows the presence or absence of disconnection 9 (see Figure 14).
- crack level A in FIG. 10 is less than 50% crack 6 around the wire, and crack level B is more than 50% crack 6 around the wire.
- crack 6 begins to occur in 2500 cycles, and as the number of cycles increases, the rate of occurrence of crack 6 also increases. It seems that change is taking place.
- Figure 14 shows the wire condition when the temperature cycle (155 to 150 ° C) test was conducted with the wire height of 0.2 2 mm (2 20 im) and the wire length of 1.8 mm. Disconnection 9 has occurred.
- the high-frequency module 1 of the present embodiment is configured to prevent the wire 9 (bonding wire) 8 from being broken due to the stress of the elastic resin by setting a range for the wire height and wire length.
- Figure 13 shows the distribution of data with and without cracks after a temperature cycle test of 1 000 cycles. According to this, when the wire length is 1.5 mm or when the wire height is 0.2 mm (200 m), a relatively large number of wire cracks have occurred. In this case, it can be estimated that the rate of occurrence of wire cracking is further increased, and the potential to reach disconnection 9 as shown in Fig. 14 is also increased.
- the region where the wire height is 0.2 mm (200 jum) or less and the wire length is 1.5 mm or less is assumed to be the estimated safety region 1 2.
- the target area for production was 13 with a length of 0.1 mm to 0.2 mm and a chair length of 0.5 mm to 1.5 mm.
- An example of a specific product target is 0.16 mm (16 0) Aim for the wire height and 1.2 mm for the wire length.
- wire deformation due to resin flow during resin molding or contact between adjacent wires can be prevented.
- the amount of elastic resin flowing into the lower part of the wire is reduced, so the absolute amount of elastic resin expansion / contraction is reduced. As a result, the reliability of the product against thermal stress can be improved.
- solder used in the high-frequency module 1 of the present embodiment will be described.
- the module substrate 4 is formed of, for example, alumina ceramic or the like, and a plurality of external terminals 1 a are provided on the front surface 4 g and the opposite back surface 4 h as shown in FIG. .
- a chip part 3 such as a ceramic chip capacitor, a chip resistor, or a chip thermistor is mounted on the surface 4 g, and these mounting parts have connection terminals at both ends. 3 d is connected to the terminal 4 a of the module substrate 4 through the solder connection part 5.
- each terminal 4a is wire-bonded using the gold wire 8
- a gold-plated layer 4b is formed on the surface of each terminal 4a as shown in FIG.
- Each chip component 3 is also solder-connected to a terminal 4a having a gold-plated layer 4b formed on the surface.
- the connection terminal 3d of the chip component 3 is composed of, for example, an AgZP d electrode 3e, an Ni undercoat layer 3f, and a soldered layer 3g in order from the lower layer.
- the terminal 4a of the substrate 4 is composed of a C ii copper body 4c, a Ni plating layer 4d, and a gold plating layer 4b in order from the lower layer, and further, the solder connection part 5 of the terminal 4a is formed.
- the area other than the location is covered and insulated by the overcoat glass 4e which is an insulating film (solder resist film).
- the gold plating layer 4b is formed on the surface of all the terminals 4a, and the chip component 3 is soldered to the gold plating layer 4b at the connection terminal 3d.
- the pad 2a is connected to the gold wire 8
- the gold wire 8 is further connected to the metallized layer 4b of the terminal 4a.
- the solder connection part 5 to which the chip component 3 is connected is made of a solder containing no lead (P b), for example, solder containing tin (S n) or antimony (S b) as a main component.
- P b solder containing no lead
- S n solder containing tin
- S b antimony
- the solder mounting portion 11 has a solder containing no lead (Pb), for example, It is preferable to use a solder mainly composed of tin (Sn), silver (Ag), and copper (Cu), and thus, Pb-free mounting of the high-frequency module 1 can be realized.
- Pb-free solder consisting mainly of tin (Sn), antimony (Sb), etc. is used for the solder-mounted components in the high-frequency module 1, and soldering to the motherboard 10 of the high-frequency module 1
- Pb-free solder consisting mainly of tin (Sn), silver (Ag), copper (Cu), etc. for mounting
- both solders have a high melting point around 230-260 ° C. This prevents the internal Pb-free solder from melting during mounting.
- a module substrate 4 shown in FIG. 5 is prepared.
- the module substrate 4 is provided with a cavity portion 4 f which is a recess capable of accommodating the semiconductor chip 2 on the surface 4, and can be soldered to the connection terminal 3 d of the chip component 3 on the periphery thereof.
- a plurality of terminals 4a are provided.
- a plurality of external terminals 1a are provided on the back surface 4h.
- solder paste is printed on each terminal 4 a and solder reflow is performed to mount a plurality of surface mount components such as semiconductor chip 2 and chip component 3.
- Pb-free solder mainly composed of tin (Sn) and antimony (Sb).
- the wire 2 a of the semiconductor chip 2 and the terminal 4 a of the module substrate 4 are wire-bonded using the gold wire 8.
- the wire height is 0.2 mm (200 zm) or less, preferably 0.1 mm ( 1 0 O ju m.) Wire bonding is performed so that the distance is 0.2 mm or less.
- wire bonding is performed so that the wire length is 1.5 mm or less, preferably 0.5 mm or more and 1.5 mm or less.
- the wire height is 0.16 mm (1600) m and the wire length is 1.2 mm.
- a sealing portion 7 is formed using an insulating and low-elasticity elastic resin such as a silicone resin, and the semiconductor chip 2, the chip component 3, and the wire 8 are sealed by the sealing portion 7. To do.
- the high-frequency module 1 of the modification shown in FIG. 16 has a configuration in which the main surface 2 b of the semiconductor chip 2 is retracted from the surface 4 g of the module substrate 4. That is, when the height of the main surface 2b of the semiconductor chip 2 is lower than the surface 4g of the module substrate 4, and the cavity portion 4f is relatively deep, such a structure is obtained. can do.
- the high-frequency module 1 of the modification shown in FIG. 17 has a configuration in which the main surface 2 b of the semiconductor chip 2 and the surface 4 g of the module substrate 4 are substantially the same height.
- the high-frequency module 1 of the modification shown in FIG. 18 has a two-stage cavity portion 4 f, and the semiconductor chip 2 is formed on the inner peripheral wall portion of the cavity portion 4 f where the semiconductor chip 2 is disposed.
- a step 4 i is formed at a depth that is almost the same height as the main surface 2 b of the wire and a little deeper than the height of the wire loop 8 a, and the gold wire 8 is connected to the step 4 i. It has a two-stage cavity part 4 f provided with a terminal 4 a.
- wire bonding is performed with the semiconductor chip 2 side as the 1st bonding side in relation to the bonding interface, but conversely, wire bonding is performed with the terminal 4a side as the 1st bonding side. May be.
- the high-frequency module 1 shown in FIG. 19 has a cavity-less structure in which the cavity portion 4 f shown in FIG. 16 is not formed on the module board 4.
- the board structure can be simplified, the cost of the module board 4 can be reduced, and the cost of the high-frequency module 1 can be reduced.
- the wire bonding described in the present embodiment can be applied to the high-frequency module 1 of the modification shown in FIGS. 16 to 19 as well, and the solder connection using Pb-free solder can be applied.
- the same effects as the high-frequency module 1 of the present embodiment shown in FIGS. 1 to 7 can be obtained.
- the high-frequency module 1 of the modified example shown in FIG. 20 has a plurality of cavity portions 4 f that are recesses, each of which has a semiconductor chip 2 mounted thereon, and a semiconductor chip 2. Use wire bonding even in the meantime.
- the high-frequency module 1 of the modified example shown in FIG. 21 performs wire bonding between the semiconductor chip 2 and the chip component 3.
- modified high-frequency module 1 shown in FIG. 22 performs wire bonding between the chip components 3.
- the low-elasticity elastic resin is a silicone resin
- the elastic resin has an elastic modulus allowable range described in the above-described embodiment, It may be a gel.
- the semiconductor device is the high-frequency module 1
- the semiconductor device includes a mounting component to be solder-mounted, the mounting component is wire-bonded, and the mounting component is elastic.
- Other module products may be used as long as the resin is sealed with resin.
- the mounting component is not limited to a chip component or a semiconductor chip, and may be another electronic component as long as it is a mounting component to be solder-mounted.
- the semiconductor device of the present invention is suitable for a module product that is assembled by wire bonding and is resin-sealed with a low-elasticity resin, and in particular, a high frequency on which a semiconductor chip or a chip component is mounted.
- modules fc o Suitable for modules fc o
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2004541173A JPWO2004032223A1 (ja) | 2002-09-30 | 2002-09-30 | 半導体装置 |
US10/524,238 US20050248039A1 (en) | 2002-09-30 | 2002-09-30 | Semiconductor device |
PCT/JP2002/010177 WO2004032223A1 (ja) | 2002-09-30 | 2002-09-30 | 半導体装置 |
CNA028294351A CN1650413A (zh) | 2002-09-30 | 2002-09-30 | 半导体器件 |
TW091134508A TWI280650B (en) | 2002-09-30 | 2002-11-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2002/010177 WO2004032223A1 (ja) | 2002-09-30 | 2002-09-30 | 半導体装置 |
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WO2004032223A1 true WO2004032223A1 (ja) | 2004-04-15 |
Family
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PCT/JP2002/010177 WO2004032223A1 (ja) | 2002-09-30 | 2002-09-30 | 半導体装置 |
Country Status (5)
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US (1) | US20050248039A1 (ja) |
JP (1) | JPWO2004032223A1 (ja) |
CN (1) | CN1650413A (ja) |
TW (1) | TWI280650B (ja) |
WO (1) | WO2004032223A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100409436C (zh) * | 2005-12-01 | 2008-08-06 | 上海华虹Nec电子有限公司 | 一种实现逻辑集成电路顶上的压焊块的应用方法 |
JP2016201456A (ja) * | 2015-04-09 | 2016-12-01 | 豊田合成株式会社 | 発光装置 |
JP7396118B2 (ja) | 2020-02-28 | 2023-12-12 | 富士電機株式会社 | 半導体モジュール |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7560821B2 (en) * | 2005-03-24 | 2009-07-14 | Sumitomo Bakelite Company, Ltd | Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same |
CN102222262B (zh) * | 2011-02-19 | 2016-08-24 | 上海祯显电子科技有限公司 | 一种非接触智能卡 |
CN104363700B (zh) * | 2014-11-13 | 2018-02-13 | 深圳市华星光电技术有限公司 | 印刷电路板 |
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JPS62291128A (ja) * | 1986-06-11 | 1987-12-17 | Nec Corp | 混成集積回路装置 |
JPH03227543A (ja) * | 1990-02-01 | 1991-10-08 | Mitsubishi Electric Corp | ワイヤボンデイング方法 |
JPH06349969A (ja) * | 1993-06-04 | 1994-12-22 | Matsushita Electric Works Ltd | 印刷基板および半導体実装基板 |
JP2000021920A (ja) * | 1998-07-02 | 2000-01-21 | Sony Corp | 半導体装置 |
JP2001237252A (ja) * | 2000-02-22 | 2001-08-31 | Hitachi Ltd | 半導体装置とそれを用いた電子装置 |
JP2001313459A (ja) * | 2000-04-28 | 2001-11-09 | Tdk Corp | 電子部品装置、電子回路モジュール、電子回路装置及びその製造方法 |
JP2002208668A (ja) * | 2001-01-10 | 2002-07-26 | Hitachi Ltd | 半導体装置およびその製造方法 |
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JPH0964240A (ja) * | 1995-08-25 | 1997-03-07 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2002240192A (ja) * | 2001-02-15 | 2002-08-28 | Minebea Co Ltd | 片面紙フェノール樹脂銅張積層板 |
-
2002
- 2002-09-30 JP JP2004541173A patent/JPWO2004032223A1/ja not_active Withdrawn
- 2002-09-30 WO PCT/JP2002/010177 patent/WO2004032223A1/ja active Application Filing
- 2002-09-30 CN CNA028294351A patent/CN1650413A/zh active Pending
- 2002-09-30 US US10/524,238 patent/US20050248039A1/en not_active Abandoned
- 2002-11-27 TW TW091134508A patent/TWI280650B/zh not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS62291128A (ja) * | 1986-06-11 | 1987-12-17 | Nec Corp | 混成集積回路装置 |
JPH03227543A (ja) * | 1990-02-01 | 1991-10-08 | Mitsubishi Electric Corp | ワイヤボンデイング方法 |
JPH06349969A (ja) * | 1993-06-04 | 1994-12-22 | Matsushita Electric Works Ltd | 印刷基板および半導体実装基板 |
JP2000021920A (ja) * | 1998-07-02 | 2000-01-21 | Sony Corp | 半導体装置 |
JP2001237252A (ja) * | 2000-02-22 | 2001-08-31 | Hitachi Ltd | 半導体装置とそれを用いた電子装置 |
JP2001313459A (ja) * | 2000-04-28 | 2001-11-09 | Tdk Corp | 電子部品装置、電子回路モジュール、電子回路装置及びその製造方法 |
JP2002208668A (ja) * | 2001-01-10 | 2002-07-26 | Hitachi Ltd | 半導体装置およびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100409436C (zh) * | 2005-12-01 | 2008-08-06 | 上海华虹Nec电子有限公司 | 一种实现逻辑集成电路顶上的压焊块的应用方法 |
JP2016201456A (ja) * | 2015-04-09 | 2016-12-01 | 豊田合成株式会社 | 発光装置 |
JP7396118B2 (ja) | 2020-02-28 | 2023-12-12 | 富士電機株式会社 | 半導体モジュール |
Also Published As
Publication number | Publication date |
---|---|
TWI280650B (en) | 2007-05-01 |
JPWO2004032223A1 (ja) | 2006-02-02 |
CN1650413A (zh) | 2005-08-03 |
TW200409321A (en) | 2004-06-01 |
US20050248039A1 (en) | 2005-11-10 |
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