WO2004029735A1 - 電子時計、電子機器および起動方法 - Google Patents
電子時計、電子機器および起動方法 Download PDFInfo
- Publication number
- WO2004029735A1 WO2004029735A1 PCT/JP2003/012145 JP0312145W WO2004029735A1 WO 2004029735 A1 WO2004029735 A1 WO 2004029735A1 JP 0312145 W JP0312145 W JP 0312145W WO 2004029735 A1 WO2004029735 A1 WO 2004029735A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- power supply
- voltage
- boosting
- supply voltage
- oscillation
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 27
- 230000010355 oscillation Effects 0.000 claims abstract description 154
- 238000007493 shaping process Methods 0.000 claims abstract description 34
- 238000001514 detection method Methods 0.000 claims description 31
- 230000005669 field effect Effects 0.000 claims description 22
- 238000005259 measurement Methods 0.000 claims 1
- 238000010248 power generation Methods 0.000 abstract description 88
- 238000010276 construction Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 53
- 238000010586 diagram Methods 0.000 description 24
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 22
- 230000008878 coupling Effects 0.000 description 17
- 238000010168 coupling process Methods 0.000 description 17
- 238000005859 coupling reaction Methods 0.000 description 17
- 230000002194 synthesizing effect Effects 0.000 description 16
- 239000013078 crystal Substances 0.000 description 13
- 230000006870 function Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000003786 synthesis reaction Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000000087 stabilizing effect Effects 0.000 description 7
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003086 colorant Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 210000004247 hand Anatomy 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 241000282693 Cercopithecidae Species 0.000 description 1
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 210000000707 wrist Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
-
- G—PHYSICS
- G04—HOROLOGY
- G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
- G04C10/00—Arrangements of electric power supplies in time pieces
- G04C10/02—Arrangements of electric power supplies in time pieces the power supply being a radioactive or photovoltaic source
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
- G04F5/04—Apparatus for producing preselected time intervals for use as timing standards using oscillators with electromechanical resonators producing electric oscillations or timing pulses
- G04F5/06—Apparatus for producing preselected time intervals for use as timing standards using oscillators with electromechanical resonators producing electric oscillations or timing pulses using piezoelectric resonators
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G19/00—Electric power supply circuits specially adapted for use in electronic time-pieces
- G04G19/02—Conversion or regulation of current or voltage
- G04G19/04—Capacitive voltage division or multiplication
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/06—Modifications of generator to ensure starting of oscillations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to an electronic timepiece or an electronic device that measures or operates by applying a predetermined operating voltage, and a method for starting the same, and in particular, an electronic timepiece having a power generation function of converting external energy into electrical energy,
- the present invention relates to electronic devices and a method for starting them.
- Electronic watches incorporating such power generation means include mechanical power generation watches that convert the mechanical energy of the rotating weight into electrical energy and use it, and serialize multiple thermocouples and measure the temperature at both ends of the thermocouple.
- FIG. 23 is a block diagram of the electronic timepiece 230.
- This conventional electronic watch 2 In 300 a current path is formed by the power generation unit 2301, the charging diode 2306, and the timekeeping unit 2304.
- the clock section 2304 is a clock block that displays time using electric energy. Further, the output of the power generation unit 2301 is boosted through the boosting unit 2302, and the power storage unit 2303 can be charged.
- the generated energy is first sent to the clock unit 2304 and the boost control unit 2305.
- the timekeeping unit 2304 starts the restart operation.
- the clock section 2304 outputs a divided clock signal SX, and the frequency-divided signal (S y in the figure) is further divided by the boost control section 2305 to the boost section 230. Sent to 2.
- the boosting unit 2302 starts the boosting operation.
- the timing section 2304 starts operating, even if the power generation voltage of the power generation section 2301 slightly decreases, the power generation output is boosted by the boosting section 2302 and Three
- 0 3 can be charged to a high voltage.
- the open-circuit voltage of one stage of a solar cell used as a power generation unit is about 0.7 [V] even under high illuminance.
- the crystal oscillation circuit normally used in the conventional electronic timepiece 230 shown in FIG. 23 requires at least about 0.6 [V] to 0.8 [V] to start oscillation. It is.
- women's electronic watches are smaller than men's electronic watches and have to use solar cells with a small effective light receiving area. There was a problem that it was not possible.
- a solar cell with a single-stage cell configuration and a ring shape is also used, and an electronic timepiece with this attached to the periphery of the dial is also in practical use.
- the solar cell cannot have a large light receiving area due to the structure of the timepiece, it is necessary to receive not only direct light but also light reflected from the dial. Therefore, the dial can only use a white dial that reflects light, and there is a problem in that it is subject to design restrictions.
- the present invention has been made in view of the above-mentioned problems, and aims to reliably start an electronic timepiece or an electronic device with a voltage lower than a voltage required for starting, thereby reducing the size of the electronic timepiece or the electronic device. It is an object of the present invention to provide an electronic timepiece, an electronic device, and a starting method that can be implemented. It is still another object of the present invention to provide an electronic timepiece, an electronic device, and a start-up method capable of improving the decorativeness including the color of the electronic timepiece or the electronic device. Disclosure of the invention
- an electronic timepiece includes a power supply voltage generating unit configured to convert external energy into electric energy to generate a power supply voltage lower than a predetermined operation voltage.
- An oscillation signal output unit that outputs a predetermined oscillation signal by applying a power supply voltage generated by the power supply voltage generation unit; and a power supply voltage generated by the power supply voltage generation unit, at least the predetermined operation voltage.
- the power supply voltage can be increased to the operation voltage by applying the power supply voltage that is lower than the operation voltage.
- a boost control unit that controls the boost unit and boosts the power supply voltage only for a predetermined time based on the predetermined oscillation signal may be provided.
- the boosting operation can be reliably performed for the predetermined time, and the operating voltage can be obtained after the predetermined time has elapsed.
- a frequency dividing means for dividing the oscillation signal output by the oscillation signal output means; and an oscillation signal output means for outputting the oscillation signal based on the frequency division signal output from the frequency dividing means.
- a boost stop instruction signal output means for outputting a boost stop instruction signal for instructing a stop of the boost operation by the boost means when the predetermined time has elapsed from the above, and the boost control means comprises: The boosting may be stopped based on the boosting stop instruction signal output by the means.
- the boosting operation can be controlled after a predetermined time has elapsed by using the frequency-divided signal of the frequency dividing means generally built in the electronic timepiece, and the number of components can be reduced. .
- the boosting control means outputs a boosting stop instruction signal for instructing the boosting means to stop the boosting operation when the predetermined time has elapsed after the oscillation signal output means has started.
- the boosting may be stopped based on a boosting stop instruction signal output by the boosting stop instruction signal output means.
- the predetermined time can be reduced by providing the boost stop instruction signal output means for controlling the boost operation when the predetermined time has elapsed, in addition to the frequency dividing means generally incorporated in the electronic timepiece.
- the time interval of the predetermined time can be changed only by replacing the boosting stop instruction signal output means.
- the boost control means may be configured to input the predetermined time in advance by using time information input means for inputting time information representing any one of a plurality of times having different time intervals, and by the time information input means.
- Time information storage hand that stores the time information
- a time information extracting means for extracting the time information stored by the time information storing means by applying the power supply voltage generated from the power supply voltage generating means; and
- a boost stop instruction signal generating means for generating a boost stop instruction signal for instructing a stop of the boost operation by the boost means when a time represented by the extracted time information elapses based on the extracted time information;
- the boosting may be stopped based on the boosting stop instruction signal generated by the boosting stop instruction signal generating means.
- the predetermined time can be appropriately changed according to the performance of the electronic timepiece by the operation of the operator, and the boosting operation and startup suitable for the performance of the electronic timepiece can be performed.
- a power supply voltage detecting means for detecting whether or not the power supply voltage has been boosted to the predetermined operating voltage by the boosting means; and controlling the boosting means to provide the predetermined oscillation signal and the power supply voltage detecting means.
- step-up control means for stepping up the power supply voltage based on the detection result detected by the step (b).
- the oscillation signal can be output and the starting voltage can be increased to the operating voltage. Then, the electronic clock can be started by the oscillation signal and the operating voltage.
- the boost control means may include, based on the oscillation signal and a detection result detected by the power supply voltage detection means, The boosting operation of the boosting means may be controlled.
- the oscillation signal can be output and the power supply voltage can be boosted to the operating voltage.
- the electronic timepiece can be started even after a predetermined time has elapsed.
- An oscillation circuit that resonates with a signal output from the oscillation circuit; a constant current circuit that supplies a constant current; and a constant current that is supplied from the constant current circuit.
- an oscillation inverter that inverts and amplifies the output signal and outputs the oscillation signal.
- overtone oscillation can be suppressed by using a constant current circuit.
- the timing unit includes a logic circuit including a plurality of field-effect transistors, and the oscillation inverter has a lower threshold voltage and a lower value voltage than the field-effect transistor included in the timing unit. It may be constituted by a field effect transistor. '
- the timekeeping means includes a logic circuit including a plurality of field effect transistors, and has a lower threshold direct voltage than the field effect transistors included in the timekeeping means. And a waveform shaping means for shaping the waveform of the oscillation signal output from the oscillation signal output means and outputting the shaped signal to the timekeeping means.
- the time-measuring means includes a logic circuit composed of a plurality of field-effect transistors, and the boosting control means includes an electric field having a lower threshold voltage than a field-effect transistor included in the time-measuring means. It may be constituted by an effect transistor.
- a bias circuit configured by a field-effect transistor having the same threshold value as the oscillation circuit and applying a predetermined bias voltage to the oscillation inverter can be provided.
- the waveform shaping section outputs a waveform of the oscillation signal output from the oscillation signal output section and outputs the waveform signal to the timing section, and a field effect transistor having the same threshold value and value as the waveform shaping section.
- a bias circuit for applying a predetermined bias voltage to the waveform shaping means.
- the electronic device of the present invention is an electronic device that operates by applying a predetermined operating voltage based on a predetermined oscillation signal, and converts external energy into electric energy, and Power supply voltage generation means for generating a power supply voltage lower than an operating voltage; oscillation signal output means for outputting the predetermined oscillation signal by the power supply voltage generated by the power supply voltage generation means; and power supply voltage generation means And a booster for boosting the power supply voltage generated at least to the predetermined operating voltage.
- the power supply voltage can be increased to the operation voltage by applying the power supply voltage lower than the operation voltage.
- a starting method is a starting method for starting an electronic device that operates by applying a predetermined operating voltage based on a predetermined oscillation signal, wherein the external energy is converted into electric energy, A power supply voltage generating step of generating a power supply voltage lower than the predetermined operation voltage; an oscillation signal output step of outputting the predetermined oscillation signal by the power supply voltage generated by the power supply voltage generating step; A boosting step of boosting the power supply voltage generated in the power supply voltage generating step to at least the predetermined operating voltage.
- the power supply voltage can be increased to the operation voltage by applying the power supply voltage lower than the operation voltage.
- FIG. 1 is a block diagram showing an overall configuration of an electronic timepiece according to an embodiment of the present invention
- FIG. 2 is a block diagram showing a specific configuration of a booster according to the embodiment of the present invention
- 3 to 5 are circuit diagrams of a booster circuit showing a boosting operation of the booster according to the embodiment of the present invention.
- FIG. 6 is a circuit diagram of the electronic timepiece according to the embodiment of the present invention.
- FIG. 7 is a circuit diagram illustrating a configuration of a clock block.
- FIG. 7 is a circuit diagram illustrating configurations of a waveform generation unit and a control signal generation unit of the electronic clock according to the embodiment of the present invention.
- FIG. 9 is a time chart showing an operation of the pulse synthesizing circuit according to the embodiment of the present invention.
- FIGS. 10 to 13 are diagrams showing the operation of the embodiment of the present invention.
- FIG. 14 is a flowchart showing a start processing procedure of the electronic timepiece.
- FIG. 14 is a timing chart showing a voltage waveform of a main part of a circuit of the electronic timepiece according to the embodiment of the present invention.
- FIG. 16 is a block diagram showing another example of the waveform generating unit according to the embodiment of the present invention.
- FIG. 16 is a flowchart showing a starting process procedure of the electronic timepiece when the waveform generating unit shown in FIG. 15 is used.
- FIG. 17 is a timing chart showing a voltage waveform of a main portion of a circuit of the electronic timepiece when the waveform generation unit of FIG. 15 is used.
- FIG. 18 is a timing chart showing an embodiment of the present invention.
- FIG. 19 is a block diagram showing another configuration example, FIG. 19 is a time chart showing a timer function provided in the control signal generation unit shown in FIG. 18, and FIG.
- FIG. 21 is a block diagram showing a hardware configuration of a boost stop instruction signal output unit for changing a predetermined time according to the embodiment;
- FIG. 21 is a block diagram showing a function of the boost stop instruction signal output unit shown in FIG. 20;
- FIG. 22 is a flowchart showing a boost stop instruction signal output processing procedure of the boost stop instruction signal output section.
- FIG. 23 is an overall view of a conventional electronic timepiece.
- FIG. 3 is a block diagram showing a configuration. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram showing an overall configuration of an electronic timepiece according to an embodiment of the present invention.
- the electronic timepiece 100 includes a power generation unit 101, a power storage unit 102, a boosting unit 103, a clock block 104, a boosting control unit 105, and a power generation detecting unit 106. It is composed of
- the power generation unit 101 converts external energy into electric energy to generate a power supply voltage lower than a predetermined operating voltage for operating the electronic timepiece 100.
- the power generation unit 101 For example, a solar cell module consisting of one-stage solar cells.
- the positive electrode of the power generator 101 is grounded, and the negative electrode is connected to the boost input terminal of the booster 103.
- an open circuit voltage of about 0.4 [V] to 0.7 [V] is generated. This open voltage becomes the power supply voltage.
- Power storage unit 102 stores the power output from power generation unit 101, and operates clock block 104 with the stored power while power generation unit 101 is not generating power.
- Power storage unit 102 has a positive electrode grounded. Further, negative electrode terminal V ss 2 of power storage unit 102 is connected to switching control unit 108.
- the power storage unit 102 can employ, for example, a lithium ion secondary battery.
- the booster 103 boosts the power supply voltage generated by the power generator 101 to at least a predetermined operating voltage.
- the booster 103 is a booster circuit that performs a boosting operation by switching the series / parallel state of the capacitor.
- the output of the power generator 101 is connected to the input side of the booster 103.
- the booster 103 is configured to receive a boost clock Sa as a boost start signal for starting the boost operation.
- the booster 103 receives the boost clock S By a, the internal capacitor is switched to perform quadruple boost operation.
- the boost output terminal name of the booster 103 is V up. The specific configuration of the booster 103 will be described later.
- the clock block 104 is a part that generates a basic signal for the timekeeping operation and the charging / discharging operation of the electronic clock 100.
- the clock block 104 includes an oscillation circuit 601, a waveform shaping circuit 603, and a timer 605.
- a capacitor 110 is connected in parallel to the clock block 104 in order to stabilize the voltage between the terminals of the clock block 104 against intermittent load operation.
- the capacitor 110 has a positive electrode grounded, and a negative terminal V ss 1 is connected to the power generator 101, the booster 103, and the switching controller 108.
- Vss1 the voltage value of the negative electrode terminal Vss1 is also referred to as Vss1.
- the capacitor 110 has a capacity of 10 [ju F] as an example.
- the internal configuration of the clock block 104 and details of each signal output from the clock block 104 will be described later.
- the boost control unit 105 is a circuit that controls the operation of the boost unit 103, and includes a control signal generation unit 107 and a switching control unit 108.
- the control signal generation unit 107 receives various signals (Sb, Sc, Sd, Se) output from the clock block 104 and a signal S i output from the power generation detection unit 106 to perform various control. Generate and output signals (S a, S f, S g, S h).
- the first charging switch signal Sf, the second charging switch signal Sg, and the third charging switch signal Sh are output to the switching control unit 108. Further, the boost clock Sa is output to the booster 103.
- the internal configuration of the control signal generation unit 107 and details of various control signals (S a, S f, S g, and S h) will be described later.
- the switching control unit 108 includes a first charging switch 111, a second charging switch 112, and a third charging switch 113.
- the first to third charging switches 111 to 113 are constituted by, for example, N-channel MOSFETs, and are synchronized with the operation of the boosting unit 103 to the clock block 104 and the power storage unit] .02. And controls the boosted output from the booster 103.
- the source terminal of the first charging switch 111 is connected to the negative terminal Vss1 of the capacitor 110. Further, the drain terminal is connected to the boosted output terminal Vup of the booster 103. Further, the gate terminal is connected to the output terminal of the control signal generation unit 107, and when the first charging switch signal S f is input, the boosting unit 103 and the clock block 104 are made conductive. .
- the source terminal of second charging switch 112 is connected to negative terminal V ss 2 of power storage unit 102. Further, the drain terminal is connected to the boosted output terminal Vup of the booster 103. The gate terminal is an output terminal of the control signal generation unit 107.
- the second charging switch signal Sg is input, the boosting unit 103 and the power storage unit 102 are made conductive.
- the source terminal of the third charging switch 113 is connected to the negative terminal Vss1 of the capacitor 110.
- the drain terminal is connected to the boost output terminal V up of the booster 103.
- the gate terminal is connected to the output terminal of the control signal generation unit 107, and the third charge switch signal Sh is input so that the booster unit 103 and the clock block 1 are connected. Conduction with 04.
- the first diode 121 sends the power of the power generation unit 101 to the clock block 104 when the clock block 104 restarts after stopping its operation.
- the anode terminal of the first diode 1 2 1 is connected to the negative terminal V ss 1 of the capacitor 1 10, and the power source terminal of the first diode 1 2 1 is connected to the negative terminal of the power generation unit 101 Have been.
- second diode 122 sends the power stored in power storage unit 102 to clock block 104 even while power generation unit 101 is not generating power.
- the anode terminal of the second diode 122 is connected to the negative terminal V ss 1 of the capacitor 110, and the cathode terminal of the second diode 122 is connected to the negative terminal of the power storage unit 102. That is, it is connected to Vss2.
- a Schottky barrier diode having a forward voltage drop of about 0.1 [V] can be used.
- the power generation detection unit 106 is a circuit block including an amplifier circuit for detecting the power generation state of the power generation unit 101.
- the power generation detection unit 106 outputs a power generation detection signal Si to the control signal generation unit 107.
- the power generation detection unit 106 operates to output the power generation detection signal S i as a high level when a predetermined power generation amount is output from the power generation unit 101, and to output a low level otherwise. I do.
- FIG. 2 is a block diagram showing a specific configuration of the booster 103.
- the booster 103 is configured by a booster circuit 201 to which the power supply voltage generated from the power generator 101 is applied and a series / parallel switching circuit 202.
- the booster circuit 201 is composed of a switch circuit 310 to 304 using a MOS field-effect transistor (hereinafter, FET), a capacitor 311 and a capacitor 311. It is constituted by.
- the switch circuit 301 to 304 of the MOS FET has a small amplitude output from the boost control section 105 by a low threshold value used for a part of the logic circuit of the boost control section 105 described later. 0.3 [V] or more), it is possible to use one configured so that the switching control can be fully performed.
- the switch circuit 305 is constituted by any one of the first charging switch 111 to the third charging switch 113 shown in FIG. 1, and the capacitor 313 is a power storage unit. It is composed of either 102 or capacitor 110.
- the series-parallel switching circuit 202 is started by the application of the power supply voltage from the power generation unit 101, and receives the boosted clock Sa output from the control signal generation unit 107. Thus, the switching signal is input to the MOS FET switch circuits 301 to 304.
- booster capacitor 311 is connected in parallel to power generator 101, and booster capacitor 311 is charged. I do. If no load is connected to the storage capacitor 3 13, the boost capacitor 3 11 1 is charged to the open voltage of the power generation unit 101.
- the boost capacitor 3 1 2 is charged.
- the boost capacitor 312 is charged up to twice the open voltage of the power generation unit 101.
- a voltage in which a boosting capacitor 311 and a boosting capacitor 312 are connected in series to the power generation unit 101 is applied to the storage capacitor 313 to store the voltage.
- the boost capacitor 3 13 is charged to a voltage four times the open voltage of the power generation unit 101. That is, the open-circuit voltage of the generated voltage is 0.
- FIG. 6 is a circuit diagram showing a configuration of a clock block in the electronic timepiece according to the embodiment of the present invention.
- the clock block 104 includes an oscillating unit 601, a waveform shaping unit 603, a bias circuit 604, and a clock unit 605.
- the clock section 605 is composed of a waveform generation section 651, a time display body 652, and a constant voltage circuit 653.
- the oscillating unit 600 1 outputs an oscillation output signal S 1 by applying the power supply voltage generated by the power generating unit 101.
- the oscillating unit 6101 includes a resonance circuit 6100.
- the resonance circuit 610 includes a crystal resonator 611, a first oscillation capacitor 612, and a second oscillation capacitor 613. The resonance circuit 610 determines the oscillation frequency of the oscillation section 601.
- the crystal oscillator 6 11 is a crystal oscillator used for a general electronic timepiece.
- the first oscillation capacitor 612 and the second oscillation capacitor 613 are capacitors built in the integrated circuit.
- the first oscillation capacitance 612 is 8 [pF]
- the second oscillation capacitance 613 is 4 [pF].
- the positive electrodes of the first oscillation capacitor 612 and the second oscillation capacitor 613 are grounded, respectively, and the negative electrodes are connected to both ends of the crystal resonator 611, respectively.
- the negative electrode of the first oscillation capacitor 612 is the output terminal of the resonance circuit 61, and receives the oscillation input signal Sp for the crystal oscillator 611 to oscillate.
- the negative electrode of the second oscillation capacitor 613 is an input terminal of the resonance circuit 610, and outputs an oscillation output signal S1 output from the crystal resonator 611.
- the resonance frequency of this resonance circuit 610 is, for example, 3 2 [KH z] (specifically, 3 2 7 6 8 [H z]).
- the oscillating unit 60 1 further includes a first transistor element 62 1 and a second transistor element 62 2, a first coupling capacitor 62 3, a second coupling capacitor 62 4, It has a first bias resistor 6 25, a second bias resistor 6 26, a third transistor element 6 27, a third bias resistor 6 28, and a stabilizing capacitor 6 29
- the first transistor element 621 and the second transistor element 622 constitute an oscillation inverter 620 serving as an inverter (inverting amplification) circuit.
- a resonance circuit 610 is connected between the input and output of the oscillation inverter 620 to form a feedback circuit.
- first bias resistor 625, the second bias resistor 626, and the third bias resistor 628 are constituted by circuit elements having high resistance values.
- the first bias resistor 625, the second bias resistor 626, and the third bias resistor 628 may have an electric resistance value of 500 [ ⁇ ].
- the first coupling capacitor 623, the second coupling capacitor 624, and the stabilizing capacitor 629 can be constituted by capacitors.
- the first transistor element 62 1 is constituted by, for example, a P-channel MOS FET.
- the second transistor element 62 2 and the third transistor element 62 7 are formed of, for example, an N-channel MOS FET.
- the first transistor element 62 1, the second transistor element 62 2, and the third transistor element 62 7 have low absolute values of threshold voltage (for example, 0.3 [V]). Is used. Specifically, the threshold voltage of the second transistor element 622 and the third transistor element 627, which are N-channel MOS SFETs, is 0.3 [V], and the threshold voltage of the P-channel MO SFETs is 0.3 [V]. The threshold value of a certain first transistor element 6 21 is 0.3 [V].
- the gate terminal of the first transistor element 6 2 1 and the second transistor element 6 The gate terminal 22 is connected via a first coupling capacitance 6 23 and a second coupling capacitance 6 24.
- the connection point between the first coupling capacitance 6 2 3 and the second coupling capacitance 6 2 4 is connected to the resonance circuit 6 10 so that the oscillation input signal Sp is input to the resonance circuit 6 10. I'm familiar.
- the drain terminal of the first transistor element 62 1 and the drain terminal of the second transistor element 62 2 are connected to each other.
- the two drain terminals are connected to the resonance circuit 610, so that the oscillation output signal S1 output from the resonance circuit 610 is input.
- the source terminal of the first transistor element 621 is grounded.
- the source terminal of the second transistor element 622 is connected to the negative electrode of the stabilizing capacitor 629.
- the positive electrode of the stabilizing capacitor 629 is grounded.
- the stabilizing capacitor 629 is provided for the purpose of temporarily supplying a current required for the operation of the oscillation inverter 620.
- drain terminal of the third transistor element 627 is connected to the negative electrode of the stabilizing capacitor 629.
- the source terminal of the third transistor element 627 is connected to the constant voltage output terminal Vreg of the constant voltage circuit 653.
- a constant voltage obtained from the bias circuit 604 is applied to the gut terminal of the third transistor element 627 via the third bias resistor 628, and the third transistor element 627 Operate as a constant current circuit.
- This constant current circuit supplies current to the stable capacitance 629.
- the first bias voltage VP output from the bias circuit 604 is DC-biased to the gate terminal of the first transistor element 621 via the first bias resistor 625.
- a second bias voltage VN is DC-biased to the gate terminal of the third transistor element 627 via a third bias resistor 628.
- the first bias voltage VP and the second bias voltage VN are generated by a bias circuit 604.
- the configuration of the bias circuit 604 will be described later. Due to the first bias voltage VP, a constant current of 15 [nA] flows in the first transistor element 62 1 in terms of direct current. Also, it is assumed that the dimensions of the third transistor element 627 are set so as to operate as a constant current circuit of 20 [nA].
- the second bias resistor 626 is inserted between the oscillation output signal S1 and the gate of the second transistor element 622 in order to cause self-feedback to the second transistor element 622. .
- the waveform shaping section 603 includes, for example, a fourth transistor element 631, which is a P-channel MOSFET, a fifth transistor element 632, which is an N-channel MOSFET, and a third coupling capacitor 633. , A fourth coupling capacitance 634, a fourth bias resistor 635, and a fifth bias resistor 636.
- the fourth transistor element 631 and the fifth transistor element 632 constitute an inverter (inverting amplification) circuit.
- the absolute value of the threshold voltage of the fourth transistor element 631 and the fifth transistor element 632 is set to 0.3 [V] which is the same as that of the MOS FET used for the oscillation section 61. The device used is used.
- the source terminal of the fourth transistor element 631 is grounded, and the source terminal of the fifth transistor element 632 is connected to the constant voltage output terminal V reg. Further, the gate terminal of the fourth transistor element 631 and the gate terminal of the fifth transistor element 632 are connected via the third coupling capacitance 633 and the fourth coupling capacitance 634. It is connected.
- a connection point between the third coupling capacitance 633 and the fourth coupling capacitance 634 is used as an input terminal of the waveform shaping section 63, and receives the oscillation output signal S1.
- the drain terminal of the fourth transistor element 631, and the drain terminal of the fifth transistor element 632 are connected, and output the waveform shaping output signal Sb.
- the fourth bias resistor 635 is connected to the gate terminal of the fourth transistor element 631, and receives the first bias voltage VP output from the bias circuit 604. It is.
- the fifth bias resistor 636 is connected to the gate terminal of the fifth transistor element 632, and receives the second bias voltage VN output from the bias circuit 604.
- the bias circuit 604 includes a sixth transistor element 641 and a seventh transistor element 642 which are P-channel MOS FETs, an eighth transistor element 643 and a ninth transistor element 644 which are N-channel MOS FETs, And a reference resistance 645 which is a resistance element.
- the sixth to ninth transistor elements 641 to 644 the elements whose absolute value of the threshold voltage is set to 0.3 [V] as in the MOSFET used for the oscillation section 601 are used.
- the bias circuit 604 is a circuit that outputs a constant voltage.
- the first bias voltage VP has an output voltage value of about ⁇ 0.3 [V], as viewed from the ground terminal, and the second bias voltage VN Operates such that the output voltage value is about +0.3 [V], as viewed from the voltage value of the constant voltage output terminal V reg.
- These output voltage values are based on the threshold voltages of the MOS FETs 641 to 644 that constitute the bias circuit 604.
- the source terminal of the sixth transistor element 641 is grounded, and the seventh transistor The source terminal of element 642 is grounded via reference resistor 645. Further, the reference resistor 645 can adjust the voltage values of the first bias voltage VP and the second bias voltage VN.
- a resistance element of 2500 [ ⁇ ] is used as the reference resistance 645.
- the gate terminal of the seventh transistor element 642 is connected to the gate terminal and the drain terminal of the sixth transistor element 641. This terminal outputs the first bias voltage VP.
- the source terminal of the eighth transistor element 643 and the source terminal of the ninth transistor element 644 are connected to the constant voltage output terminal Vreg.
- the gate terminal of the ninth transistor element 644 is connected to the eighth transistor element 643 Are connected to the gate terminal and the drain terminal. From this terminal, the second bias voltage VN is output. Further, the drain terminal of the sixth transistor element 644 is connected to the drain terminal of the ninth transistor element 644. In addition, the drain terminal of the seventh transistor element 643 is connected to the drain terminal of the eighth transistor element 643.
- the first bias voltage VP is applied to the gate terminal of the first transistor element 621 via the first bias resistor 625. Similarly, the first bias voltage VP is applied to the gate terminal of the fourth transistor element 631 via the fourth bias resistor 635.
- the second bias voltage VN is applied to the gate terminal of the third transistor element 627 via the third bias resistor 628.
- the second bias voltage VN is applied to the gate terminal of the fifth transistor element 632 via the fifth bias resistor 636.
- each transistor element in the oscillation section 601 has a low threshold. Even with a value transistor, the oscillating section 601 can start oscillating at a lower voltage. As a result, power consumption can be reduced.
- the clock section 605 includes a waveform generation section 651, a time display body 652, a constant voltage circuit 653, and a pnore down switch 654.
- the waveform generation unit 651 divides the waveform of the oscillation output signal S1 which is the output of the oscillation unit 601 by shaping the waveform of the oscillation output signal S1 with a multistage flip-flop circuit, and generates a plurality of frequency division stages. This is a logic circuit that generates a pulse waveform for driving the step motor by synthesizing the frequency-divided signal obtained from.
- the waveform generator 651 outputs a high-level backup signal Sj for 1.5 seconds after the power is turned on.
- the waveform generation unit 651 It outputs a top source signal Sc, a boost signal Sd, and a charging clock Se. The configuration of these various signals and the waveform generator 651 will be described later.
- the time display body 652 is composed of, for example, elements constituting an analog timepiece, for example, a time display element such as a stepping motor (not shown), a reduction gear train, a dial, and hands.
- the time display 652 drives the stepping motor based on the pulse waveform generated by the waveform generator 651, and displays the time by rotating the hands through the deceleration wheel train. Since the time display body 652 has a general configuration, a detailed description of the configuration is omitted.
- the constant voltage circuit 653 is a general constant voltage circuit (voltage regulator) that outputs a constant voltage.
- the output terminal of the constant voltage circuit 653 is set to V reg.
- the constant voltage circuit 653 is driven by the voltage between the ground and the terminal Vss1, which is the operating voltage of the watch block 104, and the voltage between the ground and the terminal Vreg becomes 0.8 [V].
- Vss1 is a negative terminal of the clock block 104.
- a drain terminal of the pull-down switch 654 is connected to the constant voltage output terminal Vreg.
- the puno down switch 654 is constituted by, for example, an N-channel MOS FET.
- the backup signal Sj is input to the gate terminal of the pull-down switch 654, and the negative terminal Vss1 of the clock block 104 is connected to the source terminal.
- This pnore down switch 654 is constituted by a threshold voltage of 0.3 [V], like the oscillation inverter 620 and the like. While the backup signal Sj is at the high level, the pull-down switch 654 causes a short circuit between the output terminal Vreg of the constant voltage circuit 653 and the negative terminal Vss1 of the clock block 104. You. On the other hand, during the period when the backup signal Sj is in the open state, the voltage value of the output terminal Vreg of the constant voltage circuit 653 operates so as to be a predetermined constant voltage.
- the constant voltage circuit 653 outputs the output of the constant voltage circuit 653 as long as the voltage between the ground and the terminal V ss1 is lower than 0.8 [V], similarly to a general constant voltage circuit.
- Terminal V re It is assumed that a potential equal to the negative terminal V ss 1 of the clock block 104 appears at g.
- the negative terminal Vss1 of the clock block 104 indicates a voltage between one ground terminal Vss1.
- the negative terminal Vss2 of the power storage unit 102 indicates a voltage between one ground terminal Vss2.
- FIG. 7 is a circuit diagram showing a configuration of the waveform generator 651 and the control signal generator 107 of the electronic timepiece according to the embodiment of the present invention.
- the waveform generator 651 includes a pulse synthesis circuit 701, a motor driver 702, a first level shifter 703, and a power. Also, the control signal generation unit 107 includes a first NAND gate 711, a first AND gate 712, a second level shifter 713, a first OR gate 714, a second AND gate 715, The first inverter 716, the third AND gate 717, the fourth AND gate 718, and the fifth AND gate 719.
- the absolute value is the same value (0.5 [V] here) as the MOSFET used in the logic circuit of a general electronic watch.
- the threshold value of the N-channel MOSFET is 0.5 [V]
- the threshold value of the P-channel MOS FET is 0.5 [V].
- the other logic circuits in the control signal generation unit 107 are the same as those used in the oscillation unit 601, in both the P-channel and N-channel circuits, using low-voltage MOS FETs with low absolute values of the threshold voltage. It consists of a threshold CMOS circuit. That is, the first NAND gate 711, the first OR gate 714, the second AND gate 715, and the fifth AND gate 719 are connected to a low threshold CMOS circuit (threshold level). The absolute value of the voltage is 0.3 [V].
- the pulse synthesizing circuit 700 is a general logic circuit composed of a frequency dividing circuit (for example, a multi-stage flip-flop circuit) and a plurality of logic gates used in a general electronic timepiece.
- a frequency dividing circuit for example, a multi-stage flip-flop circuit
- the waveform shaping output signal Sb is frequency-divided and the frequency-divided signals obtained from a plurality of frequency-dividing stages are combined to display time.
- the pulse synthesizing circuit 701 outputs the pickup source signal Sc, the boost signal Sd, and the charging clock Se.
- the boost signal S d is a square wave of 409 [H z].
- the charging clock S e is a square wave of 1 [H z].
- the backup original signal Sc is a pulse signal which becomes high level for 1.5 seconds after the power is turned on to the clock block 104. The details of the pulse synthesizing circuit 70 1 will be described later.
- the motor driver 702 is a driver circuit that can convert the level of the motor driving pulse waveform of the clock synthesizing circuit 701 and supply a large current for driving the stepping motor of the time display body 652. is there. Although not particularly shown, the output terminal of the motor driver 72 is connected to a drive coil of a stepping motor of the time display 652.
- the motor driver 7002 has the same circuit configuration as a general electronic timepiece, and a detailed description thereof will be omitted.
- the first level shifter 703 is a level shifter circuit that converts a logic signal having a level between one ground terminal Vreg terminal into a signal having a level between one ground terminal Vss1.
- the backup source signal Sc is level-converted into a backup signal Sj by the first level shifter 703.
- the first NAND gate 7 1 1 is a two-input NAND gate that outputs a NOT signal of the logical product of the waveform shaping output signal Sb and the backup source signal Sc. ing.
- the first AND gate 712 is a two-input AND gate, and outputs a logical product of the power generation detection signal S i and the boost signal S d.
- the second level shifter 7 13 is a level shifter circuit that converts a logic signal having a level between one ground terminal Vreg to a signal having a level between one ground terminal Vss1.
- the second level / shifter 713 is a circuit for level-converting the output of the first AND gate 712.
- the first OR gate 714 is a two-input OR gate, and outputs the logical sum of the output of the second level shifter 713 and the backup signal Sj.
- the second AND gate 715 is a two-input AND gate, and outputs a logical product of the output of the first NAND gate 711 and the first OR gate 714. .
- the output of the second AND gate 715 is set as a boost clock S a.
- the first inverter 716 inverts the charging clock Se output from the pulse synthesizing circuit 701, and outputs a negative signal of the charging clock Se.
- the third AND gate 717 is a two-input gate, and outputs a logical product of the output of the second level shifter 713 and the charging clock Se.
- the output of the third AND gate 717 is the first charging switch signal S f.
- the fourth AND gate 718 is a two-input AND gate, and outputs the logical product of the output of the second level shifter 713 and the output of the first inverter 716. ing.
- the output of the fourth AND gate 718 is the second charging switch signal Sg.
- the fifth AND gate 711 is a two-input AND gate, and outputs a logical product of the backup signal Sj and the first NAND gate 711.
- the output of the fifth AND gate 7 19 is the third charge switch signal Sh.
- the pulse synthesizing circuit 70 1 and the first NAND gate 71 1 are operated by the output terminal V reg (voltage between the ground and the terminal V reg) of the constant voltage circuit 65 3. It has become.
- the other logic circuit elements in the waveform generator 651 and the control signal generator 107 depend on the negative terminal V ss 1 (voltage between the ground and the terminal V ss 1) of the clock block 104. It is supposed to work.
- FIG. 8 is a circuit diagram showing a configuration of a pulse synthesis circuit.
- the pulse synthesizing circuit 701 includes a frequency dividing circuit 801, a power-on reset circuit 802, an AND gate 803, a latch circuit 804, and an inverter 805. I have.
- the frequency divider circuit 81 is a counter circuit composed of 15 or more stages of flip-flops.
- the frequency divider circuit 81 divides the waveform shaping output signal Sb output from the waveform shaping section 603, and converts this frequency-divided signal into a motor signal. Output to driver 700 (see Fig. 7). Further, in the frequency divider circuit 811, the boost signal Sd and the charging clock Se are frequency-divided outputs of the frequency divider circuit.
- the power-on reset circuit 802 outputs a power-on reset signal Sk which outputs a high level (ground potential) for several microphone seconds and then changes to a low level when the circuit itself is powered on. .
- the AND gate 803 inputs the logical product of the 1 [Hz] panoric signal and the 2 [Hz] pulse signal output from the frequency dividing circuit 801 to the latch circuit 804.
- the latch circuit 804 is a logic gate that passes or holds a logic signal.
- FIG. 9 is a time chart showing the operation of the pulse synthesis circuit 71. First, when a power-on reset rises by applying a voltage between the ground and one terminal Vss1, the latch circuit 804 is reset by the power-on reset circuit 802, and the knock-up original signal Sc becomes High level.
- the AND gate 803 outputs a high level in response to the output of the frequency divider circuit 81, so that the latch circuit 804 is set and the backup source signal Sc changes to a low level. This state is maintained. As a result, the backup source signal Sc becomes a pulse signal that becomes high level for 1.5 seconds.
- FIGS. 10 to 13 are flowcharts showing the processing procedure of the overall operation of the electronic timepiece according to the embodiment of the present invention.
- FIG. 14 is a timing chart showing a voltage waveform of a main part of a circuit of the electronic timepiece according to the embodiment of the present invention.
- FIG. 14 shows the period in which the oscillation section 61 1 and its surroundings start operating by the power generation section 101 starting power generation from the state where the electronic timepiece is stopped, and the step-up section 103.
- FIG. 9 shows a period during which the operation is switched to the boosting operation and waveforms of main circuit parts at.
- the waveform diagram of FIG. 14 except for the oscillation output signal S1, the waveform shaping output signal Sb, and the voltage value of the constant voltage output terminal Vreg, only the logic ⁇ ! Is shown on the waveform diagram. I have.
- the power storage unit 102 is empty, the power generation unit 101 is not generating power, and the operation of the clock block 104 is stopped. The case of starting power generation will be described.
- the first to third charging switches 11 1 to 11 shown in FIG. 1 are in an OFF state, and the power generation detection signal Si is at a low level (step S 1001). .
- the power generation unit 101 which is a solar cell, receives light (step S1002: Yes)
- power generation is started (step S1003).
- the power generation detection unit 106 shown in FIG. 1 converts the low-level power generation detection signal S i into a high-level power generation detection signal S i and outputs it (step S 10). 0 4).
- the current output from the power generation unit 101 via the first diode 121 is stored in the capacitor 110 as electric charge.
- the open-circuit voltage of the power generation unit 101 is about 0.4 [V].
- the power supply voltage (the voltage of the terminal Vss1) becomes 0.3 [V] due to the voltage drop of the first diode 121.
- the back-at 7 word Sj becomes high level (ground potential) (step S1005), and the pull-down switch 654 becomes almost conductive (step S1006).
- the voltage value of the constant voltage output terminal Vreg is the same as the voltage value of the power supply voltage (the voltage of the terminal Vss1). In other words, the power supply voltage (voltage at terminal Vss1) and the voltage value at constant voltage output terminal Vreg both become 0.3 [V].
- step S 1007 if the voltage at the terminal Vr eg, which is the operating power supply, that is, the power supply voltage (voltage at the terminal V ss1) in this state is equal to or higher than the threshold value of its own M ⁇ S FET (step S 1007: Yes ), The bias circuit 604 starts operating (step S1008).
- the first bias voltage VP becomes a potential 0.3 [V] lower than the ground potential
- the second bias voltage VN becomes 0.3 from the terminal V reg. [V] High potential.
- the oscillating unit 601 performs an oscillating operation with the oscillating operating point fixed (step S1101). That is, a voltage near the threshold voltage is substantially DC-biased to the gate terminal of the transistor element constituting the oscillating unit 601.
- the oscillation inverter 620 in the oscillation section 601 can operate as an amplifier even from about 0.3 [V]. Further, the oscillation output signal S 1 is fed back to the input side again (via the first and second coupling capacitors 623 and 624 in an AC manner) via the resonance circuit 610, and as a result, the oscillation section 601 is obtained. Oscillates at 32 [KHz], which is the resonance frequency of the resonance circuit 610. Start. This oscillation output signal S1 is substantially a sine wave.
- the current consumption of the oscillation section 60] is determined by the constant current circuit formed by the third transistor element 627, and is suppressed to a set value of about 20 [nA]. Then, the oscillation section 601 performs a stable operation without overtone oscillation. The voltage between the terminals of the stabilizing capacitor 629 is almost 0.3 [V] during the oscillation operation. Then, the waveform shaping section 603 fixes the operating point and starts a stable amplification operation (step S1102). In other words, a voltage substantially near the threshold voltage is DC-biased to the gate terminal of the transistor element forming the waveform shaping unit 603. For this reason, the amplification factor of the transistor element becomes maximum, and the waveform shaping unit 603 can operate as an amplifier even from about 0.3 [V].
- the oscillation output signal S1 is applied to this gate terminal via the third coupling capacitance 633 and the fourth coupling capacitance 634 in an AC manner. As a result, the oscillation output signal S1 is inverted and the amplitude is grounded.
- the waveform shaping output signal Sb amplified to the voltage between one terminal Vreg is output (step S1103).
- the waveform shaping output signal Sb is sent to the second AND gate 715 via the first NAND gate 711 constituted by a low threshold CMOS. Then, the control signal generation unit 107 generates and outputs the boosted clock Sa to the boosting unit 103 (Step S1104).
- the boosting unit 103 starts boosting the power supply voltage (the voltage of the terminal V ss1) applied from the power generating unit 101 based on the boosting clock Sa (Ste S1 105). That is, the series-parallel switching operation of the capacitors 311 to 313 inside the boosting unit 103 is performed by the oscillation frequency of 32 [KHz] of the oscillating unit 601.
- the waveform shaping output signal Sb is sent to the fifth AND gate 719 via the first NAND gate 711.
- the control signal generation unit 107 generates the third charging switch signal Sh in which the negative signal of the waveform shaping output signal Sb is amplified and becomes a square wave, and outputs it to the switching control unit 108 (step S 1 106).
- Third charging switch]. 13 performs an opening / closing operation in synchronization with the boosting operation of the boosting unit 103 due to the input of the third charging switch signal Sh (step S1107).
- an operation is performed to send the boosted output to the clock block 104 (step S1201).
- the pulse synthesizing circuit 701 and the motor dryino 702, etc. which are configured by the MOSFET having a high threshold voltage, do not operate.
- the power supply voltage (the voltage of the terminal Vss1) increases.
- the pull-down switch 654 remains conductive, so that the voltage of the constant voltage output terminal V reg remains the same as the power supply voltage (the voltage of the terminal V ss1). It is.
- the power supply voltage (voltage at terminal V ss 1) eventually rises to about 1.6 [V], which is four times the generated voltage. If the power supply voltage (the voltage of the terminal V ss 1) is boosted to the operating voltage (for example, 1.2 [V]) of the timer unit 605 (step S 1202: Yes), the pulse synthesis circuit 70 1 Operation starts (Step S1 203) 0
- the pulse synthesizing circuit 701 can also perform the frequency division and the pulse synthesizing operation, and outputs the boosting clock Sd and the charging clock Se (step S1204). Also, if 1.5 seconds have elapsed since the start of the operation of the oscillation section 601 (step S1205: Yes), the backup signal Sj (that is, the backup source signal Sc) falls from the high level to the low level ( Step S1 206).
- the down switch 654 is turned off (step S1207).
- the voltage value of the constant voltage output terminal Vreg switches to a predetermined constant voltage value. Since the constant voltage circuit 653 operates at a constant voltage, the voltage value of the constant voltage output terminal Vreg does not exceed the predetermined constant voltage value even if the power supply voltage (the voltage of the terminal Vss1) increases.
- step S1301: Yes When 1.5 seconds have elapsed since the oscillation section 601 started operating, and the power generation detection section 106 detects power generation (step S1301: Yes), the power generation detection signal S i becomes Hold high level. Then, the boost signal Sd is sent to the third AND gate 7 17 and the fourth AND gate 7 18 via the first AND gate 7 12 and the second level shifter 7 13.
- the boost signal Sd appears every 500 ms in the first charge switch signal Sf and the second charge switch signal Sg, and the first charge switch signal Sf and the second charge switch The signal S g is output.
- the first charging switch signal S # is input to the first charging switch 111
- the first charging switch 111 opens and closes (step S1302).
- the booster 103 outputs the boosted output to the clock block 104, and the clocking operation of the clock block 104 is performed (step S133).
- step S1304 when the second charging switch signal Sg is input to the second charging switch 112, the second charging switch 112 opens and closes (step S1304). As a result, the voltage is boosted from boosting section 103 to power storage section 102, and the power storage operation of power storage section 102 is performed (step S135). Thereafter, the process returns to step S1301.
- the first charging switch 111 and the second charging switch 112 distribute the boosted output from the booster 103 to the clock block 104 and the power storage unit 102,
- the clocking operation of the clock block 104 and the charging operation of the power storage unit 102 can be performed in parallel.
- the power generation detection unit 106 detects this and the boosting unit 103 performs the boosting operation, so that the time is displayed and the power storage unit 1 is displayed. 0 2 can be charged.
- step S1301 when power generation is not detected (step S1301: No), the power generation unit 101 is in a non-power generation state, and the power generation detection signal Si is at a low level (step S1306). As a result, the boost clock S a goes low (step S 1307), and the output of the first charge switch signal S f and the second charge switch signal S g stops. As a result, the opening / closing operation of the first charging switch 1 1 1 and the second charging switch 1 12 is stopped (step S 1308). As a result, the boosting operation of the booster 103 stops.
- step S1309 Yes
- step S1310 timekeeping operation of timekeeping unit 605 is performed.
- step S1310 the flow returns to step S1301.
- the clocking operation of the clock block 104 can be continued even when the power generation unit 101 is in a non-power generation state.
- the booster 103 forcibly outputs the boosted output to the clock 104 for 1.5 seconds corresponding to a predetermined period immediately after the electronic clock 100 starts oscillating. After that, it can operate to output boosted voltage depending on the presence or absence of power generation.
- the period during which the boosting unit 103 operates is fixed to a predetermined time of 1.5 seconds after the oscillation unit 601 starts, but the electronic timepiece 100 is started more safely. Therefore, the booster 103 may be continuously operated until the voltage between the terminals of the clock block 104 is sufficiently increased.
- FIG. 15 is a block diagram showing another example of the waveform generator.
- the same components as those of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.
- the waveform generation unit 1500 includes the power of the panorama synthesis circuit 701, the motor driver 702 and the level shifter 703 shown in FIG. 7, a power supply voltage detection unit 1501, and a power on It is composed of a reset circuit 1502, a latch circuit 1503, and an inverter 1504. These are: It can be composed of MOSFETs having the same threshold value as the noise combining circuit 701 and the like.
- the power-on reset circuit 1502 is a circuit that outputs a high-level (ground potential) for several microphone seconds and then outputs a power-on reset signal that changes to a mouth level when the circuit itself is turned on.
- the power supply voltage detection section 1501 is a general voltage detection circuit that determines whether the input voltage is lower than a predetermined voltage. Here, a low level is output if the voltage applied to the clock block 104 is less than 1.2 [V], and a high level is output otherwise.
- the output signal of the power supply voltage detection section 1501 is a power supply voltage detection signal Sm.
- the latch circuit 1503 is a general latch circuit composed of two NOR gates. No input to the reset input of the latch circuit 1503. A signal output from the power-on reset circuit 1502 is input, and the power supply voltage detection signal Sm is input to the set input.
- the output signal of the latch circuit 1503 is input to the inverter 1504 to generate a negative signal of the output signal of the latch circuit 1503.
- the output signal of the inverter 1504 is input to the NAND gate 711 and the first level shifter 703 as the backup source signal Sc shown in the embodiment.
- FIG. 16 is a flowchart showing an operation processing procedure of the electronic timepiece 100 when the waveform generator 150 is used.
- FIG. 17 is a flowchart showing the operation of the waveform generator 150.
- 6 is a timing chart showing a voltage waveform of a main part of a circuit of the electronic timepiece 100 when the electronic timepiece 100 is used.
- the start-up procedure shown in FIGS. 10, 11 and 13 is common to this start-up procedure, and a description thereof will be omitted.
- step S 161 when the power supply voltage (the voltage of the terminal Vss1) has not been raised to the operating voltage of the timer section 605 (for example, 1.2 [V]) (step S 161: No), the power supply voltage detection signal S m holds the low level (step S 162). Therefore, since the latch circuit 1503 also holds the reset state (step S1663), the backup signal Si also holds the high level (step S1603). Step SI604), Continuing to boost the capacitor 110 and the clock block 104. Then, the process returns to step S1661.
- step S1601 Y es
- the voltage detection signal Sm switches from a low level to a high level (step S165). Accordingly, the latch circuit 1503 also switches from the reset state to the set state (step S166), and the backup signal Sj also falls from the high level to the mouth level (step S166).
- the pull-down switch 654 is turned off (step S166). This stops the boost operation.
- the electronic timepiece 1 ⁇ 0 is operated from immediately after the oscillation of the electronic timepiece 100 is started until the terminal voltage of the clock block 104 reaches 1.2 [V] corresponding to a predetermined voltage value. Then, the booster section 103 forcibly outputs a boosted output to the clock block 104, and thereafter operates so as to perform the boosted output according to the presence or absence of power generation.
- the operation of the pulse synthesizing circuit 701 starts (step S169).
- the pulse synthesizing circuit 701 can also perform frequency division and pulse synthesizing operations, and output the boosting clock Sd and the charging clock Se (step S1610).
- the process proceeds to step S1301 shown in FIG. 13, and the boosting unit 103 can perform the boosting operation according to the power generation state of the power generation unit 101.
- the electronic timepiece 100 is operated from immediately after the oscillation section 601 starts oscillating until the terminal voltage of the clock block 104 reaches 1.2 [V] corresponding to a predetermined voltage value.
- the booster section 103 forcibly outputs the boosted output to the clock block 104, and thereafter operates to perform the boosted output according to the presence or absence of power generation.
- Block 104 starts electronic clock safely without malfunction at low voltage Can work.
- a timer function for a predetermined time (1.5 seconds) for performing the boosting operation in the above-described embodiment is not provided in the waveform generation unit, but is provided to the control signal generation unit independently of the waveform generation unit. It is a configuration example provided.
- FIG. 18 is a block diagram showing another configuration example of the waveform generator and the control signal generator.
- FIG. 19 shows a timer function provided in the control signal generator shown in FIG. It is a time chart.
- the same components as those of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.
- the internal configuration of the control signal generation unit 1802 not shown in FIG. 18 is the same as that of the control signal generation unit 107 of the above-described embodiment (see FIG. 7). Therefore, it is omitted here.
- the frequency divider circuit 1801 shown in FIG. 18 is a counter circuit including 15 or more stages of flip-flops, like the frequency divider circuit 81 shown in FIG.
- the frequency shaping output signal Sb output from the waveform shaping section 603 is frequency-divided, and this frequency-divided signal is output to the motor driver 702.
- the frequency divider circuit 81 outputs a boost signal Sd and a charging clock Se.
- the frequency dividing circuit 1801 supplies the control signal generating section] .802 with a 1 [Hz] pulse signal and a 1 [Hz] signal for generating a backup source signal Sc which is a reference for the boosting operation. And 2 [H z] pulse signals are not output.
- the power-on reset circuit 1803 is a circuit that outputs a power-on reset signal that changes to a speech level after outputting a high level (ground potential) for several microphone mouth seconds when the circuit itself is powered on. is there.
- the timer circuit 1804 as a boost stop instruction signal output unit is a circuit that outputs a timer signal So for 1.5 seconds after the power is turned on, and then changes to a high level after being output to a high level.
- the latch circuit 1805 resets the power-on reset signal. When a set signal is input and the timer signal S0 is set, a certain signal passing through the logic signal is constituted by a logic gate that holds the signal.
- the power-on reset signal of the power-on reset circuit 1803 causes the latch circuit 18 05 is reset, and the backup source signal Sc becomes high level by the inverter 1806.
- the timer circuit 1804 outputs a high level, so the latch circuit 1805 is set, and the knock-up source signal Sc becomes low level by the inverter] -806. And this state is maintained. Then, as a result, the backup source signal Sc becomes a pulse signal that becomes high level for 1.5 seconds.
- the timer circuit for stopping the boosting operation is different from the frequency divider circuit 1801 Since it can be configured separately, it is possible to change the output timing of the timer signal So only by replacing the timer circuit, and to change the stop time of the boost operation at startup for each electronic clock. Can be.
- FIG. 20 is a block diagram showing a hardware configuration of a boost stop instruction signal output unit for changing a predetermined time.
- this step-up stop instruction signal output section 20000 includes a CPU 2001, a RAM200, a ROM2003, and inputs I and F ( Interface) 204, EEPROM 202 which is a non-volatile memory, and outputs I and F (interface) 206, which are connected to bus 207. .
- CPU 2001 controls the entire boost stop instruction signal output unit 2000. This
- the CPU 201 is configured to be driven by a low voltage.
- the CPU 201 is driven by a negative terminal V ss 1 (a voltage between one ground terminal V ss) of the clock block 104. It works.
- the RAM 2002 is used as a work area of the CPU 2001.
- the ROM 2003 stores a program for executing the timer processing and the like.
- the input IF 2004 inputs time information obtained by operating the input key 2010.
- This input key 2010 is a switchable switch or button that can select four types of time information, such as 0.5 seconds, 1.0 seconds, 1.5 seconds, or 2.0 seconds. And so on.
- the input time information is written into the EEPROM 2005. If there are four types of time information as described above, EE PROM 2005 can be configured with about 2 bits. Note that a flash memory may be used instead of the EEPROM 2005.
- the output I / F 2006 outputs the generated boost stop instruction signal to the latch circuit 1805 shown in FIG.
- FIG. 21 is a block diagram showing a functional configuration of a boost stop instruction signal output unit shown in FIG.
- the input unit 2101 inputs any time information selected by operating the input key 2010. Specifically, the function of the input unit 21 1 is realized by the input I / F 2004 shown in FIG.
- the time information writing processing unit 2102 writes the time information input from the input unit 2101 to the time information storage unit 2103. At this time, the time information stored so far is deleted.
- This time information write processing unit 2 102 specifically, it can, for example, realizes its function by the program stored in the ROM 2003 shown in FIG. 20 CPU 200 1 is executed.
- the time information storage unit 2103 stores the time information written by the time information writing processing unit 2102.
- the function of the time information storage unit 2103 is specifically realized by, for example, the EE PROM 2005 shown in FIG.
- the time information extraction unit 2104 The time information stored in 2 103 is extracted.
- the time information extraction unit 210 is, for example, implemented by executing a program stored in the ROM 2000 shown in FIG. To achieve.
- the boosting stop instruction signal generation unit 210 generates the boosting stop instruction signal corresponding to the time interval of the time information, based on the time information extracted by the time information extracting unit 210, and the latch circuit 18 0 Output to 5.
- This boost stop instruction signal is the same as the timer signal So shown in FIG. 19, but the rise time differs for each time information. For example, if the time information is 0.5 seconds, the time until the boost stop instruction signal rises is also 0.5 seconds.
- the boost stop instruction signal generation unit 2105 executes the program stored in the ROM 2003 shown in FIG. Implement the function.
- FIG. 22 is a flowchart showing the procedure of the boosting stop instruction signal output process of the boosting stop instruction signal output unit 2000.
- step S2201 when the input key 201 is operated (step S2201: Yes), the time information selected by the operation of the input key 210 is converted to the time information. The data is written to the storage unit 210 (step S2202).
- step S2203 Yes
- step S2204 the time information stored in the time information storage unit 210 is extracted (step S2204).
- a timer signal So is generated from the extracted time information as a boost stop instruction signal and output to the latch circuit 1805 (step S2205). If a plurality of types of electronic timepieces are manufactured, for example, set to 1.5 seconds uniformly, the time can be changed at the time of shipment or sale, and the size and size of each electronic timepiece can be changed. Boost operation according to the effective light receiving area of power generation unit 101 depending on design A change process of a predetermined time serving as a reference can be performed, and a stable start can be performed according to the type of the electronic timepiece.
- an electronic watch for women is smaller than an electronic watch for men, so the solar cell that is the power generation unit 101 is also small, and the effective light receiving area is also small.
- the time interval of the predetermined time which is the reference for the boosting operation, to be longer, stable start-up can be performed even when the solar cell is not generating or charging. .
- the crystal oscillation circuit itself is started to oscillate by application of a low power generation voltage of 0.4 [V], which is lower than that of one solar cell. be able to.
- V a low power generation voltage
- the size of the solar cell can be reduced, and the size of the electronic timepiece 100 itself can be reduced.
- even a female electronic watch 100, which is smaller than a male electronic watch can be started by low-voltage power generation.
- the weight of the electronic timepiece 100 can be reduced, the portability can be improved, and the electronic timepiece 100 can be manufactured without fatigue even when the electronic timepiece is attached to the wrist for a long time.
- a disk-shaped solar cell laid under the dial can generate a high power supply voltage and is restricted by a black dial with good transmission characteristics of incident light.
- the oscillating unit 601 can be started at a low voltage by a starting voltage lower than the power supply voltage of the power generating unit 101, the electronic timepiece 100 can be sufficiently started even if the light receiving efficiency is reduced. . Therefore, it is not necessary to limit the dial to a black type, and dials of various colors can be adopted, so that decorativeness can be improved.
- the oscillating unit 601 and the waveform shaping unit 603 directly drive the boosting unit 103 with the boosted clock Sa having the same frequency as the oscillation frequency immediately after the start of oscillation.
- a load such as a stepping motor having a higher rated voltage than the starting voltage of the oscillation section 601 itself can be operated immediately.
- the electronic timepiece 100 employs a crystal oscillator 611 used for an oscillation circuit of a general electronic timepiece, and uses other oscillation circuits such as a CR oscillation circuit and a ring oscillation circuit which consume a large amount of current. Is not used. Therefore, the current required for the oscillating operation can be significantly reduced, and the oscillation can be easily started, and the electronic watch 100 can be started smoothly.
- thermoelectric generator having a high output resistance value to be used as the power generation unit 101.
- an oscillation circuit such as a CR oscillation circuit or a ring oscillation circuit that consumes large current, and the number of components can be reduced. This reduction in the number of parts can reduce the size of the electronic watch 100, making it possible to design a small electronic watch like the electronic watch 100 for women and improve the degree of freedom in designing. it can.
- the circuit elements constituting electronic timepiece 100 in the above-described embodiment are not limited to these.
- the second diode 122 was used to supply power from the power storage unit 102 to the clock block 104 in order to simplify the charge / discharge control path of the power storage unit 102.
- This can also be used as a switch composed of M ⁇ SFET.
- the first diode 1221 may be a switch composed of MOS FET.
- the booster 103 is assumed to be of the type that switches the connection state of the capacitor, other types that use an induced voltage generated in the coil may be used.
- the present invention can be applied to electronic watches for women, which are required to be miniaturized.
- the electronic timepiece 100 that generates power using a solar cell has been described as the power generation unit 101.
- a plurality of thermocouples that generate heat energy by the heat of the human body are provided.
- a temperature-difference-type electronic timepiece that serializes and generates electric power based on the temperature difference between both ends of the thermocouple, and a mechanical-powered type electronic timepiece that generates electric power by converting mechanical energy obtained by the vibration of a rotating spindle into electric energy Can also be applied.
- various electronic devices other than the electronic timepiece 100 can be driven by using a generator having a low generated voltage.
- the electronic device other than the electronic timepiece 100 include a portable electronic device, for example, a mobile phone, a PDA (PersonadalDigita1Assistanc), or a portable radio (for example, a card-type radio).
- a portable electronic device for example, a mobile phone, a PDA (PersonadalDigita1Assistanc), or a portable radio (for example, a card-type radio).
- the timing unit 605 shown in Fig. 1 by replacing the timing unit 605 shown in Fig. 1 with an operating unit that performs operations unique to the electronic device, the oscillation output from the oscillating unit 601 that started at low voltage starts the electronic device. Can be performed.
- the power supply voltage can be increased to the operation voltage by applying a power supply voltage lower than the operation voltage required when the electronic timepiece or the electronic device operates. Therefore, even if the power supply voltage generated by converting external energy obtained from the sun or the light of lighting, heat or vibration of the human body into electrical energy is lower than the operating voltage, the electronic watch or electronic device can be reliably used. This has the effect of being able to be activated.
- a power supply voltage generating means for converting external energy into electric energy for example, a solar cell, a thermocouple or
- the oscillating weight can be miniaturized to such an extent that a power supply voltage can be generated, and the electronic timepiece and the electronic device can be miniaturized.
- small solar cells, thermocouples, or circuits whose generated voltage is about the power supply voltage Even when the oscillating weight is mounted, since it can be started sufficiently, it has an effect that it can be applied to an electronic timepiece for women which is smaller than an electronic timepiece for men. In addition, there is no need to provide large solar cells, thermocouples or rotating weights for generating an operating voltage, so that a small female electronic timepiece with fine decoration can be produced.
- the present invention can be applied to electronic timepieces having a power generation function of converting external energy into electric energy, and electronic devices such as mobile phones, PDAs, and portable radios.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
- Dc-Dc Converters (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004539497A JP4459812B2 (ja) | 2002-09-24 | 2003-09-24 | 電子時計 |
EP03748571A EP1544694B1 (en) | 2002-09-24 | 2003-09-24 | Electronic timepiece |
US10/528,807 US7327638B2 (en) | 2002-09-24 | 2003-09-24 | Electronic timepiece |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-276572 | 2002-09-24 | ||
JP2002276572 | 2002-09-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004029735A1 true WO2004029735A1 (ja) | 2004-04-08 |
Family
ID=32040385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/012145 WO2004029735A1 (ja) | 2002-09-24 | 2003-09-24 | 電子時計、電子機器および起動方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7327638B2 (ja) |
EP (1) | EP1544694B1 (ja) |
JP (1) | JP4459812B2 (ja) |
CN (1) | CN100422879C (ja) |
WO (1) | WO2004029735A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7474249B1 (en) * | 2004-08-12 | 2009-01-06 | Lockheed Martin Corporation | Systems and methods for dedicating power to a radar module |
JP5211534B2 (ja) * | 2007-04-03 | 2013-06-12 | セイコーエプソン株式会社 | 発電機能付き電子時計 |
WO2010011118A1 (es) * | 2008-07-21 | 2010-01-28 | Garcia De Alba Garcin Sergio | Un convertidor boost auto-oscilatorio para aplicaciones solares |
CN103038990B (zh) | 2008-07-24 | 2016-06-22 | 三菱电机株式会社 | 电力变换装置 |
JP2011147330A (ja) * | 2009-12-16 | 2011-07-28 | Seiko Instruments Inc | ステッピングモータ制御回路及びアナログ電子時計 |
JP5823747B2 (ja) * | 2010-09-03 | 2015-11-25 | セイコーインスツル株式会社 | 消費電力制御装置、時計装置、電子機器、消費電力制御方法、及び消費電力制御プログラム |
KR20150019000A (ko) * | 2013-08-12 | 2015-02-25 | 삼성디스플레이 주식회사 | 기준 전류 생성 회로 및 이의 구동 방법 |
CN104467810B (zh) * | 2014-12-05 | 2018-07-13 | 无锡中感微电子股份有限公司 | 一种数字整形方法和采用该方法的时钟系统 |
US10171033B2 (en) * | 2016-11-03 | 2019-01-01 | Intel Corporation | Crystal oscillator interconnect architecture with noise immunity |
DE102017204044A1 (de) | 2017-02-14 | 2018-08-16 | Ellenberger & Poensgen Gmbh | Verfahren und Spannungsvervielfacher zur Wandlung einer Eingangsspannung sowie Trennschaltung |
JP6658610B2 (ja) * | 2017-02-27 | 2020-03-04 | カシオ計算機株式会社 | 情報通知方法、情報通知装置、及びプログラム |
JP7200512B2 (ja) * | 2018-06-21 | 2023-01-10 | カシオ計算機株式会社 | 電子機器、電子時計および電池充電方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5625280U (ja) * | 1980-07-16 | 1981-03-07 | ||
JPS5745483A (en) * | 1980-09-02 | 1982-03-15 | Citizen Watch Co Ltd | Circuit for electrooptic display timepiece |
JPH078108B2 (ja) * | 1985-06-03 | 1995-01-30 | カシオ計算機株式会社 | 電源供給方式 |
EP0898355A2 (en) * | 1997-07-22 | 1999-02-24 | Seiko Instruments R&D Center Inc. | Electronic apparatus |
JP7092507B2 (ja) * | 2017-03-17 | 2022-06-28 | ザ・ボーイング・カンパニー | 自己整列するリベット締め工具及びその動作方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240371A (en) * | 1975-09-27 | 1977-03-29 | Citizen Watch Co Ltd | Electronic watch |
JPS54123068A (en) * | 1978-03-17 | 1979-09-25 | Citizen Watch Co Ltd | Electronic watch |
US4653931A (en) * | 1983-11-21 | 1987-03-31 | Shiojiri Kogyo Kabushiki Kaisha | Self-charging electronic timepiece |
JPH0792507B2 (ja) * | 1985-03-29 | 1995-10-09 | セイコーエプソン株式会社 | 電子時計 |
JP2622540B2 (ja) * | 1985-04-10 | 1997-06-18 | セイコーエプソン株式会社 | 電子時計 |
JP2973273B2 (ja) * | 1994-05-13 | 1999-11-08 | セイコーエプソン株式会社 | 電子時計及びその充電方法 |
JP3174245B2 (ja) * | 1994-08-03 | 2001-06-11 | セイコーインスツルメンツ株式会社 | 電子制御時計 |
JPH0996686A (ja) * | 1995-09-29 | 1997-04-08 | Citizen Watch Co Ltd | 電子時計とその充電方法 |
CH691010A5 (fr) * | 1997-01-09 | 2001-03-30 | Asulab Sa | Appareil électrique fonctionnant à l'aide d'une source photovoltaïque, notamment pièce d'horlogerie. |
JP3650269B2 (ja) * | 1997-10-07 | 2005-05-18 | セイコーインスツル株式会社 | 発電素子を有する電子時計 |
US6301198B1 (en) * | 1997-12-11 | 2001-10-09 | Citizen Watch Co., Ltd. | Electronic timepiece |
JP2000125578A (ja) * | 1998-07-02 | 2000-04-28 | Citizen Watch Co Ltd | 熱電システム |
DE69927949T2 (de) * | 1998-12-04 | 2006-07-27 | Seiko Epson Corp. | Elektronische vorrichtung, elektronisches uhrwerk und leistungsregelungsverfahren |
JP3596383B2 (ja) * | 1999-11-04 | 2004-12-02 | セイコーエプソン株式会社 | 発電機を持つ電子時計の充電装置、電子時計、及び充電装置の制御方法 |
JP2002280834A (ja) | 2001-03-16 | 2002-09-27 | Citizen Watch Co Ltd | 発振回路およびそれを用いた電子時計 |
JP4963764B2 (ja) | 2001-09-11 | 2012-06-27 | シチズンホールディングス株式会社 | 電子時計 |
-
2003
- 2003-09-24 US US10/528,807 patent/US7327638B2/en active Active
- 2003-09-24 JP JP2004539497A patent/JP4459812B2/ja not_active Expired - Lifetime
- 2003-09-24 EP EP03748571A patent/EP1544694B1/en not_active Expired - Lifetime
- 2003-09-24 CN CNB038253631A patent/CN100422879C/zh not_active Expired - Lifetime
- 2003-09-24 WO PCT/JP2003/012145 patent/WO2004029735A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5625280U (ja) * | 1980-07-16 | 1981-03-07 | ||
JPS5745483A (en) * | 1980-09-02 | 1982-03-15 | Citizen Watch Co Ltd | Circuit for electrooptic display timepiece |
JPH078108B2 (ja) * | 1985-06-03 | 1995-01-30 | カシオ計算機株式会社 | 電源供給方式 |
EP0898355A2 (en) * | 1997-07-22 | 1999-02-24 | Seiko Instruments R&D Center Inc. | Electronic apparatus |
JP7092507B2 (ja) * | 2017-03-17 | 2022-06-28 | ザ・ボーイング・カンパニー | 自己整列するリベット締め工具及びその動作方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1544694A4 * |
Also Published As
Publication number | Publication date |
---|---|
US20050243657A1 (en) | 2005-11-03 |
CN1701284A (zh) | 2005-11-23 |
JPWO2004029735A1 (ja) | 2006-01-26 |
EP1544694A1 (en) | 2005-06-22 |
CN100422879C (zh) | 2008-10-01 |
JP4459812B2 (ja) | 2010-04-28 |
EP1544694A4 (en) | 2008-06-18 |
EP1544694B1 (en) | 2012-04-04 |
US7327638B2 (en) | 2008-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2004029735A1 (ja) | 電子時計、電子機器および起動方法 | |
JP3271992B2 (ja) | 電子時計 | |
JPH11174167A (ja) | 発電素子を有する電子時計 | |
US6580665B1 (en) | Electronic timepiece having power generating function | |
JP4652491B2 (ja) | 光電源で給電される電気装置、特に時計 | |
JP5458692B2 (ja) | 電子装置 | |
US4763310A (en) | Electronic clock with solar cell and rechangeable battery | |
JP2000504834A (ja) | 光電池を用いた蓄電池充電装置と、そのような充填装置を有する時計 | |
US6646960B1 (en) | Electronic timepiece | |
JP3830289B2 (ja) | 電子機器および計時装置 | |
JP3601375B2 (ja) | 携帯用電子機器及び携帯用電子機器の制御方法 | |
JP6610048B2 (ja) | 半導体装置および電子時計 | |
WO1998035272A1 (fr) | Horloge electronique | |
JP4963764B2 (ja) | 電子時計 | |
JP4647806B2 (ja) | 昇圧システム | |
JP4234472B2 (ja) | 電子時計 | |
JP4055446B2 (ja) | 電子機器、電子機器の制御方法、計時装置、および計時装置の制御方法 | |
JPH10206568A (ja) | 発振回路、半導体装置及びこれらを具備した携帯用電子機器および時計 | |
JP3017541B2 (ja) | 電子時計 | |
JP2002280834A (ja) | 発振回路およびそれを用いた電子時計 | |
JP2004135497A (ja) | 電子機器、電子制御式時計および電源制御方法 | |
JPS6359475B2 (ja) | ||
JPH01114333A (ja) | 電源回路 | |
JPH0549180A (ja) | 電源回路 | |
JP2002328188A (ja) | 携帯用電子機器及び携帯用電子機器の制御方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2004539497 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2003748571 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10528807 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 20038253631 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 2003748571 Country of ref document: EP |