WO2004004002A1 - Unter ein pad integrierte halbleiterstruktur - Google Patents

Unter ein pad integrierte halbleiterstruktur Download PDF

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Publication number
WO2004004002A1
WO2004004002A1 PCT/DE2003/001955 DE0301955W WO2004004002A1 WO 2004004002 A1 WO2004004002 A1 WO 2004004002A1 DE 0301955 W DE0301955 W DE 0301955W WO 2004004002 A1 WO2004004002 A1 WO 2004004002A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
semiconductor structure
conductor tracks
integrated semiconductor
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2003/001955
Other languages
German (de)
English (en)
French (fr)
Inventor
Robert Bauer
Werner Ertle
Till FROHNMÜLLER
Bernd Goller
Reinhard Greiderer
Oliver Nagler
Olaf Schmeckebier
Wolfgang Stadler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to US10/519,860 priority Critical patent/US7190077B2/en
Priority to DE50311482T priority patent/DE50311482D1/de
Priority to EP03761414A priority patent/EP1518272B1/de
Priority to JP2004516476A priority patent/JP4065876B2/ja
Publication of WO2004004002A1 publication Critical patent/WO2004004002A1/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
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    • H01L2924/3025—Electromagnetic shielding

Definitions

  • Such a semiconductor structure is, for example, from the US. 6,207,547.
  • One embodiment of the integrated semiconductor structure according to the invention provides that the number of conductor tracks within a metal layer, at least below the surface of the pad metal, is between 2 and 6, depending on the size and extent of this pad metal. According to the invention, the conductor tracks can be electrically insulated from one another within a metal layer.
  • a further advantageous embodiment of the integrated semiconductor structure provides that the metal layers consist, at least for the most part, of a sufficiently hard metal. This can prevent the thickness of the metal layers from decreasing under mechanical stress or the insulation layer which lies above the metal layer from being pushed through to the insulation layer lying underneath.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
PCT/DE2003/001955 2002-07-01 2003-06-12 Unter ein pad integrierte halbleiterstruktur Ceased WO2004004002A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/519,860 US7190077B2 (en) 2002-07-01 2003-06-12 Semiconductor structure integrated under a pad
DE50311482T DE50311482D1 (enExample) 2002-07-01 2003-06-12
EP03761414A EP1518272B1 (de) 2002-07-01 2003-06-12 Unter ein pad integrierte halbleiterstruktur
JP2004516476A JP4065876B2 (ja) 2002-07-01 2003-06-12 パッド下の集積半導体構造

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10229493A DE10229493B4 (de) 2002-07-01 2002-07-01 Integrierte Halbleiterstruktur
DE10229493.3 2002-07-01

Publications (1)

Publication Number Publication Date
WO2004004002A1 true WO2004004002A1 (de) 2004-01-08

Family

ID=29796063

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001955 Ceased WO2004004002A1 (de) 2002-07-01 2003-06-12 Unter ein pad integrierte halbleiterstruktur

Country Status (7)

Country Link
US (1) US7190077B2 (enExample)
EP (1) EP1518272B1 (enExample)
JP (1) JP4065876B2 (enExample)
CN (1) CN100440497C (enExample)
DE (2) DE10229493B4 (enExample)
TW (1) TWI237890B (enExample)
WO (1) WO2004004002A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108329A (ja) * 2004-10-04 2006-04-20 Fujitsu Ltd 半導体装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100413066C (zh) * 2005-11-30 2008-08-20 中芯国际集成电路制造(上海)有限公司 低k介电材料的接合焊盘和用于制造半导体器件的方法
JP5353313B2 (ja) * 2009-03-06 2013-11-27 富士通セミコンダクター株式会社 半導体装置
KR101823677B1 (ko) 2011-04-21 2018-01-30 엘지이노텍 주식회사 엘이디 조명장치
US20130154099A1 (en) * 2011-12-16 2013-06-20 Semiconductor Components Industries, Llc Pad over interconnect pad structure design
CN102571135B (zh) * 2012-02-15 2014-05-14 京信通信系统（中国）有限公司 射频半集成应用装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US20010010408A1 (en) * 1999-03-19 2001-08-02 Ming-Dou Ker Low-capacitance bonding pad for semiconductor device
EP1143513A1 (en) * 2000-04-03 2001-10-10 Nec Corporation Semiconductor device and method of fabricating the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2598328B2 (ja) * 1989-10-17 1997-04-09 三菱電機株式会社 半導体装置およびその製造方法
KR100267105B1 (ko) * 1997-12-09 2000-11-01 윤종용 다층패드를구비한반도체소자및그제조방법
US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6087732A (en) * 1998-09-28 2000-07-11 Lucent Technologies, Inc. Bond pad for a flip-chip package
JP2000183104A (ja) * 1998-12-15 2000-06-30 Texas Instr Inc <Ti> 集積回路上でボンディングするためのシステム及び方法
US7201784B2 (en) * 2003-06-30 2007-04-10 Intel Corporation Surfactant slurry additives to improve erosion, dishing, and defects during chemical mechanical polishing of copper damascene with low k dielectrics

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US20010010408A1 (en) * 1999-03-19 2001-08-02 Ming-Dou Ker Low-capacitance bonding pad for semiconductor device
EP1143513A1 (en) * 2000-04-03 2001-10-10 Nec Corporation Semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108329A (ja) * 2004-10-04 2006-04-20 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
JP4065876B2 (ja) 2008-03-26
US20050242374A1 (en) 2005-11-03
DE10229493B4 (de) 2007-03-29
DE10229493A1 (de) 2004-01-29
DE50311482D1 (enExample) 2009-06-10
CN100440497C (zh) 2008-12-03
TW200402863A (en) 2004-02-16
JP2006502561A (ja) 2006-01-19
EP1518272B1 (de) 2009-04-29
CN1666336A (zh) 2005-09-07
EP1518272A1 (de) 2005-03-30
US7190077B2 (en) 2007-03-13
TWI237890B (en) 2005-08-11

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