CN100440497C - 集成半导体结构 - Google Patents

集成半导体结构 Download PDF

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CN100440497C
CN100440497C CNB038157144A CN03815714A CN100440497C CN 100440497 C CN100440497 C CN 100440497C CN B038157144 A CNB038157144 A CN B038157144A CN 03815714 A CN03815714 A CN 03815714A CN 100440497 C CN100440497 C CN 100440497C
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metal
interconnection
semiconductor structure
pad metal
pad
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CN1666336A (zh
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R·鲍尔
W·厄特勒
T·弗罗赫米勒
B·戈尔勒
R·格雷德尔
O·纳格勒
O·施梅克比尔
W·斯塔德勒
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Infineon Technologies AG
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Abstract

本发明系关于一种集成半导体结构，其具基板(1)，至少一位于该基板(1)上的半导体组件(2)，具表面(F)的垫金属(3)，位于该垫金属(3)及该基板(1)之间的许多金属层(4.x)，及许多绝缘层(5，y)，其将该金属层(4.x)彼此分开，至少在部分该至少一半导体组件(2)上延伸的该垫金属(3)。本发明特征在于在该垫金属(3)的表面(F)下方，至少该顶部两金属层(4.x、4.x-1)具一种至少包括两相邻的互连(4.x.z、4.x-1.z)的结构。

Description

集成半导体结构
技术领域
本发明涉及一种集成半导体结构，其具基板，至少一位于该基板上的半导体组件，具表面的垫金属，位于该垫金属及该基板之间的多个金属层，及多个绝缘层，其将金属层彼此分开，垫金属至少在部分该至少一半导体组件上延伸。
背景技术
此种形式的半导体基板由美国专利第6,207,547号为已知。
在集成半导体结构的制造的重要方向为位于该半导体结构内的该半导体组件的电接触(连结)。在此情况下，在外框接触(PINs)及该半导体组件间的电接触经由接触岛产生，该接触岛为电连接至该半导体组件及金属层的金属区域(垫金属)。因为目前所使用的连接方法，与下方该半导体组件的尺寸相较，该垫金属为在该半导体结构的相当大尺寸。所以，该垫金属覆盖该芯片表面的显著部分，及结果位于该垫金属下方的区域形成该芯片体积的显著部分。
在该半导体结构的连结期间，高机械负荷出现于该垫金属，此负荷带来位于该垫金属下方的结构被损伤的风险。例如，直接在该垫金属下方的顶部绝缘层可能变为破裂的，因为该半导体结构的保护被损坏，导致漏电流。第二，因可靠性的原因，该半导体组件，如主动结构，如具相当薄栅极氧化物的MOS晶体管，在所有情况下必须被保护免于额外压力。所以，先前半导体组件并未置于该垫金属下方，以避免损伤，此表示相当大的芯片面积的损失必须被接受。
欧洲专利第1 017 098 A2号提出应力吸收金属层及机械加强电绝缘层的组合，及足够厚度的这两层，使得至少部分该半导体组件可直接在该垫金属下方延伸，然而，此仅些微地减少在该芯片表面上所占据的面积。
由美国专利第6,207,547号(其已在简介中提及)已知引入结构化中间层于垫金属及顶部金属层之间以稳定化及保护下方的主动电路。此结果为具栅极氧化物的结构，如MOS晶体管，可被直接位于该垫金属下方。然而，此种形式的结构化中间层的制造需要特别改良及复杂的制造方法。
发明内容
所以，本发明目的为提供一种半导体结构，其允许简化的制造方法可被使用且没有关于位于该垫金属下方的半导体组件的使用的任何限制。
根据本发明，此目的可由叙述于简介中形式的集成半导体结构达到，其中，低于该垫金属表面，至少该最顶两层金属层皆具一种至少包括两相邻互连的结构。
根据本发明的一种集成半导体结构，具有：基板；至少一个位于所述基板上的半导体组件；具有表面的垫金属；位于所述垫金属和所述基板之间的多个金属层；多个绝缘层，其将所述金属层彼此分开；至少在部分所述至少一个半导体组件上延伸的所述垫金属；及，在所述垫金属的表面下方，至少最顶两层金属层均具有至少包括两相邻的互连的结构，其中，至少在所述垫金属的表面下方，所述最顶两层金属层的互连具有多个孔洞，及，其中，所述最顶两层金属层的互连彼此排列，使得在最顶层的互连的孔洞相对于在下方互连的孔洞偏位。
本发明基于阻尼及稳定化结构可由使用直接位于该垫金属下方的该顶部两金属层的合适排列(配置)而形成的发现而不需改变该集成半导体结构的制造方法，而且，本发明者发现因为此半导体结构的增加稳定性，任何形式的半导体组件可被排列于该垫金属表面下方。
与长久已知的设计相反，本发明的互连可被电利用及不仅用于增加稳定性。例如，在该垫金属下方的互连连接至在该半导体结构的一或不同的电位。该顶部金属层的互连典型上用做下方半导体组件(如晶体管)的供应线路。
依据所使用技术，金属层的数目可介于3及11之间，例如介于4及8之间的金属层目前用于0.13微米CMOS技术。
依据此垫金属的尺寸及范围，根据本发明集成半导体结构的构造提供在金属层内至少低于该垫金属表面的互连数目在2及6之间。
根据本发明，在金属层内的互连可彼此电绝缘。
在进一步发展中，在金属层内的互连可彼此电连接，而且，若有超过两互连低于该垫金属表面，在金属层内的个别互连可与其它互连彼此电绝缘，其余互连可彼此电连接。
亦可理解对已知为假结构的结构，其纯粹具稳定功能但不电连接至任何电位，被并入至少在低于该垫金属表面的小区域。然而，此设计导致电可用区域的损失。
屏蔽位于该垫金属下方的结构免于机械负荷的进一步有利结构提供互连被设计为足够宽及以宽松间隔彼此隔开。根据本发明，在互连的宽度及在互连之间的间隔的比值介于3及20，较佳为10。所以至少该顶部两金属层被设计为宽的互连以达到阻尼的效果且不需任何不必要的步骤。
在根据本发明集成半导体结构的特别有利进一步发展中，至少在该垫金属表面下方存在多个电连接该顶部金属层的互连至下方金属层的互连的贯孔，该贯孔垂直地通过在该顶部两金属层间的该绝缘层。此首先确保即使在这些金属层间发生短路(可能因机械压力的结果而发生)情况下，该半导体组件仍作用。第二，该贯孔进一步稳定化该集成半导体结构。
最适的稳定化及阻尼可由合适的贯孔资料达到，在该顶部两金属层间的相当大数目的贯孔较佳为在该垫金属表面下分布，该贯孔与另一串连排列或是相关于彼此偏位，以此方式，发生的任何压力在最大可能区域分布。
根据本发明集成半导体结构的另一特别有利发展提供该顶部两金属层的互连具多种孔洞至少低于该垫金属表面。这些孔洞以与形成该绝缘层的材料相同的材料填充，例如二氧化硅或氮化硅。此亦额外地稳定化该半导体结构。
在根据本发明集成半导体结构的另一进一步发展中，至少低于该垫金属表面的该孔洞具有的总面积为介于互连的总面积的5％和30％之间，该孔洞较佳为形成20％的互连。
根据本发明，该集成半导体结构关于所发生压力的稳定性亦由该顶部两金属层的互连增加，该顶部两金属层的互连以一种方式关于彼此排列使得在该顶部互连的孔洞关于在下方互连的孔洞偏位，此偏位装置确保高阻尼程度。
在根据本发明集成半导体结构的另一具体实施例中，该顶部金属层的互连约略一致地位于下方该金属层的互连上。
该顶部金属层的互连较佳为关于下方该金属层的互连偏位，此使得非常有效的阻尼结构形成，在此情况下在互连间的侧边偏位在其最大值，所以在此情况下金属层的两相邻互连由上方的互连部分覆盖。
集成半导体结构的进一步有利结构至少对最多部分提供金属层为由足够地硬质金属形成，此使得防止该金属层的厚度不致在机械负荷下被减少或是防止位于该金属层上方的绝缘层不致在机械负荷下被推至下方的绝缘层。
该金属典型上为铜、铝、钨、钼、银、金、铂或其合金。
在另一细节中，该垫金属表面覆盖在金属层内包含至少50％金属的区域，这些较佳为包括互连的金属区域(无孔洞)，亦包括额外引入的金属假结构。
对集成半导体结构的特别稳定结构，该金属均匀地分布于该垫金属表面下方。所以，由金属及在该互连内的孔洞及亦在相邻互连间的电连接所组成的互连较佳为均匀地分布于该垫金属表面下方。
较佳为存在顶部绝缘层于该垫金属及该顶部金属层之间，该顶部绝缘层具第一厚度D1及该顶部金属层具第二厚度D2，及该两厚度D1及D2间的比值介于1及5之间，此减少裂缝在该顶部绝缘层形成的风险及因而为下方半导体组件提供增加的保护。
根据本发明集成半导体结构的另一发展提供使该顶部绝缘层具厚度D1及使该垫金属具厚度D3，及使两厚度D1及D3间的比值介于0.5及3之间。
附图说明
本发明参考图式详细于下文说明，其中：
图1显示根据本发明集成半导体结构的示例具体实施例的截面区段，
图2以透视说明显示部分图1的该顶部两金属层的互连，
图3显示具垫金属及互连的根据本发明集成半导体结构的平面视图。
具体实施方式
该半导体结构包括具表面F及厚度D3的垫金属3(例如厚的铝层)、保护层8、基板1、半导体组件2(例如位于基板上的晶体管2，该晶体管2被排列于该垫金属3的表面F下方)、多样金属层4.x、及将该金属层4.x彼此分开的多样绝缘层5.y。为清晰目的，图1图标地说明仅第一及顶部两金属层4.1、4.x-1及4.x；依据所使用的技术而定，目前多至11个金属层4.x可被一在一上方地排列。
为形成关于该机械压力的屏蔽，其产生该集成半导体结构的连结或测试，该垫金属3及该顶部绝缘层5.y(其直接位于该垫金属3下方)皆被设计为足够厚。该绝缘层5.y较佳为具厚度D1，其为该顶部金属层4.x的厚度D2的一及五倍之间的厚度及该垫金属3的厚度D3的0.5及三倍间的厚度。
顶部两金属层4.x、4.x-1由绝缘层5.y-1彼此隔开，该贯孔6垂直地穿过此绝缘层5.y-1及电连接该顶部金属层4.x至下方的该金属层4.x-1。特别是在该垫金属3的表面F下方的区域，存在多个贯孔6于该两金属层4.x、4.x-1之间。这些结构提供该晶体管2关于发生的机械负荷的足够保护。
图2显示在直接于该垫金属的表面下方的该顶部两金属层区域的部分根据本发明集成半导体结构的透视说明。该顶部金属层的互连4.x.z及下方金属层的互连4.x-1.z皆具孔洞7.x及7.x-1。在该互连4.x.z的孔洞7.x关于下方互连4.x-1.z的孔洞7.x-1偏位排列。所以该孔洞7.x及7.x-1并非直接一位于另一上方。而且，该两互连4.x.z及4.x-1.z经由垂直运行的贯孔6彼此电连接。为确保关于压力的最大可能稳定度，尽可能多的贯孔6特别在该垫金属下方的区域排列。
当熟知本技艺者应用其专业知识及能力时可产生孔洞7.x及贯孔6的其它排列。
图3显示具垫金属3及相邻垫金属3的根据本发明集成半导体结构的平面视图。四个互连4.x.1至4.x.4存在于该垫金属3下方的区域，第五互连4.x.5存在于该垫金属3区域之外。在个别互连4.x.z之间的间隔A及它们的宽度B被清楚示出。半导体组件，如晶体管或二极管，同样地位于该垫金属3的表面F下方，但无法由图3看出。
本发明的整体结果为可得到一种合适的阻尼及稳定化结构甚至没有昂贵的方法变化或是没有要加入额外的方法特征的要求，此结构使得任何形式的电半导体组件可被排列于该垫金属表面下方且在压力情况下(如在连结或测试期间发生)不会有对这些半导体组件损伤的风险。而且，现在可能利用在该垫金属表面下方的区域于电力供应轨。
参考符号清单
1      基板
2      半导体组件，晶体管
3      垫金属
4.x    金属层
4.x.z  互连
5.y    绝缘层
6      贯孔
7.x    孔洞
8      保护层
D1     顶部绝缘层5.y的厚度
D2     顶部金属层4.x的厚度
D3     垫金属3的厚度
A      两互连4.x.z的间隔
B      互连4.x.z的宽度
F      垫金属3的表面

Claims (18)

1.一种集成半导体结构，具有：
基板(1)；
至少一个位于所述基板(1)上的半导体组件(2)；
具有表面(F)的垫金属(3)；
位于所述垫金属(3)和所述基板(1)之间的多个金属层(4.x)；
多个绝缘层(5，y)，其将所述金属层(4.x)彼此分开；
至少在部分所述至少一个半导体组件(2)上延伸的所述垫金属(3)；及
在所述垫金属(3)的表面(F)下方，至少最顶两层金属层(4.x、4.x-1)均具有至少包括两相邻的互连(4.x.z、4.x-1.z)的结构，
其中，至少在所述垫金属(3)的表面(F)下方，所述最顶两层金属层(4.x、4.x-1)的互连(4.x.z、4.x-1.z)具有多个孔洞(7.x、7.x-1)，及
其中，所述最顶两层金属层(4.x、4.x-1)的互连(4.x.z、4.x-1.z)彼此排列，使得在最顶层的互连(4.x.z)的孔洞(7.x)相对于在下方互连(4.x-1.z)的孔洞(7.x-1)偏位。
2.根据权利要求1的半导体结构，其中，在所述垫金属(3)的表面(F)下方，所述金属层(4.x)的互连(4.x.z)的数目z介于2及6之间。
3.根据上述权利要求的其中一项的半导体结构，其中，所述金属层(4.x)的互连(4.x.z)彼此电绝缘。
4.根据权利要求1或2的半导体结构，其中，所述金属层(4.x)的互连(4.x.z)彼此电连接。
5.根据权利要求1或2的半导体结构，其中，所述金属层(4.x)的互连(4.x.z)具有宽度(B)并且彼此间具有间隔(A)，所述宽度(B)和所述间隔(A)间的比值介于3及20之间。
6.根据权利要求5的半导体结构，其中，所述宽度(B)和所述间隔(A)间的比值为10。
7.根据权利要求1或2的半导体结构，其中，至少在所述垫金属(3)的表面(F)下方，存在多个电连接最顶层金属层(4.x)的互连(4.x.z)至其下方金属层(4.x-1)的互连(4.x-1.z)的贯孔(6)，所述贯孔(6)穿过所述绝缘层(5.y-1)。
8.根据权利要求1或2的半导体结构，其中，至少在所述垫金属(3)的表面(F)下方，所述孔洞(7.x及7.x-1)具有的总面积为介于所述互连(4.x.z、4.x-1.z)的总面积的5％和30％之间。
9.根据权利要求1或2的半导体结构，其中，所述孔洞(7.x、7.x-1)具有的总面积为所述互连(4.x.z、4.x-1.z)总面积的20％。
10.根据权利要求1或2的半导体结构，其中，最顶层金属层(4.x)的互连(4.x.z)一致地位于下方所述金属层(4.x-1)的互连(4.x-1.z)上方。
11.根据权利要求1或2的半导体结构，其中，最顶层金属层(4.x)的互连(4.x.z)关于下方所述金属层(4.x-1)的互连(4.x-1.z)偏位。
12.根据权利要求1或2的半导体结构，其中，所述金属层(4.x)至少大部分由硬质金属制造。
13.根据权利要求12的半导体结构，其中，所述金属包含铝、铜、钨、钼、银、金、铂或其合金。
14.根据权利要求1或2的半导体结构，其中，所述垫金属(3)表面(F)覆盖在所述金属层(4.x)内包含至少50％金属的区域。
15.根据权利要求14的半导体结构，其中，所述至少50％金属均匀地分布于所述垫金属(3)的表面(F)下方。
16.根据权利要求1或2的半导体结构，其中，顶部绝缘层(5.y)设置在所述垫金属(3)和最顶层金属层(4.x)之间，所述顶部绝缘层(5.y)具有第一厚度(D1)并且所述最顶层金属层(4.x)具有第二厚度(D2)，所述两厚度(D1、D2)间的比值介于1及5之间。
17.根据权利要求1或2的半导体结构，其中，顶部绝缘层(5.y)设置在所述垫金属(3)和最顶层金属层(4.x)之间，所述顶部绝缘层(5.y)具有第一厚度(D1)并且所述垫金属(3)具有另一个厚度(D3)，所述两厚度(D1、D3)间的比值介于0.5及3之间。
18.根据权利要求1或2的半导体结构，其中，所述金属层(4.x)的数目x介于3及11之间。
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