WO2004001762A1 - 半導体メモリ - Google Patents

半導体メモリ Download PDF

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Publication number
WO2004001762A1
WO2004001762A1 PCT/JP2003/001853 JP0301853W WO2004001762A1 WO 2004001762 A1 WO2004001762 A1 WO 2004001762A1 JP 0301853 W JP0301853 W JP 0301853W WO 2004001762 A1 WO2004001762 A1 WO 2004001762A1
Authority
WO
WIPO (PCT)
Prior art keywords
time
memory core
external access
core
predetermined time
Prior art date
Application number
PCT/JP2003/001853
Other languages
English (en)
French (fr)
Inventor
Toshikazu Nakamura
Satoshi Eto
Toshiya Miyo
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2004515472A priority Critical patent/JP4119427B2/ja
Priority to KR1020047017149A priority patent/KR100649068B1/ko
Priority to EP03705345A priority patent/EP1517332B1/en
Priority to DE60315651T priority patent/DE60315651T2/de
Publication of WO2004001762A1 publication Critical patent/WO2004001762A1/ja
Priority to US10/965,951 priority patent/US7072243B2/en
Priority to US11/215,045 priority patent/US7064998B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Storage Device Security (AREA)

Abstract

タイマは、メモリコアに読み出し動作を実行させるための外部アクセス信号を受信してから所定時間を計測し、この所定時間後にメモリコアを動作させるためのアクセス要求信号を出力する。所定時間は、メモリコアが１回動作するためのコア動作時間より長く設定されている。このため、外部アクセス信号が所定時間より短い時間で変化するとき、メモリコアは動作しない。したがって、メモリコアが正常に動作できない間隔で外部アクセス信号が供給されたときにも、メモリコアの誤動作を防止でき、メモリセルに保持されているデータが破壊することを防止できる。
PCT/JP2003/001853 2002-06-25 2003-02-20 半導体メモリ WO2004001762A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2004515472A JP4119427B2 (ja) 2002-06-25 2003-02-20 半導体メモリ
KR1020047017149A KR100649068B1 (ko) 2002-06-25 2003-02-20 반도체 메모리
EP03705345A EP1517332B1 (en) 2002-06-25 2003-02-20 Semiconductor memory
DE60315651T DE60315651T2 (de) 2002-06-25 2003-02-20 Halbleiterspeicher
US10/965,951 US7072243B2 (en) 2002-06-25 2004-10-18 Semiconductor memory
US11/215,045 US7064998B2 (en) 2002-06-25 2005-08-31 Semiconductor memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPPCT/JP02/06327 2002-06-25
PCT/JP2002/006327 WO2004001761A1 (ja) 2002-06-25 2002-06-25 半導体メモリ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/965,951 Continuation US7072243B2 (en) 2002-06-25 2004-10-18 Semiconductor memory

Publications (1)

Publication Number Publication Date
WO2004001762A1 true WO2004001762A1 (ja) 2003-12-31

Family

ID=29808141

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2002/006327 WO2004001761A1 (ja) 2002-06-25 2002-06-25 半導体メモリ
PCT/JP2003/001853 WO2004001762A1 (ja) 2002-06-25 2003-02-20 半導体メモリ

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/006327 WO2004001761A1 (ja) 2002-06-25 2002-06-25 半導体メモリ

Country Status (7)

Country Link
US (2) US7072243B2 (ja)
EP (2) EP1669999B1 (ja)
JP (1) JP4119427B2 (ja)
KR (2) KR100615414B1 (ja)
CN (4) CN101452739B (ja)
DE (2) DE60317381T2 (ja)
WO (2) WO2004001761A1 (ja)

Cited By (1)

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JP2006517712A (ja) * 2003-02-03 2006-07-27 マイクロン　テクノロジー　インコーポレイテッド 混合された非同期メモリ動作および同期メモリ動作のための検出回路

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JP2003297080A (ja) * 2002-03-29 2003-10-17 Mitsubishi Electric Corp 半導体記憶装置
US7117408B2 (en) * 2003-02-26 2006-10-03 Lsi Logic Corporation Method and system of testing data retention of memory
KR100692529B1 (ko) * 2005-07-01 2007-03-09 삼성전자주식회사 최적화된 딜레이 타임 결정 방법, 장치 및 최적화된 딜레이타임 결정 프로그램이 기록된 컴퓨터로 판독 가능한기록매체
JP4972948B2 (ja) * 2006-02-14 2012-07-11 富士通株式会社 バックボード伝送方法、バックボード伝送装置及び基板ユニット
JP2008165865A (ja) * 2006-12-27 2008-07-17 Fujitsu Ltd 半導体メモリおよび半導体メモリの動作方法
KR101163035B1 (ko) * 2009-09-04 2012-07-09 에스케이하이닉스 주식회사 데이터 라인 구동 회로
KR101046273B1 (ko) * 2010-01-29 2011-07-04 주식회사 하이닉스반도체 반도체 장치
CN102354530B (zh) * 2011-08-25 2014-08-20 西安电子科技大学 用于无源uhfrfid芯片的eeprom读取装置
JP5728370B2 (ja) * 2011-11-21 2015-06-03 株式会社東芝 半導体記憶装置およびその駆動方法
US8539146B2 (en) * 2011-11-28 2013-09-17 International Business Machines Corporation Apparatus for scheduling memory refresh operations including power states
CN102521077B (zh) * 2011-12-01 2013-12-25 广州中大微电子有限公司 一种文件防插拔写入方法及系统
CN104076263B (zh) * 2013-03-28 2017-03-15 致茂电子(苏州)有限公司 半导体自动测试设备的时间量测模块及方法
CN103325422B (zh) * 2013-07-17 2016-03-23 苏州兆芯半导体科技有限公司 Sram时序测试电路及测试方法
KR102254100B1 (ko) * 2015-01-05 2021-05-20 삼성전자주식회사 메모리 장치, 메모리 시스템 및 메모리 장치의 동작 방법
CN106158044B (zh) * 2015-04-17 2019-06-18 中芯国际集成电路制造(上海)有限公司 Sram访问时间的测试电路与测试方法
KR102393426B1 (ko) * 2015-11-10 2022-05-04 에스케이하이닉스 주식회사 반도체장치
CN109656854A (zh) * 2017-10-12 2019-04-19 光宝科技股份有限公司 固态储存装置的重置电路及其重置方法
KR102512897B1 (ko) * 2018-01-11 2023-03-23 에스케이하이닉스 주식회사 반도체 장치와 그를 포함하는 반도체 시스템
CN109741774B (zh) * 2018-11-23 2021-07-02 成都汇蓉国科微系统技术有限公司 一种基于fpga片上ram模拟实现ddr3突发的控制器以及方法

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JPH10247399A (ja) * 1997-03-03 1998-09-14 Hitachi Ltd 半導体集積回路装置
JP2002074944A (ja) * 1999-12-03 2002-03-15 Nec Corp 半導体記憶装置及びそのテスト方法
JP2002032986A (ja) * 2000-03-08 2002-01-31 Nec Corp 半導体記憶装置
JP2001332088A (ja) * 2000-03-13 2001-11-30 Nec Corp ワンショット信号発生回路
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Title
See also references of EP1517332A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006517712A (ja) * 2003-02-03 2006-07-27 マイクロン　テクノロジー　インコーポレイテッド 混合された非同期メモリ動作および同期メモリ動作のための検出回路

Also Published As

Publication number Publication date
DE60315651D1 (de) 2007-09-27
CN101452738B (zh) 2010-10-13
CN1662996A (zh) 2005-08-31
EP1517332A4 (en) 2005-09-14
CN101452738A (zh) 2009-06-10
KR20060067980A (ko) 2006-06-20
DE60317381T2 (de) 2008-04-10
EP1517332A1 (en) 2005-03-23
JP4119427B2 (ja) 2008-07-16
US7072243B2 (en) 2006-07-04
CN101452739B (zh) 2011-01-19
KR20040106389A (ko) 2004-12-17
DE60317381D1 (de) 2007-12-20
DE60315651T2 (de) 2007-11-22
KR100615414B1 (ko) 2006-08-25
CN101261877B (zh) 2010-07-28
US7064998B2 (en) 2006-06-20
US20050052941A1 (en) 2005-03-10
EP1669999A1 (en) 2006-06-14
CN100520962C (zh) 2009-07-29
EP1669999B1 (en) 2007-11-07
KR100649068B1 (ko) 2006-11-27
CN101452739A (zh) 2009-06-10
EP1517332B1 (en) 2007-08-15
JPWO2004001762A1 (ja) 2005-10-27
CN101261877A (zh) 2008-09-10
WO2004001761A1 (ja) 2003-12-31
US20060023547A1 (en) 2006-02-02

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