WO2002089204A1 - Dispositif semiconducteur - Google Patents

Dispositif semiconducteur Download PDF

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Publication number
WO2002089204A1
WO2002089204A1 PCT/JP2002/003617 JP0203617W WO02089204A1 WO 2002089204 A1 WO2002089204 A1 WO 2002089204A1 JP 0203617 W JP0203617 W JP 0203617W WO 02089204 A1 WO02089204 A1 WO 02089204A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductor
analog
digital
circuit
chip
Prior art date
Application number
PCT/JP2002/003617
Other languages
English (en)
Japanese (ja)
Inventor
Takeshi Ikeda
Hiroshi Miyagi
Original Assignee
Niigata Seimitsu Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Niigata Seimitsu Co., Ltd. filed Critical Niigata Seimitsu Co., Ltd.
Publication of WO2002089204A1 publication Critical patent/WO2002089204A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the present invention relates to a semiconductor device, and more particularly, to an analog circuit and a digital circuit.
  • ICs have been highly integrated and semiconductor elements have been miniaturized to reduce the size and weight of these terminals. Is rapidly progressing. Under these circumstances, attempts have been made to make wireless circuits including passive components such as capacitors into ICs (single chip).
  • a radio circuit for transmitting and receiving analog signals and a PLL (Phase Locked) for channel selection in radio receivers, mobile phone devices, short-range wireless data communication technology Bluetooth, wireless LAN, etc. Loop
  • a frequency synthesizer circuit digital circuit
  • a baseband signal processing circuit digital circuit
  • FIG. 1 is a top view showing a conventional example in which an IC chip in which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board (PCB).
  • PCB printed circuit board
  • reference numeral 1 denotes an IC chip, inside which an analog circuit 2 and Digital circuit 3 is mixed.
  • the internal region of the IC chip 1 is divided in the vertical direction, an analog circuit 2 is arranged in one region, and a digital circuit 3 is arranged in the other region.
  • an analog power supply line and a ground line (hereinafter, referred to as an analog power supply line) 4 are arranged along the outer periphery of the IC chip 1.
  • a digital power line and a ground line (hereinafter referred to as a digital power line) 5 are wired around the digital circuit 3 along the outer periphery of the IC chip 1.
  • the IC chip 1 configured as described above is mounted on a conductor 200 provided on the surface of the printed circuit board 100, and is electrically connected by wire bonding or soldering.
  • FIG. 2 is a cross-sectional view showing a conventional example in which an IC chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
  • the IC chip 1 has an analog circuit 2 formed by integrating various elements including a MOS transistor 7 on a silicon substrate 6.
  • various elements including the MOS transistor 8 and the like are integrated on the same silicon substrate 6 to form the digital circuit 3.
  • an analog power supply line 4 of FIG. 1 including an analog ground line 9 and a power supply line (not shown) is wired.
  • a digital power line 5 of FIG. 1 including a digital ground line 10 and a power line (not shown) is provided around the digital circuit 3.
  • the IC chip 1 having such a configuration is mounted on a conductor 200 provided on the surface of the printed circuit board 100, and is electrically connected by wire pond or soldering.
  • the analog ground line 9 and the digital ground line 10 are connected to the conductor 200 of the printed circuit board 100.
  • the conductor portion 200 is optional. (For example, a position near either the analog ground line 9 or the digital ground line 10).
  • the analog circuit 2 and the digital circuit 3 are grounded.
  • a substrate such as the silicon substrate 6 has a resistance.
  • the analog circuit 2 and the digital circuit 3 and the printed circuit board 100 A potential difference is generated in the substrate itself between the substrate and the ground portion, and a current flows to the ground portion of the printed circuit board 100 through the substrate.
  • the present invention has been made in order to solve such a problem.
  • a semiconductor chip in which an analog circuit and a digital circuit are mixed, the current from the analog circuit and the current from the digital circuit are suppressed.
  • the purpose is to prevent the inconvenience of mixing in by flowing through a tray, etc., and to reduce noise for analog or digital signals.
  • a semiconductor device of the present invention is a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board, wherein the conductor of the printed circuit board is a first conductor and By the second conductor Wherein the semiconductor chip is mounted on the first conductor portion and the second conductor portion.
  • the semiconductor chip is mounted such that the analog circuit is disposed on the first conductor, and the digital circuit is disposed on the second conductor.
  • the first conductor and the second conductor are separately grounded.
  • Another aspect of the present invention is characterized in that the first conductor and the second conductor are commonly grounded.
  • a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
  • a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a lead frame. It is characterized by comprising a conductor portion and a second conductor portion, and mounting the semiconductor chip on the first conductor portion and the second conductor portion.
  • the present invention comprises the above technical means, in a semiconductor chip in which an analog circuit and a digital circuit are mixed, the current generated from the analog circuit based on the potential difference in the substrate is transmitted from the first conductor to the ground through the substrate. Flows into On the other hand, the current generated from the digital circuit flows from the second conductor to the ground through the substrate. This allows the current from the analog circuit and the power from the digital circuit The inconvenience that the flow and the flow are mixed through the substrate is prevented.
  • FIG. 1 is a top view showing a conventional example in which an IC chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
  • FIG. 2 is a cross-sectional view showing a conventional example in which an IC chip in which analog circuits and digital circuits are mixed is mounted on a printed circuit board.
  • FIG. 3 is a top view showing the configuration of an IC chip implementing the semiconductor device of the present invention and an example of mounting the IC chip on a printed circuit board.
  • FIG. 4 is a cross-sectional view showing a configuration of an IC chip in which the semiconductor device of the present invention is implemented, and an example of mounting on a printed circuit board.
  • FIG. 3 is a top view showing a configuration example of a semiconductor chip (IC chip) embodying the semiconductor device of the present invention mounted on a printed circuit board.
  • IC chip semiconductor chip
  • the IC chip 1 of the present embodiment includes an analog circuit 2 for processing an analog signal and a digital circuit 3 for processing a digital signal.
  • the internal area of the IC chip 1 is divided in the vertical direction, the analog circuit 2 is arranged in one area, and the digital circuit 3 is arranged in the other area.
  • An analog power supply line 4 (an analog power supply line and a ground line) is wired around the analog circuit 2 along the outer periphery of the IC chip 1.
  • a digital power supply line 5 (digital power supply line and ground line) is wired around the digital circuit 3 along the outer periphery of the IC chip 1.
  • a first conductor section 11 and a second conductor section 12 are provided as conductor sections of a printed circuit board 20 on which the IC chip 1 configured as described above is mounted.
  • the first and second conductor portions 11 and 12 are formed, for example, by providing a slit 21 in the conductor portion of the printed circuit board 20 and dividing the conductor portion into two regions.
  • the IC chip 1 is mounted on the two conductors 11 and 12 so as to straddle them, and is electrically connected to the conductors 11 and 12 by wire bonding or soldering. At this time, the IC chip 1 is preferably mounted at a position where the analog circuit 2 comes above the first conductor 11 and the digital circuit 3 comes above the second conductor 12.
  • FIG. 4 is a cross-sectional view showing the configuration of the IC chip according to the present embodiment and an example of mounting the IC chip on a printed circuit board.
  • an analog circuit 2 is formed by integrating various elements including a MOS transistor 7 on a silicon substrate 6 of an IC chip 1.
  • various elements including a MOS transistor 8 and the like are integrated on the same silicon substrate 6 to form a digital circuit 3.
  • an analog power supply line 4 of FIG. 3 including an analog ground line 9 and a power supply line (not shown) is wired.
  • a digital power line 5 of FIG. 3 including a digital ground line 10 and a power line (not shown) is wired.
  • the IC chip 1 having such a configuration is mounted on the surface of the two conductors 11 and 12 so as to straddle them, and is electrically connected by wire pond or soldering.
  • the analog ground wire 9 is connected to the first conductor portion 11 by, for example, a bonding wire 13
  • the digital ground wire 10 is connected to the second conductor portion 12 by, for example, a bonding wire 14.
  • the current from the analog circuit 2 generated by the potential difference of the silicon substrate 6 flows into the first conductor 11 through the silicon substrate 6, and further flows to the common ground. Further, the current from the digital circuit 3 flows into the second conductor section 12 through the silicon substrate 6, and further flows to the common ground.
  • the conductor of the printed circuit board 20 is divided into two (the first conductor 11 and the second conductor 12).
  • the number of divisions may be more.
  • the conductor of the printed circuit board 20 may be divided into three or more regions in accordance with the division. .
  • first conductor portion and the second conductor portion referred to in the present invention mean, for example, areas respectively corresponding to an analog circuit and a digital circuit, and include the first conductor portion and the second conductor portion. 2 conductor parts themselves Area may be divided. .
  • the present invention is not limited to this.
  • the present invention can be similarly applied to a case where an IC chip is mounted on a lead frame.
  • a current generated from the analog circuit flows from the first conductor through the substrate to the first conductor.
  • the current generated by the digital circuit can flow through the substrate, and can flow from the second conductor portion to the ground through the substrate.
  • the present invention provides an analog-to-digital converter that prevents the inconvenience of current from an analog circuit and current from a digital circuit flowing through a subrate or the like and being mixed, thereby reducing noise with respect to an analog signal or a digital signal. Useful for mixed chips.

Abstract

L'invention concerne un microcircuit intégré (1) monté chevauchant sur une première partie conductrice (11) et une deuxième partie conductrice (12) d'une carte de circuits imprimés (20). Ces parties conductrices (11, 12) sont mises à la terre de sorte que le courant provenant d'un circuit analogique (2) basé sur une différence de potentiel créée dans le substrat silicium (6) du microcircuit intégré (1) passe de la première partie conductrice (11), à travers le substrat silicium (6), jusqu'à la terre, et que le courant provenant d'un circuit numérique (3) passe de la deuxième partie conductrice (12), à travers le substrat silicium (6), jusqu'à la terre. Le courant provenant du circuit analogique (2) et le courant provenant du circuit numérique (3) ne peuvent ainsi pas se mélanger à travers le substrat silicium (6).
PCT/JP2002/003617 2001-04-16 2002-04-11 Dispositif semiconducteur WO2002089204A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-116416 2001-04-16
JP2001116416A JP2002313980A (ja) 2001-04-16 2001-04-16 半導体装置

Publications (1)

Publication Number Publication Date
WO2002089204A1 true WO2002089204A1 (fr) 2002-11-07

Family

ID=18967153

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/003617 WO2002089204A1 (fr) 2001-04-16 2002-04-11 Dispositif semiconducteur

Country Status (2)

Country Link
JP (1) JP2002313980A (fr)
WO (1) WO2002089204A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1639862A (zh) * 2002-07-24 2005-07-13 三菱电机株式会社 半导体器件
JP2005340741A (ja) * 2004-05-31 2005-12-08 Renesas Technology Corp 半導体装置
JP4744111B2 (ja) * 2004-07-30 2011-08-10 株式会社平和 遊技機用回路基板、遊技機及び回胴式遊技機
KR100817070B1 (ko) 2006-10-30 2008-03-26 삼성전자주식회사 다중 그라운드 쉴딩 반도체 패키지, 그 패키지의 제조방법 및 그 그라운드 쉴딩을 이용한 노이즈 방지방법
JP6323643B2 (ja) 2013-11-07 2018-05-16 セイコーエプソン株式会社 半導体回路装置、発振器、電子機器及び移動体

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996006460A1 (fr) * 1994-08-19 1996-02-29 Hitachi, Ltd. Dispositif semi-conducteur
JPH09199818A (ja) * 1996-01-12 1997-07-31 Canon Inc グランド間接続構造
JPH09223705A (ja) * 1996-02-15 1997-08-26 Hitachi Ltd 半導体装置
JPH11121643A (ja) * 1997-10-09 1999-04-30 Hitachi Ltd 半導体装置
JP2000223613A (ja) * 1999-01-28 2000-08-11 Citizen Watch Co Ltd 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996006460A1 (fr) * 1994-08-19 1996-02-29 Hitachi, Ltd. Dispositif semi-conducteur
JPH09199818A (ja) * 1996-01-12 1997-07-31 Canon Inc グランド間接続構造
JPH09223705A (ja) * 1996-02-15 1997-08-26 Hitachi Ltd 半導体装置
JPH11121643A (ja) * 1997-10-09 1999-04-30 Hitachi Ltd 半導体装置
JP2000223613A (ja) * 1999-01-28 2000-08-11 Citizen Watch Co Ltd 半導体装置

Also Published As

Publication number Publication date
JP2002313980A (ja) 2002-10-25

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