CN1639862A - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN1639862A
CN1639862A CNA028293673A CN02829367A CN1639862A CN 1639862 A CN1639862 A CN 1639862A CN A028293673 A CNA028293673 A CN A028293673A CN 02829367 A CN02829367 A CN 02829367A CN 1639862 A CN1639862 A CN 1639862A
Authority
CN
China
Prior art keywords
earth terminal
functional block
semiconductor device
signal
signal end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA028293673A
Other languages
English (en)
Inventor
二宫圭治
伊东健治
上马弘敬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN1639862A publication Critical patent/CN1639862A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48253—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及半导体器件，特别是具有接地端、以及配置在其周边的多个信号端的半导体器件，其目的在于提供提高其性能的技术。为了达到上述目的，使得与功能块(11)连接的接地端(5、35)和与功能块(12)连接的接地端(6、36)分离。因此，对某一功能块通过接地端供给的接地电位不随流过另一功能块的电流大小而变化。其结果，各功能块的性能提高，半导体器件的性能提高。

Description

半导体器件
技术领域
本发明涉及半导体器件，特别涉及具有接地端、以及配置在其周边多个信号端的半导体器件。
背景技术
图11所示为以往的半导体器件101的结构平面图，是表示从前底面来看时的外形。另外，图12所示为以往的半导体器件101的构成方框图，为了简单起见，省略了图11所示的电源端107及信号端104的图示。
如图11及12所示，以往的半导体器件101具有由多个功能构成的半导体集成电路110、放置该半导体集成电路110的管壳102、以及从管壳102外露的1个接地端105和多个信号端104和电源端107。
半导体集成电路110具有例如是数字电路的功能块111、以及例如是模拟电路的功能块112。在功能块111中设置供给成为其动作基准的接地电位的电极(以后称为“电极111a”)，在功能块112中设置供给成为其动作基准的接地电位的电极(以后称为“电极112a”)。
管壳102由形成半导体器件101外形106的模铸树脂103构成。该模铸树脂103使接地端105、电源端107及信号端104露出，并将接地端105、电源端107及信号端104封装。
接地端105、电源端107及信号端104设置在管壳102的底面，电源端107及信号端104配置在接地端105的周边。如图12所示，接地端105在管壳102的内部与上述电极111a及电极112a电气连接，从半导体器件101地外部向接地端105供给接地电位120。通过这样，接地端105与各功能块111及112电气连接，对各功能块111集112通过接地端105供给成为它们动作基准的接地电位。
信号端104在图12中虽未示出，但在管壳102的内部与功能块111或功能块112电气连接。对与功能块111连接的某信号端104，从半导体器件101的外部供给例如成为数字电路动作基准的时钟信号或其它输入信号，其结果来自外部的输入信号供给功能块111。另外，对与功能块111连接的其它信号端104，供给来自功能块111的输出信号。通过这样，半导体器件101的外部器件能够接受来自功能块111的输出信号。
对与功能块112连接的某信号端114，从半导体器件101的外部供给例如用天线(未图示)接收到高频信号，其结果该高频信号供给功能块112。另外，对与功能块112连接的其它信号端104，供给来自功能块112的输出信号。另外，以后有的情况下，将从半导体器件101地外部供给信号的信号端101称为“输入信号端104”，将供给来自功能块111或112多输出信号的信号端104称为“输出信号端104”。
电源端107在图12中虽未图示，但在管壳102的内部与功能块111及功能块112电气连接，从半导体器件101的外部供给半导体集成电路110动作用的所必需的电源、例如正电位。通过这样，对各功能块111及112通过电源端107供给电源，各功能块111及112以通过接地端105供给的接地电位为基准进行动作。
若半导体集成电路110动作，则对功能块111及112分别流过电流I111及I112。这些电流I111及I112从电源端107、输入信号端104或输出信号端104流向接地端105。
若电流I111及I112流向接地端105，则由于接地端105的电阻及电感等阻抗115的作用，在从半导体器件101的外部供给接地端105的接地电位120、与实际供给电极111a及112a的接地电位之间产生电位差。由于电流I111及I112的两个电流流向接地端105，因此该电位差随各电流I111及I112的大小而变化。即，供给功能块111及112的某一功能块的接地电位不仅随自己本身流过的电流大小而变化也随流过另一功能块的电流大小而变化。因而，有的情况下某一功能块的性能随流过另一功能块的电流大小而恶化，通过这样作为整个半导体器件101的性能就恶化。
发明内容
本发明正是为了解决上述那样的问题而进行的，其目的在于提供提高半导体器件性能的技术。
本发明有关的半导体器件的第1方面，是包括具有第1功能块及第2功能块的半导体集成电路、放置所述半导体集成电路的管壳、以及从所述管壳外露的接地端和信号端，所述接地端包含互相分离的第1及第2接地端，所述信号端包含配置在所述接地端周围的多个第1信号端，所述第1接地端与所述第1功能块电气连接，所述第2接地端与所述第2功能块电气连接。
本发明有关的半导体器件的第2方面，是所述第2接地端包围所述第1接地端。
本发明有关的半导体器件的第3方面，是所述信号端还包含第2信号端，前述第2接地端也包围所述第2信号端。
根据本发明有关的半导体器件的第1方面，由于与第1功能块连接的第1接地端和与第2功能块连接的第2接地端分离，因此对某一功能块通过接地端供给的接地电位不随流过另一功能块的电流大小而变动。其结果，第1及第2功能块的各自的性能提高，半导体器件的性能提高。
根据本发明有关的半导体器件的第2方面，由于第2接地端包围第1接地端，因此第1接地端的电位不容易受到第1信号端的电位变化的影响。
根据本发明有关的半导体器件的第3方面，由于第2接地端也包围第2信号端，因此不仅第1接地端的电位，而且第2信号端的电位也不容易受到第1信号端的电位变化的影响。
根据以下的详细说明及附图，将更明白本发明的目的、特性、方面及优点。
附图说明
图1所示为本发明实施形态1有关的半导体器件的结构平面图。
图2所示为本发明实施形态1有关的半导体器件的构成方框图。
图3所示为本发明实施形态1有关的半导体器件的结构平面图。
图4所示为本发明实施形态1有关的半导体器件的结构剖面图。
图5所示为本发明实施形态2有关的半导体器件的结构平面图。
图6所示为本发明实施形态2有关的半导体器件的结构平面图。
图7所示为本发明实施形态2有关的半导体器件的结构剖面图。
图8所示为本发明实施形态3有关的半导体器件的结构平面图。
图9所示为本发明实施形态3有关的半导体器件的结构平面图。
图10所示为本发明实施形态3有关的半导体器件的结构剖面图。
图11所示为以往的半导体器件的结构平面图。
图12所示为以往的半导体器件的构成方框图。
具体实施方式
1.实施形态1
图1及图3所示为本发明实施形态1有关的半导体器件1的结构平面图，图4为图3所示的箭头III-III方向的剖面图。图1所示为从底面来看时的外形，图3所示为从上面来看时的内部结构。另外，在图3中，由于是表示半导体器件1的内部结构，因此省略图1所示的模铸树脂3的图示，用虚线表示半导体器件1的外形7。
另外，图2所示为本实施形态1有关的半导体器件1的构成方框图，为了简单起见，省略了图1所示的电源端8及信号端4的图示。
如图1～图4所示，实施形态1有关的半导体器件1包括具有多个功能块的半导体集成电路10、放置该半导体集成电路10的管壳2、以及从管壳2外露的接地端66和多个信号端4和1个电源端8。
半导体集成电路10形成在半导体芯片21上，例如具有2个功能块11及12。功能块11例如用数字电路构成，功能块12例如用模拟电路构成。具体来说，例如在将实施形态1有关的半导体器件1用于数字调制信号的接收机时，功能块12用包含从接收信号取出希望信号的滤波器电路、以及将该滤波器电路的输出放大的放大器电路等的模拟电路构成，功能块11用包含对解调的数字信号进行纠错等解码器等的数字电路构成。
如图3所示，在半导体芯片21的上表面，在形成功能块11的区域(未图示)内，设置供给成为功能块11的动作基准的接地电位的电极25，在形成功能块12的区域(未图示)内，设置供给成为功能块12的动作基准的接地电位的电极26。另外，如图4所示，半导体芯片21用其下表面与绝缘基板22接合。绝缘基板22例如是玻璃环氧基板或特氟纶基板。
如图1所示，半导体器件1的管壳2由形成半导体器件1的外形7的模铸树脂3构成。接地端16由互相分离的接地端5及6构成，该接地端5与6互相相邻配置。另外，接地端16、电源端8及信号端4设置在管壳2的底面，电源端8及信号端4配置在接地端16的周边。
如图3及图4所示，与半导体芯片21接合的绝缘基板22在相对于半导体芯片21的相反侧与各接地端5及6接合。即，在接地端5及6上，依次载有绝缘基板22及半导体芯片21。
各接地端5及6例如是由金属制成的四边形薄板。如图2～图4所示，接地端5及6在管壳2的内部用铝线23分别与半导体芯片21的电极25及26接合。通过这样，接地端5与功能块11电气连接，接地端6与功能块12电气连接。
如图2所示，对各接地端5及6从半导体器件的外部供给接地电位，其结果对各功能块11及12供给成为它们动作基准的接地电位。
信号端4例如是由金属制成的四边形的薄板。在图2～图4中虽未图示，但在半导体芯片21的上表面的周边设置供给来自功能块11及12的输出信号的电极、或者将来自半导体器件1的外部的信号供给功能块11及12用的电极。另外，信号端4用铝线与该电极电气连接。通过这样，信号端4在管壳2的内部与功能块11或功能块12电气连接。
对与功能块1连接的某信号端4，从半导体器件1的外部供给例如成为数字电路动作基准的时钟信号或其它输入信号，其结果来自外部的输入信号供给功能块11。另外，对与功能块11连接的其它信号端4，供给来自功能块11的输出信号。通过这样，半导体器件1的外部器件能够接受来自功能块1的输出信号。
对与功能块12连接的某信号端4，从半导体器件1的外部供给例如用天线(示图示)接收的高频信号，其结果该高频信号供给功能块12。另外，对与功能块12连接的其它信号端4，供给来自功能块12的输出信号。另外，以后有的情况下，将从半导体器件1的外部供给信号的信号端4称为“输入信号端4”，将供给来自功能块111或112的输出信号的信号端4称为“输出信号端4”。
电源端8例如是由金属制成的四边形的薄板。在图2～图4中虽未图示，但在半导体芯片21的上表面设置从半导体器件1的外部向功能块11及12供给电源用的电极。另外，电源端8用铝线与该电极电气连接。通过这样，电源端8在管壳2的内部与功能块11及功能块12电气连接。
对电源端8从半导体器件1的外部供给半导体集成电路10动作用的所必需的电源、例如正电位。其结果，对各功能块11及12通过电源端7供给电源。通过这样，功能块11以通过接地端5供给的接地电压为基准进行动作，功能块12以通过接地端6供给的接地电压为基准进行动作。
如图1及图4所示，模铸树脂3使接地端5及6、电源端8及信号端4外露，并将半导体芯片21、绝缘基板22、接地端5及6、电源端8、信号端4及铝线23封装。
如上所述，若从半导体器件1的外部对半导体集成电路10供给电源，开始动作，则对功能块11及12分别流过电流I11及I12。流过功能块11的电流I11从电源端8、输入信号端4或输出信号端4流向接地端5。另外，流过功能块12的电流I12从电源端8、输入信号端4或输出信号端4流向接地端6。
由于接地端5与接地端6分离，因此电流I11不流向接地端6，电流I12不流向接地端5。所以在电流流向接地端5，由于接地端5的阻抗5a的作用，而在从半导体器件1的外部供给接地端5的接地电位20、与实际供给电极25的接地电位之间产生电位差时，该电位差不随电流I12的大小而变化。同时，在电流流向接地端6，由于接地端6的阻抗6a的作用，而在从半导体器件1的外部供给接端6的接地电位20、与实际供给电极26的接地电位之间产生电位差时，该电位差不随电流I11的大小而变化。
因而，对功能块11及12的某一功能块供给的接地电位仅随流过自己本身的电流大小而变化，而不受流过另一功能块的电流大小的影响。
这样，根据本实施形态1有关的半导体器件1，由于半导体集成电路10的每个功能块的接地端是分离的，因此与上述以往的半导体器件101不同，对某一功能块通过接地端供给的接地电位不随流过除此以外的功能块的电流大小而变化。其结果，各功能块的性能提高，因而，本实施形态1有关的半导体器件1的性能比以往的半导体器件101要提高。
2.实施形态2
图5及图6所示为本发明实施形态2有关的半导体器件31的结构平面图，图7为图6所示的箭头VI-VI方向的剖面图。图5所示为从底面来看时的外形，图6所示为从上面来看时的内部结构。另外，在图6中，由于是表示半导体器件31的内部结构，因此省略图5所示的模铸树脂33的图示，用虚线表示半导体器件31的外形37。
本实施形态2有关的半导体器件31是在上述实施形态1有关的半导体器件1中，基本上是改变接地端5及6的形状的半导体器件。
本实施形态2有关的半导体器件31包括上述的半导体集成电路10、放置该半导体集成电路10的管壳32、以及从管壳32外露的接地端66和信号端4和电源端8。
半导体器件31的管壳32如图5所示，由形成半导体器件31的外形37的模铸树脂33构成，接地端66由互相分离的接地端35及36构成。另外，接地端66、电源端8及信号端4设置在管壳32的底面。
接地端35是实施形态1有关的接地端5的形状的变形，例如是近似正方形的薄板。接地端36是实施形态1有关的接地端6的形状的变形，例如是方框形的薄板。而且，接地端36包围接地端35，电源端8及信号端4配置在接地端66的周边。
如图6及图7所示，与半导体芯片21接合的绝缘基板42在相对于半导体芯片21的相反侧与各接地端35接合。即，在接地端35上，依次载有绝缘基板42及半导体芯片21。另外绝缘基板42例如是玻璃环氧基板或特氟纶基板。
如图6及图7所示，接地端35及36在管壳2的内部用铝线43分别与半导体芯片21的电极25及26接合。通过这样，接地端35与功能块11电气连接，接地端36与功能块12电气连接。另外，由于绝缘基板42的大小比接地端35的大小要小，因此能够用铝线43连接在半导体巨芯片21的上表面上形成的电极26与接地端35。
模铸树脂33如图5及7所示，使接地端66、电源端8及信号端4外露，并将半导体芯片21、绝缘基板42、接地端66、电源端8、信号端4及铝线43封装。本实施形态2有关的半导体器件31的其它结构，由于与上述实施形态1有关的半导体器件1相同，因此其说明省略。
这样，在本实施形态2有关的半导体器件31中，接地端36包围接地端35。因而，接地端35的电位不容易受信号端4的电位变化的影响。
在实施形态1有关的半导体器件1中，接地端5及6都是四边形，仅仅单纯互相相邻配置。因此，若在信号端4有例如数+MHz的时钟信号输入，以因该信号端4的电位变化，往往接地端5及6的一端或两端的电位发生变化。因此，有时与电位变化的接地端连接的功能块的性能变化。
在本实施形态2中，由于一个接地端包围另一个接地端，因此至少能够减少因信号端4的电位变化而引起的该另一个接地端的电位变化。其结果，与上述的实施形态1有关的半导体器件1相比，半导体器件32的性能更进一步提高。
3.实施形态3
图8及图9所示为本发明实施形态3有关的半导体器件51的结构平面图，图10为图9所示的箭头IX-IX方向的剖面图。图8所示为从底面来看时的外形，图9所示为从上面来看时的内部结构。另外，在图9中，由于是表示半导体器件51的内部结构，因此省略图8所示的模铸树脂53的图示，用虚线表示半导体器件51的外形57。
本实施形态3有关的半导体器件51是在上述实施形态2有关的半导体器件31中，再设置信号端，接地端36还包围该信号端。
本实施形态3有关的半导体器件51包括上述的半导体集成电路10、放置该半导体集成电路10的管壳52、以及从管壳52外露的接地端66和信号端4及54和电源端8。管壳52如图8所示，由形成半导体器件51的外形57的模铸树脂53构成。
信号端54设置多个，例如是由金属制成的四边形的薄板。另外，与信号端4相同，在管壳2的内部与功能块11或功能块12电气连接。具体来说，如实施形态1中所述，在半导体芯片21的上表面周边设置供给来自功能块11及12的输出信号的电极(未图示)、或从半导体器件1的外部将信号输入功能块11及12用的电极(未图示)。管壳52的信号端54用铝线与这些电极的一部分电气连接。
对于与功能块11或12连接的信号端54，是从半导体器件51的外部供给输入信号，或者供给来自功能块11或12的输出信号。通过这样，来自外部器件的信号能够供给功能块11或12，或者外部的器件能够接受来自功能块11或12的输出信号。
接地端66、电源端8、信号端4及54设置在管壳52的底面，接地端36包围接地端35及信号端54。
模铸树脂53如图8及图10所示，使接地端66、电源端8、信号端4及54外露，并将半导体芯片21、绝缘基板42、接地端66、电源端8、信号端4及45、以及铝线43封装。本实施形态3有关的半导体器件51及其结构，由于与上述实施形态2有关的半导体器件31相同，因此其说明省略。
这样，根据本实施形态3有关的半导体器件51，由于接地端36也包围信号端54，因此不仅接地端35的电位，而且信号端54的电位，也不容易受信号端4的电位变化的影响。
在上述实施形态2有关的半导体器件31中，例如在对互相相邻的信号端4的一信号端供给数+MHz的时钟信号，而对另一信号端输入信号电平非常小的模拟信号、例如用天线接收的微弱无线信号时，因时钟信号输入的信号端4的电位变化，往往无线信号输入的信号端4的电位发生变化。从而，无线信号输入的功能块12往往不能适当处理该无线信号。
在本实施形态3中，由于设置了被接地端36包围的信号端54，因此将上述那样抗干扰能力弱的信号分配给该信号端54，通过这样能够在半导体器件51内部或外部改善其信号因信号端4的电位变化而不能适当处理的问题。其结果，与上述实施形态2有关的半导体器件31相比，其性能更进一步提高。
另外，在上述实施形态1～3中，对半导体集成电路10供给电源用的电源端8是1个，但也可以在接地端的周边设置多个。
另外，对于半导体集成电路10具有的功能块11及12，说明的是采用数字电路及模拟电路的情况，但也可以采用具有其它功能的功能块。例如，在将上述半导体器件1、31及51用于超外差式接收机时，也可以作为功能块11是采用处理RF(Radio Frequency，射频)信号的电路，作为功能块12是采用处理IF(Intermediate Frequency，中频)信号的电路。
作为处理RF信号的电路的具体例子，包含从输入至信号端4或信号端54的RF信号取出希望信号的滤波器电路、将该滤波器电路的输出放大的放大器电路、以及将RF信号变换为IF信号的频率变换电路等。另外，作为处理IF信号的电路的具体例子，包含将从处理RF信号的电路输出的IF信号进行滤波的滤波器电路、将该滤波器电路的输出放大的放大器电路、以及将IF信号解调后取出声音信号等的解调器等。
另外，也可从对功能块11采用流过数+mA至数百mA的比较大的电流的电路，对功能块12采用流过数μA～数+μA的比较小的电流的电路。作为流过比较大的电流的电路，例如有扬声器放大器电路等，作为流过比较小的电流的电路，有上述的处理RF信号的电路等。
另外，上述的实施形态1～3中，半导体集成电路10具有2个功能块11及12，但也可以具有3个及3个以上的功能块。例如，也可以具有2个用模拟电路构成的功能块，具有1个用数字电路构成的功能块。在这种情况下，对每个功能块将管壳的接地端分离，通过这样各功能块的性能提高，其结果半导体器件的性能提高。
以上虽对本发明作了详细说明，但上述的说明在所有的方面都是表示例子，本发明不限定于此。未例示的无数变形例可以理解为不超出本发明范围的能够设想到的例子。

Claims (3)

1.一种半导体器件，其特征在于，包括
具有第1功能块及第2功能块的半导体集成电路、
放置所述半导体集成电路的管壳、以及
从所述管壳外露的接地端和信号端，
所述接地端包含互相分离的第1及第2接地端，
所述信号端包含配置在所述接地端周围的多个第1信号端，
所述第1接地端与所述第1功能块电气连接，
所述第2接地端与所述第2功能块电气连接。
2.如权利要求1所述的半导体器件，其特征在于，
所述第2接地端包围所述第1接地端。
3.如权利要求2所述的半导体器件，其特征在于，
所述信号端还包含第2信号端，
所述第2接地端也包围所述第2信号端。
CNA028293673A 2002-07-24 2002-07-24 半导体器件 Pending CN1639862A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2002/007513 WO2004010497A1 (ja) 2002-07-24 2002-07-24 半導体装置

Publications (1)

Publication Number Publication Date
CN1639862A true CN1639862A (zh) 2005-07-13

Family

ID=30490775

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA028293673A Pending CN1639862A (zh) 2002-07-24 2002-07-24 半导体器件

Country Status (5)

Country Link
US (1) US20050161798A1 (zh)
EP (1) EP1524689A1 (zh)
JP (1) JP4004500B2 (zh)
CN (1) CN1639862A (zh)
WO (1) WO2004010497A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340741A (ja) * 2004-05-31 2005-12-08 Renesas Technology Corp 半導体装置
JP2009212211A (ja) * 2008-03-03 2009-09-17 Rohm Co Ltd 半導体装置
JP5352551B2 (ja) * 2010-09-07 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置
US9070700B2 (en) * 2011-11-04 2015-06-30 Broadcom Corporation Apparatus for electrostatic discharge protection and noise suppression in circuits
WO2013140886A1 (ja) * 2012-03-22 2013-09-26 株式会社 村田製作所 半導体装置および半導体モジュール

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545923A (en) * 1993-10-22 1996-08-13 Lsi Logic Corporation Semiconductor device assembly with minimized bond finger connections
JPH07312404A (ja) * 1994-05-18 1995-11-28 Hitachi Ltd 樹脂封止型半導体装置
JP3449099B2 (ja) * 1996-02-15 2003-09-22 株式会社日立製作所 半導体装置
JP3947292B2 (ja) * 1998-02-10 2007-07-18 大日本印刷株式会社 樹脂封止型半導体装置の製造方法
US6025640A (en) * 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
EP0895287A3 (en) * 1997-07-31 2006-04-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and lead frame for the same
US5903050A (en) * 1998-04-30 1999-05-11 Lsi Logic Corporation Semiconductor package having capacitive extension spokes and method for making the same
US6539531B2 (en) * 1999-02-25 2003-03-25 Formfactor, Inc. Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes
US6208190B1 (en) * 1999-05-27 2001-03-27 Lucent Technologies Inc. Minimizing effects of switching noise in mixed signal chips
JP2002076228A (ja) * 2000-09-04 2002-03-15 Dainippon Printing Co Ltd 樹脂封止型半導体装置
US6867493B2 (en) * 2000-11-15 2005-03-15 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless multi-die carrier
JP2002313980A (ja) * 2001-04-16 2002-10-25 Niigata Seimitsu Kk 半導体装置
JP2003324151A (ja) * 2002-04-26 2003-11-14 Toshiba Microelectronics Corp 半導体集積回路装置、実装基板装置、及び実装基板装置の配線切断方法
US6818973B1 (en) * 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6927483B1 (en) * 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement

Also Published As

Publication number Publication date
WO2004010497A1 (ja) 2004-01-29
JP4004500B2 (ja) 2007-11-07
JPWO2004010497A1 (ja) 2005-11-17
US20050161798A1 (en) 2005-07-28
EP1524689A1 (en) 2005-04-20

Similar Documents

Publication Publication Date Title
CN1113584C (zh) 印刷电路板装置
CN1187894C (zh) 多级放大器
CN1082281C (zh) 携带式无线电收发机
CN1134105C (zh) 适合倒装片安装的表面声波器件
CN1094271C (zh) 通信用无线电装置的收发信电路及半导体集成电路装置
CN1188005C (zh) 半导体集成转换电路
CN1577853A (zh) 高频功率放大器模块及半导体集成电路器件
CN1941641A (zh) 信号接收装置
CN1466800A (zh) 用于移动无线设备的天线
CN1839554A (zh) 射频电路模块
CN1705123A (zh) 一种半导体器件
CN1624905A (zh) 固态成像装置、布线衬底和制造该衬底的方法
CN1276543C (zh) 匹配器
CN1372381A (zh) 开关电路装置
CN1930786A (zh) 接收电路和使用该接收电路的接收装置及收发装置
CN1639862A (zh) 半导体器件
CN1914800A (zh) 表面安装型saw元件
CN100351633C (zh) 用于测试电子器件的方法和装置
CN1669230A (zh) 使用可通过深n阱CMOS技术获得的纵向双极结型晶体管的直接转换接收器
CN1969486A (zh) 用于在电子设备的音频信号路径中进行接口并且抑制esd和无线电信号的无源处理设备
CN1619957A (zh) 表面声波滤波器和采用该表面声波滤波器的无线设备
CN1235396C (zh) 高频信号传输装置及使用它的电子调谐器
CN1115060C (zh) 能够提高接收率的无线选呼接收机
CN1586024A (zh) 天线装置
CN1604465A (zh) 发射极接地电路、以及使用该电路的高频接收设备和高频发送设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication