WO2002089204A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2002089204A1
WO2002089204A1 PCT/JP2002/003617 JP0203617W WO02089204A1 WO 2002089204 A1 WO2002089204 A1 WO 2002089204A1 JP 0203617 W JP0203617 W JP 0203617W WO 02089204 A1 WO02089204 A1 WO 02089204A1
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Prior art keywords
conductor
analog
digital
circuit
chip
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PCT/JP2002/003617
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French (fr)
Japanese (ja)
Inventor
Takeshi Ikeda
Hiroshi Miyagi
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Niigata Seimitsu Co., Ltd.
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Publication of WO2002089204A1 publication Critical patent/WO2002089204A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the present invention relates to a semiconductor device, and more particularly, to an analog circuit and a digital circuit.
  • ICs have been highly integrated and semiconductor elements have been miniaturized to reduce the size and weight of these terminals. Is rapidly progressing. Under these circumstances, attempts have been made to make wireless circuits including passive components such as capacitors into ICs (single chip).
  • a radio circuit for transmitting and receiving analog signals and a PLL (Phase Locked) for channel selection in radio receivers, mobile phone devices, short-range wireless data communication technology Bluetooth, wireless LAN, etc. Loop
  • a frequency synthesizer circuit digital circuit
  • a baseband signal processing circuit digital circuit
  • FIG. 1 is a top view showing a conventional example in which an IC chip in which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board (PCB).
  • PCB printed circuit board
  • reference numeral 1 denotes an IC chip, inside which an analog circuit 2 and Digital circuit 3 is mixed.
  • the internal region of the IC chip 1 is divided in the vertical direction, an analog circuit 2 is arranged in one region, and a digital circuit 3 is arranged in the other region.
  • an analog power supply line and a ground line (hereinafter, referred to as an analog power supply line) 4 are arranged along the outer periphery of the IC chip 1.
  • a digital power line and a ground line (hereinafter referred to as a digital power line) 5 are wired around the digital circuit 3 along the outer periphery of the IC chip 1.
  • the IC chip 1 configured as described above is mounted on a conductor 200 provided on the surface of the printed circuit board 100, and is electrically connected by wire bonding or soldering.
  • FIG. 2 is a cross-sectional view showing a conventional example in which an IC chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
  • the IC chip 1 has an analog circuit 2 formed by integrating various elements including a MOS transistor 7 on a silicon substrate 6.
  • various elements including the MOS transistor 8 and the like are integrated on the same silicon substrate 6 to form the digital circuit 3.
  • an analog power supply line 4 of FIG. 1 including an analog ground line 9 and a power supply line (not shown) is wired.
  • a digital power line 5 of FIG. 1 including a digital ground line 10 and a power line (not shown) is provided around the digital circuit 3.
  • the IC chip 1 having such a configuration is mounted on a conductor 200 provided on the surface of the printed circuit board 100, and is electrically connected by wire pond or soldering.
  • the analog ground line 9 and the digital ground line 10 are connected to the conductor 200 of the printed circuit board 100.
  • the conductor portion 200 is optional. (For example, a position near either the analog ground line 9 or the digital ground line 10).
  • the analog circuit 2 and the digital circuit 3 are grounded.
  • a substrate such as the silicon substrate 6 has a resistance.
  • the analog circuit 2 and the digital circuit 3 and the printed circuit board 100 A potential difference is generated in the substrate itself between the substrate and the ground portion, and a current flows to the ground portion of the printed circuit board 100 through the substrate.
  • the present invention has been made in order to solve such a problem.
  • a semiconductor chip in which an analog circuit and a digital circuit are mixed, the current from the analog circuit and the current from the digital circuit are suppressed.
  • the purpose is to prevent the inconvenience of mixing in by flowing through a tray, etc., and to reduce noise for analog or digital signals.
  • a semiconductor device of the present invention is a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board, wherein the conductor of the printed circuit board is a first conductor and By the second conductor Wherein the semiconductor chip is mounted on the first conductor portion and the second conductor portion.
  • the semiconductor chip is mounted such that the analog circuit is disposed on the first conductor, and the digital circuit is disposed on the second conductor.
  • the first conductor and the second conductor are separately grounded.
  • Another aspect of the present invention is characterized in that the first conductor and the second conductor are commonly grounded.
  • a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
  • a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a lead frame. It is characterized by comprising a conductor portion and a second conductor portion, and mounting the semiconductor chip on the first conductor portion and the second conductor portion.
  • the present invention comprises the above technical means, in a semiconductor chip in which an analog circuit and a digital circuit are mixed, the current generated from the analog circuit based on the potential difference in the substrate is transmitted from the first conductor to the ground through the substrate. Flows into On the other hand, the current generated from the digital circuit flows from the second conductor to the ground through the substrate. This allows the current from the analog circuit and the power from the digital circuit The inconvenience that the flow and the flow are mixed through the substrate is prevented.
  • FIG. 1 is a top view showing a conventional example in which an IC chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
  • FIG. 2 is a cross-sectional view showing a conventional example in which an IC chip in which analog circuits and digital circuits are mixed is mounted on a printed circuit board.
  • FIG. 3 is a top view showing the configuration of an IC chip implementing the semiconductor device of the present invention and an example of mounting the IC chip on a printed circuit board.
  • FIG. 4 is a cross-sectional view showing a configuration of an IC chip in which the semiconductor device of the present invention is implemented, and an example of mounting on a printed circuit board.
  • FIG. 3 is a top view showing a configuration example of a semiconductor chip (IC chip) embodying the semiconductor device of the present invention mounted on a printed circuit board.
  • IC chip semiconductor chip
  • the IC chip 1 of the present embodiment includes an analog circuit 2 for processing an analog signal and a digital circuit 3 for processing a digital signal.
  • the internal area of the IC chip 1 is divided in the vertical direction, the analog circuit 2 is arranged in one area, and the digital circuit 3 is arranged in the other area.
  • An analog power supply line 4 (an analog power supply line and a ground line) is wired around the analog circuit 2 along the outer periphery of the IC chip 1.
  • a digital power supply line 5 (digital power supply line and ground line) is wired around the digital circuit 3 along the outer periphery of the IC chip 1.
  • a first conductor section 11 and a second conductor section 12 are provided as conductor sections of a printed circuit board 20 on which the IC chip 1 configured as described above is mounted.
  • the first and second conductor portions 11 and 12 are formed, for example, by providing a slit 21 in the conductor portion of the printed circuit board 20 and dividing the conductor portion into two regions.
  • the IC chip 1 is mounted on the two conductors 11 and 12 so as to straddle them, and is electrically connected to the conductors 11 and 12 by wire bonding or soldering. At this time, the IC chip 1 is preferably mounted at a position where the analog circuit 2 comes above the first conductor 11 and the digital circuit 3 comes above the second conductor 12.
  • FIG. 4 is a cross-sectional view showing the configuration of the IC chip according to the present embodiment and an example of mounting the IC chip on a printed circuit board.
  • an analog circuit 2 is formed by integrating various elements including a MOS transistor 7 on a silicon substrate 6 of an IC chip 1.
  • various elements including a MOS transistor 8 and the like are integrated on the same silicon substrate 6 to form a digital circuit 3.
  • an analog power supply line 4 of FIG. 3 including an analog ground line 9 and a power supply line (not shown) is wired.
  • a digital power line 5 of FIG. 3 including a digital ground line 10 and a power line (not shown) is wired.
  • the IC chip 1 having such a configuration is mounted on the surface of the two conductors 11 and 12 so as to straddle them, and is electrically connected by wire pond or soldering.
  • the analog ground wire 9 is connected to the first conductor portion 11 by, for example, a bonding wire 13
  • the digital ground wire 10 is connected to the second conductor portion 12 by, for example, a bonding wire 14.
  • the current from the analog circuit 2 generated by the potential difference of the silicon substrate 6 flows into the first conductor 11 through the silicon substrate 6, and further flows to the common ground. Further, the current from the digital circuit 3 flows into the second conductor section 12 through the silicon substrate 6, and further flows to the common ground.
  • the conductor of the printed circuit board 20 is divided into two (the first conductor 11 and the second conductor 12).
  • the number of divisions may be more.
  • the conductor of the printed circuit board 20 may be divided into three or more regions in accordance with the division. .
  • first conductor portion and the second conductor portion referred to in the present invention mean, for example, areas respectively corresponding to an analog circuit and a digital circuit, and include the first conductor portion and the second conductor portion. 2 conductor parts themselves Area may be divided. .
  • the present invention is not limited to this.
  • the present invention can be similarly applied to a case where an IC chip is mounted on a lead frame.
  • a current generated from the analog circuit flows from the first conductor through the substrate to the first conductor.
  • the current generated by the digital circuit can flow through the substrate, and can flow from the second conductor portion to the ground through the substrate.
  • the present invention provides an analog-to-digital converter that prevents the inconvenience of current from an analog circuit and current from a digital circuit flowing through a subrate or the like and being mixed, thereby reducing noise with respect to an analog signal or a digital signal. Useful for mixed chips.

Abstract

An IC chip (1) is mounted astride a first conductor section (11) and a second conductor section (12) of a printed circuit board (20), and the conductor sections (11, 12) are grounded to cause the current from an analog circuit (2) based on a potential difference generated in a silicon substrate (6) of the IC chip (1) to flow from the conductor section (11) through the silicon substrate (6) into the ground, and the current from a digital circuit (3) to flow from the conductor section (12) through the silicon substrate (6) into the ground. Thus, the current from the analog circuit (2) and the current from the digital circuit (3) are prevented from mixing through the silicon substrate (6).

Description

明 細 書 半導体装置 技術分野  Description Semiconductor device technology
本発明は半導体装置に関し、 特に、 アナログ回路とデジタル回路とが The present invention relates to a semiconductor device, and more particularly, to an analog circuit and a digital circuit.
1つのチップ内に搭載された半導体装置に用いて好適なものである。 背景技術 It is suitable for use in a semiconductor device mounted in one chip. Background art
ラジオ受信機、 携帯電話装置、 P D A (Personal Digital Assistants ) などの無線通信端末の普及を背景に、 これら端末の小型化、 軽量化な どを目的として I Cの高集積化、 半導体素子の微細化などが急速に進め られている。 このような中、 コンデンサなどの受動部品を含む無線回路 を I C化 （ 1チップ化） する試みも成されている。  With the spread of wireless communication terminals such as radio receivers, mobile phone devices, and PDAs (Personal Digital Assistants), ICs have been highly integrated and semiconductor elements have been miniaturized to reduce the size and weight of these terminals. Is rapidly progressing. Under these circumstances, attempts have been made to make wireless circuits including passive components such as capacitors into ICs (single chip).
また、 最近では、 アナログ回路とデジタル回路とを 1チップの中に混 載したいという要求が高まっている。 例えば、 ラジオ受信機、 携帯電話 装置、 近距離無線データ通信技術のブルートゥース、 無線 L ANなどに おいて、 アナログ信号を送受信するための無線回路 （アナログ回路） と 、 選局用の P L L (Phase Locked Loop) 周波数シンセサイザ回路 （デジ タル回路） や、 送受信する信号をデジタル信号処理するためのベースバ ン ド信号処理回路 （デジタル回路） とを 1チップ化する試みが盛んに行 われている。  Recently, there has been an increasing demand to mix analog and digital circuits in a single chip. For example, a radio circuit (analog circuit) for transmitting and receiving analog signals and a PLL (Phase Locked) for channel selection in radio receivers, mobile phone devices, short-range wireless data communication technology Bluetooth, wireless LAN, etc. Loop) Many attempts have been made to integrate a frequency synthesizer circuit (digital circuit) and a baseband signal processing circuit (digital circuit) for digitally processing signals to be transmitted and received into a single chip.
図 1は、 アナログ回路とデジタル回路とが混載された I Cチップをプ リ ント回路基板 （ P C B) 上に搭載したときの従来例を示す上面図であ る。  FIG. 1 is a top view showing a conventional example in which an IC chip in which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board (PCB).
図 1において、 1は I Cチップであり、 その内部にアナログ回路 2 と デジタル回路 3 とを混載している。 この図 1 の例では、 I Cチップ 1 の 内部領域が縦方向に分割され、 一方の領域にアナログ回路 2が配置され 、 他方の領域にデジタル回路 3が配置されている。 In FIG. 1, reference numeral 1 denotes an IC chip, inside which an analog circuit 2 and Digital circuit 3 is mixed. In the example of FIG. 1, the internal region of the IC chip 1 is divided in the vertical direction, an analog circuit 2 is arranged in one region, and a digital circuit 3 is arranged in the other region.
アナログ回路 2の周囲には、 I Cチップ 1 の外周に沿ってアナログ用 の電源線およびグランド線 （以下、 アナログ電源ラインと言う） 4が配 線されている。 また、 デジタル回路 3の周囲には、 I Cチップ 1 の外周 に沿ってデジタル用の電源線およびグランド線 （以下、 デジタル電源ラ インと言う） 5が配線されている。 このように構成された I Cチップ 1 は、 プリント回路基板 1 0 0の表面に設けられた導体部 2 0 0上に搭載 され、 ワイヤポン ドあるいはハンダ付けなどによつて電気的に接続され ている。  Around the analog circuit 2, an analog power supply line and a ground line (hereinafter, referred to as an analog power supply line) 4 are arranged along the outer periphery of the IC chip 1. A digital power line and a ground line (hereinafter referred to as a digital power line) 5 are wired around the digital circuit 3 along the outer periphery of the IC chip 1. The IC chip 1 configured as described above is mounted on a conductor 200 provided on the surface of the printed circuit board 100, and is electrically connected by wire bonding or soldering.
図 2は、 アナログ回路とデジタル回路とが混載された I Cチップをプ リ ント回路基板上に搭載したときの従来例を示す断面図である。  FIG. 2 is a cross-sectional view showing a conventional example in which an IC chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
図 2に示すように、 I Cチップ 1は、 シリコン基板 6上に M O S トラ ンジス夕 7などを含む各種の素子が集積されてアナログ回路 2が形成さ れている。 また、 同じシリコン基板 6上に M O S トランジスタ 8などを 含む各種の素子が集積されてデジタル回路 3が形成されている。  As shown in FIG. 2, the IC chip 1 has an analog circuit 2 formed by integrating various elements including a MOS transistor 7 on a silicon substrate 6. Various elements including the MOS transistor 8 and the like are integrated on the same silicon substrate 6 to form the digital circuit 3.
アナログ回路 2の周囲には、 アナログ用のグラン ド線 9および図示し ない電源線を含む図 1のアナログ電源ライン 4が配線されている。 また 、 デジタル回路 3の周囲には、 デジタル用のグランド線 1 0および図示 しない電源線を含む図 1 のデジタル電源ライン 5が配線されている。 このような構成から成る I Cチップ 1が、 プリント回路基板 1 0 0の 表面に設けられた導体部 2 0 0上に搭載され、 ワイヤポンドあるいはハ ンダ付けなどによって電気的に接続されている。 このとき、 アナログ用 グランド線 9およびデジタル用グランド線 1 0は、 プリント回路基板 1 0 0の導体部 2 0 0に接続される。 さらに、 当該導体部 2 0 0は、 任意 の位置 （例えば、 アナログ用グランド線 9 またはデジタル用グランド線 1 0の何れかに近い位置） で接地される。 これによつてアナログ回路 2 およびデジタル回路 3のアースがとられている。 Around the analog circuit 2, an analog power supply line 4 of FIG. 1 including an analog ground line 9 and a power supply line (not shown) is wired. A digital power line 5 of FIG. 1 including a digital ground line 10 and a power line (not shown) is provided around the digital circuit 3. The IC chip 1 having such a configuration is mounted on a conductor 200 provided on the surface of the printed circuit board 100, and is electrically connected by wire pond or soldering. At this time, the analog ground line 9 and the digital ground line 10 are connected to the conductor 200 of the printed circuit board 100. Further, the conductor portion 200 is optional. (For example, a position near either the analog ground line 9 or the digital ground line 10). Thus, the analog circuit 2 and the digital circuit 3 are grounded.
一般に、 シリ コン基板 6などのサブス トレートには抵抗があるので、 その上のアナログ回路 2 とデジタル回路 3に電流が流れると、 当該アナ ログ回路 2およびデジタル回路 3 とプリ ント回路基板 1 0 0の接地部分 との間にあるサブス トレート自身に電位差が生じ、 サブストレートを通 じてプリント回路基板 1 0 0の接地部分へと電流が流れてしまう。  Generally, a substrate such as the silicon substrate 6 has a resistance. When a current flows through the analog circuit 2 and the digital circuit 3 thereon, the analog circuit 2 and the digital circuit 3 and the printed circuit board 100 A potential difference is generated in the substrate itself between the substrate and the ground portion, and a current flows to the ground portion of the printed circuit board 100 through the substrate.
この場合、 図 2に示すようにアナログ回路 2の近傍で接地をすると、 デジタル回路 3側からアナログ回路 2側に向かって、 サブストレートや 導体部 2 0 0 を通じて電流が流れ込んできてしまい、 これがアナログ信 号に対するノイズ源となってしまうという問題があった。 逆に、 デジ夕 ル回路 3の近傍において接地した場合は、 アナログ回路 2側からデジ夕 ル回路 3側に向かって電流が流れ込んできてしまい、 これがノイズ源と なってしまう という問題があった。  In this case, if grounding is performed in the vicinity of the analog circuit 2 as shown in FIG. 2, current flows from the digital circuit 3 toward the analog circuit 2 through the substrate and the conductor 200. There was a problem that it became a noise source for the signal. Conversely, if the grounding is performed in the vicinity of the digital circuit 3, a current flows from the analog circuit 2 toward the digital circuit 3 and there is a problem that this becomes a noise source.
本発明は、 このような問題を解決するために成されたものであり、 ァ ナログ回路とデジタル回路とを混載した半導体チップにおいて、 アナ口 グ回路からの電流とデジタル回路からの電流とがサプス 卜レー卜等を通 じて流れ込んで混在してしまう不都合を防止し、 アナログ信号あるいは デジタル信号に対するノイズを低減できるようにすることを目的とする  The present invention has been made in order to solve such a problem. In a semiconductor chip in which an analog circuit and a digital circuit are mixed, the current from the analog circuit and the current from the digital circuit are suppressed. The purpose is to prevent the inconvenience of mixing in by flowing through a tray, etc., and to reduce noise for analog or digital signals.
発明の開示 Disclosure of the invention
本発明の半導体装置は、 アナログ回路とデジタル回路とが混載された 半導体チップをプリ ント回路基板上に実装する半導体装置であって、 上 記プリ ント回路基板の導体部を第 1の導体部および第 2の導体部により 構成し、 上記半導体チップを上記第 1 の導体部および上記第 2の導体部 の上に搭載したことを特徴とする。 A semiconductor device of the present invention is a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board, wherein the conductor of the printed circuit board is a first conductor and By the second conductor Wherein the semiconductor chip is mounted on the first conductor portion and the second conductor portion.
本発明の他の態様では、 上記アナログ回路が上記第 1 の導体部の上に 配置され、 上記デジタル回路が上記第 2の導体部の上に配置されるよう に上記半導体チップを搭載したことを特徴とする。  In another aspect of the present invention, the semiconductor chip is mounted such that the analog circuit is disposed on the first conductor, and the digital circuit is disposed on the second conductor. Features.
本発明のその他の態様では、 上記第 1の導体部おょぴ上記第 2の導体 部のそれぞれを別個に接地したことを特徴とする。  In another aspect of the present invention, the first conductor and the second conductor are separately grounded.
本発明のその他の態様では、 上記第 1 の導体部と上記第 2の導体部と を共通に接地したことを特徴とする。  Another aspect of the present invention is characterized in that the first conductor and the second conductor are commonly grounded.
本発明のその他の態様では、 アナログ回路とデジタル回路とが混載さ れた半導体チップをプリ ント回路基板上に実装する半導体装置であって According to another aspect of the present invention, there is provided a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
、 上記プリント回路基板の導体部にスリ ッ トを設けることにより、 上記 プリ ント回路基板の導体部を少なく とも 2つの領域に分割し、 上記半導 体チップを上記分割したそれぞれの領域上に搭載したことを特徴とする 本発明のその他の態様では、 アナログ回路とデジタル回路とが混載さ れた半導体チップをリードフレーム上に実装する半導体装置であって、 上記リードフレームの導体部を第 1 の導体部および第 2の導体部により 構成し、 上記半導体チップを上記第 1 の導体部および上記第 2の導体部 の上に搭載したことを特徵とする。 By providing a slit in the conductor of the printed circuit board, the conductor of the printed circuit board is divided into at least two areas, and the semiconductor chip is mounted on each of the divided areas. According to another aspect of the present invention, there is provided a semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a lead frame. It is characterized by comprising a conductor portion and a second conductor portion, and mounting the semiconductor chip on the first conductor portion and the second conductor portion.
本発明は上記技術手段より成るので、 アナログ回路とデジタル回路と を混載した半導体チップにおいて、 サブス 卜レートにおける電位差に基 づきアナログ回路から生じた電流は、 サブス トレートを通じて第 1 の導 体部からグランドへと流れ込む。 一方、 デジタル回路から生じた電流は 、 サブス トレー トを通じて第 2の導体部からグランドへと流れ込むよう になる。 これにより、 アナログ回路からの電流とデジタル回路からの電 流とがサブス トレートを通して混在してしまう不都合が防止される。 図面の簡単な説明 Since the present invention comprises the above technical means, in a semiconductor chip in which an analog circuit and a digital circuit are mixed, the current generated from the analog circuit based on the potential difference in the substrate is transmitted from the first conductor to the ground through the substrate. Flows into On the other hand, the current generated from the digital circuit flows from the second conductor to the ground through the substrate. This allows the current from the analog circuit and the power from the digital circuit The inconvenience that the flow and the flow are mixed through the substrate is prevented. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 アナログ回路とデジタル回路とが混載された I Cチップをプ リント回路基板上に搭載した従来例を示す上面図である。  FIG. 1 is a top view showing a conventional example in which an IC chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
図 2は、 アナログ回路とデジタル回路とが混載された I Cチップをプ リ ント回路基板上に搭載した従来例を示す断面図である。  FIG. 2 is a cross-sectional view showing a conventional example in which an IC chip in which analog circuits and digital circuits are mixed is mounted on a printed circuit board.
図 3は、 本発明の半導体装置を実施した I Cチップの構成およびプリ ント回路基板上への実装例を示す上面図である。  FIG. 3 is a top view showing the configuration of an IC chip implementing the semiconductor device of the present invention and an example of mounting the IC chip on a printed circuit board.
図 4は、 本発明の半導体装置を実施した I Cチップの構成およびプリ ント回路基板上への実装例を示す断面図である。 発明を実施するための最良の形態  FIG. 4 is a cross-sectional view showing a configuration of an IC chip in which the semiconductor device of the present invention is implemented, and an example of mounting on a printed circuit board. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の一実施形態を図面に基づいて説明する。  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
図 3は、 本発明の半導体装置を実施した半導体チップ （ I Cチップ） の構成おょぴプリ ント回路基板上への実装例を示す上面図である。  FIG. 3 is a top view showing a configuration example of a semiconductor chip (IC chip) embodying the semiconductor device of the present invention mounted on a printed circuit board.
図 3において、 本実施形態の I Cチップ 1は、 アナログ信号を処理す るアナログ回路 2 と、 デジタル信号を処理するデジタル回路 3 とを備え ている。 この図 3の例では、 I Cチップ 1 の内部領域が縦方向に分割さ れ、 一方の領域にアナログ回路 2が配置され、 他方の領域にデジタル回 路 3が配置されている。  In FIG. 3, the IC chip 1 of the present embodiment includes an analog circuit 2 for processing an analog signal and a digital circuit 3 for processing a digital signal. In the example of FIG. 3, the internal area of the IC chip 1 is divided in the vertical direction, the analog circuit 2 is arranged in one area, and the digital circuit 3 is arranged in the other area.
アナログ回路 2の周囲には、 I Cチップ 1の外周に沿ってアナログ電 源ライン 4 (アナログ用の電源線およびグランド線） が配線されている 。 また、 デジタル回路 3の周囲には、 I Cチップ 1 の外周に沿ってデジ タル電源ライ ン 5 (デジタル用の電源線およびグランド線） が配線され ている。 本実施形態においては、 このように構成された I Cチップ 1 を実装す るプリ ント回路基板 2 0の導体部として、 第 1 の導体部 1 1および第 2 の導体部 1 2 を備えている。 この第 1および第 2の導体部 1 1， 1 2は 、 例えば、 プリ ント回路基板 2 0の導体部にスリ ッ ト 2 1 を設け、 導体 部を 2つの領域に分割することによって形成する。 An analog power supply line 4 (an analog power supply line and a ground line) is wired around the analog circuit 2 along the outer periphery of the IC chip 1. A digital power supply line 5 (digital power supply line and ground line) is wired around the digital circuit 3 along the outer periphery of the IC chip 1. In the present embodiment, a first conductor section 11 and a second conductor section 12 are provided as conductor sections of a printed circuit board 20 on which the IC chip 1 configured as described above is mounted. The first and second conductor portions 11 and 12 are formed, for example, by providing a slit 21 in the conductor portion of the printed circuit board 20 and dividing the conductor portion into two regions.
I Cチップ 1 は、 2つの導体部 1 1 , 1 2の上にこれらを跨ぐように 搭載し、 それぞれの導体部 1 1 , 1 2にワイヤボン ドあるいはハンダ付 けなどによって電気的に接続する。 このとき I Cチップ 1は、 アナログ 回路 2が第 1の導体部 1 1の上にきて、 デジタル回路 3が第 2の導体部 1 2の上にくる位置に搭載するのが好ましい。  The IC chip 1 is mounted on the two conductors 11 and 12 so as to straddle them, and is electrically connected to the conductors 11 and 12 by wire bonding or soldering. At this time, the IC chip 1 is preferably mounted at a position where the analog circuit 2 comes above the first conductor 11 and the digital circuit 3 comes above the second conductor 12.
図 4は、 本実施形態による I Cチップの構成およびプリ ント回路基板 上への実装例を示す断面図である。  FIG. 4 is a cross-sectional view showing the configuration of the IC chip according to the present embodiment and an example of mounting the IC chip on a printed circuit board.
図 4に示すように、 I Cチップ 1 のシリコン基板 6上に M O S トラン ジス夕 7などを含む各種の素子が集積されてアナログ回路 2が形成され ている。 また、 同じシリコン基板 6上に M O S トランジスタ 8などを含 む各種の素子が集積されてデジタル回路 3が形成されている。  As shown in FIG. 4, an analog circuit 2 is formed by integrating various elements including a MOS transistor 7 on a silicon substrate 6 of an IC chip 1. In addition, various elements including a MOS transistor 8 and the like are integrated on the same silicon substrate 6 to form a digital circuit 3.
アナログ回路 2の周囲には、 アナログ用のグラン ド線 9および図示し ない電源線を含む図 3のアナログ電源ライン 4が配線されている。 また 、 デジタル回路 3の周囲には、 デジタル用のグランド線 1 0および図示 しない電源線を含む図 3のデジタル電源ライン 5が配線されている。 このような構成から成る I Cチップ 1が 2つの導体部 1 1， 1 2の表 面上にこれらを跨ぐように搭載され、 ワイヤポンドあるいはハンダ付け などによって電気的に接続されている。 このとき、 アナログ用グラン ド 線 9は、 例えばボンディ ングワイヤ 1 3などによって第 1の導体部 1 1 と接続され、 デジタル用グランド線 1 0は、 例えばボンディ ングワイヤ 1 4によって第 2の導体部 1 2 と接続されている。 これら 2つの導体部 1 1， 1 2は、 それぞれ任意の位置 （例えば、 ァ ナログ用ダランド線 9およびデジタル用ダランド線 1 0に近い位置） か ら外部で共通に接地されている。 なお、 ここでは 2つの導体部 1 1 , 1 2を共通に接地する例を示したが、 それぞれ別個に接地するようにして も良い。 Around the analog circuit 2, an analog power supply line 4 of FIG. 3 including an analog ground line 9 and a power supply line (not shown) is wired. Around the digital circuit 3, a digital power line 5 of FIG. 3 including a digital ground line 10 and a power line (not shown) is wired. The IC chip 1 having such a configuration is mounted on the surface of the two conductors 11 and 12 so as to straddle them, and is electrically connected by wire pond or soldering. At this time, the analog ground wire 9 is connected to the first conductor portion 11 by, for example, a bonding wire 13, and the digital ground wire 10 is connected to the second conductor portion 12 by, for example, a bonding wire 14. Is connected to These two conductors 11 and 12 are commonly grounded from an arbitrary position (for example, a position close to the analog duland line 9 and the digital duland line 10). Here, an example is shown in which the two conductor portions 11 and 12 are grounded in common, but they may be separately grounded.
以上のように構成することにより、 シリコン基板 6の電位差によって 生じたアナログ回路 2からの電流は、 シリコン基板 6を通じて第 1 の導 体部 1 1 に流れ込み、 更に共通アースへと流れる。 また、 デジタル回路 3からの電流は、 シリコン基板 6 を通じて第 2の導体部 1 2に流れ込み 、 更に共通アースへと流れるようになる。  With the configuration described above, the current from the analog circuit 2 generated by the potential difference of the silicon substrate 6 flows into the first conductor 11 through the silicon substrate 6, and further flows to the common ground. Further, the current from the digital circuit 3 flows into the second conductor section 12 through the silicon substrate 6, and further flows to the common ground.
すなわち、 プリ ント回路基板 2 0の導体部 1 1 , 1 2は非常に抵抗が 小さいので、 ここに電位差は殆ど生じない。 したがって、 アナログ回路 2およびデジタル回路 3から生じた電流は、 それぞれが接地された 2つ の導体部 1 1 , 1 2に別々に向かって流れ込み、 導体部 1 1， 1 2の外 部でアースに落とされるようになる。 これにより、 アナログ回路 2およ ぴデジタル回路 3からの電流がプリン卜回路基板 2 0上で混在すること がなくなり、 例えばアナログ信号がデジタルノイズを拾ってしまうよう な不都合をなく してノィズの低減を図ることができる。  That is, since the conductors 11 and 12 of the printed circuit board 20 have extremely low resistance, a potential difference hardly occurs here. Therefore, the currents generated from the analog circuit 2 and the digital circuit 3 separately flow toward the two grounded conductors 11 1 and 12, respectively, and are grounded outside the conductors 1 1 and 1 2. You will be dropped. This prevents currents from the analog circuit 2 and the digital circuit 3 from being mixed on the printed circuit board 20 and, for example, eliminates the inconvenience of analog signals picking up digital noise and reduces noise. Can be achieved.
なお、 上記実施形態では、 プリ ント回路基板 2 0の導体部を 2分割 （ 第 1の導体部 1 1、 第 2の導体部 1 2 ) したが、 分割数はこれ以上であ つても良い。 例えば、 I Cチップ内でアナログ回路とデジタル回路とが 3個以上の領域に分割される場合は、 それに合わせてプリント回路基板 2 0の導体部も 3個以上の領域に分割するようにしても良い。  In the above embodiment, the conductor of the printed circuit board 20 is divided into two (the first conductor 11 and the second conductor 12). However, the number of divisions may be more. For example, when an analog circuit and a digital circuit are divided into three or more regions in an IC chip, the conductor of the printed circuit board 20 may be divided into three or more regions in accordance with the division. .
つまり、 本発明で言う第 1の導体部および第 2の導体部は、 例えばそ れぞれがアナログ回路およびデジタル回路に対応した領域のことを意味 するものであり、 第 1 の導体部および第 2の導体部自身がそれぞれ複数 の領域に分割されていても良い。 . That is, the first conductor portion and the second conductor portion referred to in the present invention mean, for example, areas respectively corresponding to an analog circuit and a digital circuit, and include the first conductor portion and the second conductor portion. 2 conductor parts themselves Area may be divided. .
また、 上記実施形態では、 I Cチップをプリント回路基板上に搭載す る際の例について説明したが、 これに限定されるものではない。 例えば 、 リードフレーム上に I Cチップを搭載する場合にも同様に本発明を適 用することが可能である。  Further, in the above embodiment, the example in which the IC chip is mounted on the printed circuit board has been described, but the present invention is not limited to this. For example, the present invention can be similarly applied to a case where an IC chip is mounted on a lead frame.
その他、 上記に示した実施形態は、 本発明を実施するにあたっての具 体化の一例を示したものに過ぎず、 これによつて本発明の技術的範囲が 限定的に解釈されてはならないものである。 すなわち、 本発明はその精 神、 またはその主要な特徴から逸脱することなく、 様々な形で実施する ことができる。  In addition, the above-described embodiments are merely examples of embodying the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. It is. That is, the present invention can be embodied in various forms without departing from its spirit or its main features.
以上説明したように、 本発明によれば、 アナログ回路とデジタル回路 とが 1つの半導体チップ内に混載した半導体装置において、 アナログ回 路から生じた電流は当該サブス トレートを通じて第 1の導体部からダラ ンドへと流れ込み、 デジタル回路から生じた電流はサブストレートを通 じて第 2の導体部からグランドへと流れ込むようにすることができる。 これにより、 アナログ回路からの電流とデジタル回路からの電流とがサ ブス トレートを通して混在してしまう不都合を防止し、 ノイズの低減を 図ることができる。 産業上の利用可能性  As described above, according to the present invention, in a semiconductor device in which an analog circuit and a digital circuit are mixedly mounted on one semiconductor chip, a current generated from the analog circuit flows from the first conductor through the substrate to the first conductor. The current generated by the digital circuit can flow through the substrate, and can flow from the second conductor portion to the ground through the substrate. As a result, it is possible to prevent the inconvenience that the current from the analog circuit and the current from the digital circuit are mixed through the subrate, and reduce noise. Industrial applicability
本発明は、 アナログ回路からの電流とデジタル回路からの電流とがサ ブス トレート等を通じて流れ込んで混在してしまう不都合を防止し、 ァ ナログ信号あるいはデジタル信号に対するノイズを低減できるようにし たアナログ—デジタル混載チップに有用である。  The present invention provides an analog-to-digital converter that prevents the inconvenience of current from an analog circuit and current from a digital circuit flowing through a subrate or the like and being mixed, thereby reducing noise with respect to an analog signal or a digital signal. Useful for mixed chips.

Claims

請 求 の 範 囲 The scope of the claims
1 . アナログ回路とデジタル回路とが混載された半導体チップをプリ ン ト回路基板上に実装する半導体装置であって、 1. A semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board,
上記プリ ント回路基板の導体部を第 1 の導体部および第 2の導体部に より構成し、 上記半導体チップを上記第 1 の導体部および上記第 2の導 体部の上に搭載したことを特徴とする半導体装置。  The conductor part of the printed circuit board is constituted by a first conductor part and a second conductor part, and the semiconductor chip is mounted on the first conductor part and the second conductor part. Characteristic semiconductor device.
2 . 上記アナログ回路が上記第 1の導体部の上に配置され、 上記デジ夕 ル回路が上記第 2の導体部の上に配置されるように上記半導体チップを 搭載したことを特徴とする請求の範囲第 1項に記載の半導体装置。  2. The semiconductor chip is mounted such that the analog circuit is disposed on the first conductor, and the digital circuit is disposed on the second conductor. 2. The semiconductor device according to item 1.
3 . 上記第 1の導体部おょぴ上記第 2の導体部のそれぞれを別個に接地 したことを特徴とする請求の範囲第 1項に記載の半導体装置。  3. The semiconductor device according to claim 1, wherein each of said first conductor and said second conductor is separately grounded.
4 . 上記第 1の導体部と上記第 2の導体部とを共通に接地したことを特 徵とする請求の範囲第 1項に記載の半導体装置。  4. The semiconductor device according to claim 1, wherein the first conductor and the second conductor are commonly grounded.
5 . アナログ回路とデジタル回路とが混載された半導体チップをプリ ン ト回路基板上に実装する半導体装置であって、  5. A semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a printed circuit board.
上記プリ ント回路基板の導体部にスリ ツ 卜を設けることにより、 上記 プリ ント回路基板の導体部を少なく とも 2つの領域に分割し、 上記半導 体チップを上記分割したそれぞれの領域上に搭載したことを特徴とする 半導体装置。  By providing slits in the conductors of the printed circuit board, the conductors of the printed circuit board are divided into at least two regions, and the semiconductor chip is mounted on each of the divided regions. A semiconductor device characterized by the following.
6 . アナログ回路とデジタル回路とが混載された半導体チップをリ一ド フレ一ム上に実装する半導体装置であって、  6. A semiconductor device in which a semiconductor chip on which an analog circuit and a digital circuit are mixed is mounted on a lead frame,
上記リー ドフレームの導体部を第 1 の導体部および第 2 の導体部によ り構成し、 上記半導体チップを上記第 1 の導体部および上記第 2 の導体 部の上に搭載したことを特徴とする半導体装置。  The conductor portion of the lead frame is constituted by a first conductor portion and a second conductor portion, and the semiconductor chip is mounted on the first conductor portion and the second conductor portion. Semiconductor device.
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